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ZEN2002AP

P ROGRAMMABLE

U N IVE RSAL

COU N TE R

Description

is a 24 bit pr ogr a m m a ble u n iver sa l cou n t er LSI .

ZENIC INC. ZEN2002AP

TH E

cou n t s ph a se-sh ift ed sign a ls a n d u p/down pu lse sign a ls, gen er a t ed fr om r ot a r y en coder s or

ZEN2002AP

lin ea r sca les.

Sin ce t h e cou n t er r espon se speed is a s h igh a s 20MH z(MAX),t h e

is u sed in a va r iet y of h igh speed

ZEN2002AP

ser vices in clu din g digit a l ser vo con t r ol a n d pr ecision m ea su r em en t .

TH E

is pr ovided wit h a fu n ct ion wh ich m on it or s t h e in pu t sign a ls a n d det ect s a n y a bn or m a l in pu t

ZEN2002AP

a ccom pa n ied wit h n oise or ot h er dist u r ba n ces, so t h a t t h e r elia bilit y of cou n t ed va lu es a r e secu r ed.

1, Features

24 bit bin a r y u p/down cou n t er .

Cou n t er r espon se speed:

20MH z.(MAX.) ( CLK f = 20MH z a t 50% du t y)

In pu t fr equ en cy of cou n t pu lse.

P h a se-sh ift ed sign a l in pu t :

A/B ph a se in pu t DC ~ 5MH z.

(less t h a n f

1/4)

U p/down pu lse sign a l in pu t :

U p/down in pu t DC ~ 10MH z

(less t h a n f

1/2)

CLK fr equ en cy DC ~ 20MH z.

(MAX.: du t y r a t io 50%)

Dir ect ion r ecogn it ion for u p/down cou n t in g.

Abn or m a l in pu t det ect ion cir cu it .

P r eloa d r egist er for t h e u p/down cou n t er .

La t ch r egist er for t h e u p/down cou n t er .

Refer en ce va lu e - cou n t va lu e coin ciden ce

det ect ion fu n ct ion .

Mom en t a r y ou t pu t : TTL

In t er r u pt ou t pu t (la t ch ed) : open collect or

On -ch ip st a t u s r egist er .

Cou n t er oper a t ion m ode.

E dge eva lu a t ion select ion : sin gle/dou ble/qu a d

(on ly for ph a se-sh ift ed sign a l in pu t )

Cou n t dir ect ion select ion .

Cou n t er clea r con t r ol:syn ch r on ou s/

a syn ch r on ou s clea r .

F ixed/va r ia ble edge clea r .

8 bit da t a bu s.

Low power CMOS t ech n ology.

TTL com pa t ible.

Sin gle 5V power su pply.

28 pin DIP .

2, Typical Applications

N C m a ch in e t ools

P r ecision posit ion er s

Robot a r m con t r oller s

Speed con t r oller s for r ot a t in g m a ch in es

E lect r on ic ga u ges

F r equ en cy cou n t er s

Pin configuration

(Top view)

VSS

VDD

CLK

INT

RESET

UD/AB

C/D

DIR

VSS

A/UP

B/DN

Z/CLR

VSS

VDD

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ZEN2002AP

4, Block function

1) Up/down counter

It is presettable up/down binary counter of 24 bit length.

The count value can be read out from the latch register via the data bus without influencing to the count operation.

The counter value is initialized by loading the preload register(24bits) or via the data bus every 8 bits.

2) Reference register

It is a writing register of 24 bit length.

The written data is compared by the comparator with the count value of the up/down counter.

3) Comparator

It is a digital comparator of 24 bit length.

The data of the reference register is always compared with the counter value of the up/down counter and the result is

output to EQ(26Pin), the status register, and the interruption control logic.

4) Preload register

It is a data register of 24 bit length.

Its data is loaded into the up/down counter by the external signal LD(8Pin) or the command(load instruction).

5) Latch register

It is a data register only for reading 24 bit length.

It latch the count value of the up/down counter by the external signal LT(9Pin) or the command(latch instruction).

6) Command register

It is a register for the command writing. ( 8 bits )

The controls of loading instruction, latch instruction, count clear control, and register (byte) selection and count mode

changes, etc. are done by using this register.

7) Status register

It is a register for the status reading. ( 8 bits )

It monitors the state of abnormal input detection, the state of input signal(A,B,Z), the state of the latch register,

count direction, the state of coincidence detection(count value = preset value), and the state of interruption output

(INT).

8) Phase distcrimination logic

The count pulse for the up/down counter is generated from the input signal of A/UP(22Pin) and B/DN(21Pin).

9) Control logic

The read/write timing control, the decoding about the command data, and the status flag control.

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ZEN2002AP

5, Pin Description

Pin No.

Signal

I/O

Function

CLK

System clock

RESET

System reset

Up/down counter, phase discrimination logic, command register

and the status register are initialized.

Chip enable

C/D

Command/data select

"High":command/status

"Low":data

Read strobing

Write strobing

Data loading

The data of the preload register is loaded to the up/down counter

Count data latch

The count value of the up/down counter is latched to the latch register.

I/O

Data bus

Bidirectional data bus ( 8 bits ).

It is used to transmit and receive the command, status and data.

Z/CLR

Counter clear

B/DN

Count pulse input B

A/UP

Count pulse input A

DIR

Count direction selection

UD/AB

Input signal selection

Selection up/down or phase-shifted pulse

Coincidence detection output

Coincidence detection output of count value and preset value of reference register.

INT

Interruption output

When the coincidence of the count value and the preset value is detected, it outputs.

It maintains to reset or the reset command execution.

VSS

Power supply ( 5v )

VDD

Ground ( 0v )

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ZEN2002AP

6, Basic operation

The read/write operation is selected according to CE, C/D, RD, and WR.

C/D

Operation

Disable

The data reading

The data writing

Status reading

Command writing

1) Selection of count pulse input

UD/AB

Input pulse signal

A/UP

B/DN

Up/down pulse

Up pulse

Down pulse

Phase-shifted pulse

Phase-A pulse

Phase-B pulse

2) Access pointer

The internal register is selected by setting the access pointer of the command register. Once setting the pointer,

it is incremented automatically after reading or writing 1 byte data. ( automatical increment function )

3) Abnormal input detection

The function is to check whether it is normal state transition () when the phase-shifted pulse is input.

When the abnormal state transition happens , D7 of the status register becomes "H".

: noamal transition

: abnormal transition

Example of causing abnormal

When it is not possible to sample signal accurately

because the pulse input frequency exceeded 1/4 of the system clock frequency.

b. When you pick up noise.

4) Selection of count edge ( C = count , nc = no count )

Up/down pulse input

Single

Phase-shifted pulse input

( CW (phase-A preceding))

( CCW (phase-B preceding))

Single

nc nc nc

Single

nc nc

Double

C nc

Double

nc C

Quad

ZENIC Inc.

Электронный компонент: ZEN2002AP