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ZEN2044F

PROGRAMMABLE UNIVERSAL COUNTER

DESCRIPTION

The

is a 24bit x 4ch. programmable universal counter LSI. The

can count

ZEN2044F

phase-shifted pulse signals or up/down pulse signals generated from rotary encoders or linear scales.

Since the counter response speed is as high as 33MHz(MAX), the

can be used in a variety of

ZEN2044F

applications required high speed counting, including digital servo controls and precision measurements. As

ZEN2044F

ZEN2011P.

to command sets, the

has a compatibility with the

The

can also monitor input signals and detect any abnormal input accompanied with noise or

ZEN2044F

other disturbances, so that the reliability of counted values are secured.

1. Features

24bit binary up/down counter x 4ch.
Counter response speed:

33MHz(MAX)(CLK fo=33MHz at 50% duty)

Input frequency of count pulse

Two phase-shifted pulse signal input:

DC-8.25MHz (less than fo x 1/4)

Up/down pulse signal input:

DC-16.5MHz (less than fo x 1/2)

Direction recognition for up/down count
Abnormal input detection circuit
Preload register for the up/down counter
Latch register for the up/down counter
Coincidence detection between reference value and count value
Counter operation mode

Quad/double/single edge evaluation(for two phase-shifted signal / single pulse signal)
Counter direction selection
Count clear control: synchronous/asynchronous

Command mode

Mode 0:

Each channel has one comparator for coincidence detection
Each channel has one port for user input

Mode 1:

Each channel has two comparators for coincidence detection
Each channel has no port for user input
Logical sum output of coincidence detections available
Interrupt output under some conditions available

8bit data bus
Low power CMOS technology
TTL level compatible input
Single 5V power supply
100 pin QFP

Note ) In following chapters;

" " corresponds to a number of the channel(0-3).

"*" stands for "Don't care".

Pin Configuration(Top View)

100

UD/AB2

DIR2

Vdd

Vss

Vdd

SEL30

EXTA3

EXTB3

Z/CLR2

LD3

B/DN3

Vss

SEL0

L01

L02

Vss

RESET

Vdd

n.c.

A/UP0 B/DN

Z/CLR

UD/AB

Vss C/D

D/CE0

D/CE1

D/CE2

D/CE

DRCTC

LD0

n.c.

Vss

TEST1

TEST0

Vss

Vdd

A/UP3

Vdd

Vss

n.c.

Vdd

n.c.

UD/

AB3

IR3 Vss

EXTB0 EXTA0

Vdd

SEL32

Vss

DN2

UP2

SEL22 SEL21 SEL20 LT2 LD2 Vss EXTA

TB2

CLK Vss DIR1 UD/AB1 Z/CLR1 B/DN

A/UP

n.c

SEL10 LT1 LD1 Vdd EXTA1 EXTB

Vss

LT0

TEST

IR0 n.c.

L11

L12

Vss

LT3

SEL31

Z/CLR3

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ZEN2044F

2. Block diagram

DRCTCE

Ch.0

AD/CE[3:0]

CPU

C/D

I/F

Status

Mode0,1

EXTA

EXTA0

C/D

reg.

function

EXTB

EXTB0

Command wr

(8bit)

control

decoder

Reference

Comparator

LT0

reg.A(24bit)

A(24bit)

LD0

Reference

Comparator

SEL0[2:0]

SEL[2:0]

reg.B(24bit)

B(24bit)

UD/AB0

UD/AB

Up/down

Latch

DIR0

DIR

Direction

counter

reg.(24bit)

A/UP0

A/UP

recognition

(24bit)

B/DN0

B/DN

for up/down

Z/CLR0

Z/CLR

Preload reg.

(24bit)

D[7:0]

cnt0

Ch.1

EXTA

EXTA1

C/D

EXTB

EXTB1

LT1

LD1

SEL1[2:0]

SEL[2:0]

UD/AB1

UD/AB

DIR1

DIR

A/UP1

A/UP

B/DN1

B/DN

Z/CLR1

Z/CLR

D[7:0]

Ch.2

Ch.3

EXTA

EXTA2

EXTA

EXTA3

C/D

EXT

EXTB2

C/D

EXTB

EXTB3

LT2

LT3

LD2

LD3

SEL2[2:0]

SEL[2:0]

SEL3[2:0]

SEL[2:0]

UD/AB2

UD/AB

UD/AB3

UD/AB

DIR2

DIR

DIR3

DIR

A/UP2

A/UP

A/UP3

A/UP

B/DN2

B/DN

B/DN3

B/DN

Z/CLR2

Z/CLR

Z/CLR3

Z/CLR

CLK

D[7:0]

RESET

Vdd

Vss

Z2044G00 ZENIC INC.

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Z2044G00 ZENIC INC.

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ZEN2044F

3. Pin description

Table 1

Name

No.

I/O

Function

EXTA0

The function of this output depends on the command mode. In Mode

EXTA1

0, EXTA

outputs the equal signal A(EQA ). In Mode 1, one of the

EXTA2

following three signals can be selected:

EXTA3

-The equal signal A(EQA ).

-The logical sum(EQA +EQB ) of the equal signal A(EQA ) and

the equal signal B(EQB ).

-The hold equal signal A(INTEQA ).

CLK

The CLK synchronizes the internal circuit operation.

RESET

The RESET initializes the up/down counter, the phase
discrimination circuit, the command register and the status register.

AD/CE0

The function of these pins depends on the DRCTCE. If DRCTCE="1",

AD/CE1

they are all treated as signals for enabling the channel directly. If

AD/CE2

DRCTCE="0",AD/CE3 and AD/CE2 are the chip enable pins and

AD/CE3

AD/CE1 and AD/CE0 are used to select the channnel.

DRCTCE

The DRCTCE specifies the mode of the channel select.

C/D

The C/D defines the type of the data transfered between the CPU
and the ZEN2044F(command or value). This pin is usually connected
with LSB of the address lines.

The RD is the strobe signal of the read operation.

The WR is the strobe signal of the write operation.

LD0

The LD

transmits the 32bit data which is stored in the preload

LD1

LD2

LD3

LT0

The LT

stores the 32bit data of the up/down counter into the latch

LT1

LT2

LT3

I/O

These pins are connected with CPU data bus.

EXTB0

I/O

In Mode 0, EXTB

is used as a general purpose input U of which

EXTB1

value can be read from the status register. In Mode 1, EXTB

is a

EXTB2

programable output. One of the following three signals can be

EXTB3

selected:

-The equal signal B(EQB )

-The signal that indicates detecting an abnormal input(INTAI )

-The hold equal signal B(INTEQB )

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Z2044G00 ZENIC INC.

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ZEN2044F

Name

No.

I/O

Function

Z/CLR0

The Z/CLR clears the value of the up/down counter. This pin is

Z/CLR1

usually connected with the index signal of a rotary encoder or a

Z/CLR2

linear scale.

Z/CLR3

B/DN0

The B/DN is the count pulse input B or DN.

B/DN1

B/DN2

B/DN3

A/UP0

The A/UP is the count pulse input A or UP.

A/UP1

A/UP2

A/UP3

SEL00

The condition of these three pins(SEL 0, SEL 1 and SEL 2)

SEL01

specifies the counter operation mode. See the Table 4.

SEL02

SEL10

SEL11

SEL12

SEL20

SEL21

SEL22

SEL30

SEL31

SEL32

DIR0

The DIR selects the count direction of the up/down counter.

DIR1

DIR2

DIR3

UD/AB0

The UD/AB selects the input pulse mode(up/down or not).

UD/AB1

UD/AB2

UD/AB3

Vss

Ground(0V)

15
24
32
40
46
49
51
66
72
78
87
90
95

Электронный компонент: ZEN2044F