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Электронный компонент: ZNBG2000

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DEVICE DESCRIPTION
The ZNBG series of devices are designed to meet the
bias requirements of GaAs and HEMT FETs
commonly used in satellite receiver LNBs, PMR,
cellular telephones etc. with a minimum of external
components.
With the addition of two capacitors and a resistor the
devices provide drain voltage and current control for
2 external grounded source FETs, generating the
regulated negative rail required for FET gate biasing
whilst operating from a single supply. This negative
bias, at -3 volts, can also be used to supply other
external circuits.
The ZNBG2000/1 contains two bias stages. A single
resistor allows FET drain current to be set to the
desired level. The series also offers the choice of
drain voltage to be set for the FETs, the ZNBG2000
gives 2.2 volts drain whilst the ZNBG2001 gives 2
volts.
These devices are unconditionally stable over the full
working temperature with the FETs in place, subject
to the inclusion of the recommended gate and drain
capacitors. These ensure RF stability and minimal
injected noise.
FEATURES
Provides bias for GaAs and HEMT FETs
Drives up to two FETs
Dynamic FET protection
Drain current set by external resistor
Regulated negative rail generator requires only 2
external capacitors
Choice in drain voltage
Wide supply voltage range
MSOP surface mount package
It is possible to use less than the devices full
complement of FET bias controls, unused drain and
gate connections can be left open circuit without
affecting operation of the remaining bias circuits.
In order to protect the external FETs the circuits have
been designed to ensure that, under any conditions
including power up/down transients, the gate drive
from the bias circuits cannot exceed the range -3.5V
to 0.7V. Furthermore if the negative rail experiences a
fault condition, such as overload or short circuit, the
drain supply to the FETs will shut down avoiding
excessive current flow.
The ZNBG2000/1 are available in MSOP10 packages
for the minimum in devices size. Device operating
temperature is -40 to 80C to suit a wide range of
environmental conditions.
APPLICATIONS
Satellite receiver LNBs
Private mobile radio (PMR)
Single in single out C Band LNB
Cellular telephones
ISSUE 1 - AUGUST 2001
FET BIAS CONTROLLER
ZNBG2000
ZNBG2001
1
ISSUE 1 - AUGUST 2001
ZNBG2000
ZNBG2001
2
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.6V to 15V
Supply Current
100mA
Drain Current (per FET)
0 to 15mA
(set by R
CAL1
and R
CAL2
)
Output Current
100mA
Operating Temperature
-40 to 80C
Storage Temperature
-40 to 85C
Power Dissipation (T
amb 25 C)
MSOP10
500mW
SYMBOL PARAMETER
CONDITIONS
LIMITS
UNITS
Min
Typ
Max
V
CC
Supply Voltage
5
12
V
I
CC
Supply Current
I
D1
and I
D2=0
I
D1
and I
D2
=10mA
5
24
10
30
mA
mA
V
SUB
Substrate Voltage
(Internally generated)
I
SUB
= 0
I
SUB
= -200
A
-3.5
-2.8
-2
-2
V
V
E
ND
E
NG
Output Noise
Drain Voltage
Gate Voltage
C
G
=4.7nF, C
D
=10nF
C
G
=4.7nF, C
D
=10nF
0.02
0.005
Vpkpk
Vpkpk
f
O
Oscillator Freq.
150
330
800
kHz
DRAIN CHARACTERISTICS
I
DO
Output Current Range
Set by R
CAL1
0
15
mA
I
D
Current
8
10
12
mA
Current Change
I
DV
with V
CC
V
CC
=5 to 12V
0.5
%/V
I
DT
with T
j
T
j
=-40 to +80C
0.05
%/C
V
D
Voltage
ZNBG2000
ZNBG2001
I
D1
and I
D2
=10mA
2
1.8
2.2
2
2.4
2.2
V
V
Voltage Change
V
DV
with V
CC
V
CC
= 5 to 12V
0.5
%/V
V
DT
with T
j
T
j
= -40 to +80C
50
ppm
GATE CHARACTERISTICS
I
GO
Output Current Range
-40
2000
A
Output Voltage
V
OL
Output Low
I
D1
and I
D2
=12mA
IG1
and I
G2
=0
-3.5
-2
V
I
D1
and I
D2
=12mA
I
G1
and I
G2
= -10
A
-3.5
-2
V
V
OH
Output High
I
D1
and I
D2
= 8mA
I
G1
and I
G2
= 0
0.4
1
V
Notes:
1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, C
NB
and C
SUB
, of 47nF are required for this
purpose.
2. The characteristics are measured using an external reference resistors R
CAL1
of value 16k
wired from pin R
CAL1
to ground.
3. Noise voltage is not measured in production.
4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs. C
G
, 4.7nF, are connected between gate outputs and
ELECTRICAL CHARACTERISTICS TEST CONDITIONS (Unless otherwise
ISSUE 1 - AUGUST 2001
ZNBG2000
ZNBG2001
3
5
JFET Drain Current v Rcal
0
10
20
30
50
0
2
4
6
8
10
Rcal (k)
Dra
i
n
Cur
re
nt
(m
A)
40
12
14
16
Vcc = 5V
JFET Drain Voltage v Drain Current
2
4
6
8
16
2.0
2.1
2.2
Drain Current (mA)
Dra
i
n
V
oltage
(V)
10
2.3
2.4
12
14
Vcc = 5V
6V
8V
10V
Vsub v External Load
0
0.2
0.4
0.6
1.0
-3.0
-2.5
-2.0
-1.5
-1.0
External Vsub Load (mA)
Vsub
(V)
0.8
-0.5
0.0
Vcc = 5V
6V
8V
10V
Drain Current (mA)
JFET Drain Voltage v Drain Current
Dra
i
n
V
oltage
(V)
4
1.8
2
2.0
1.9
6
8
Vcc = 5V
10V
8V
6V
2.2
2.1
10
12
14
16
Note:- Operation with loads > 200
A
is not guaranteed.
ZNBG2001
ZNBG2000
TYPICAL CHARACTERISTICS
FUNCTIONAL
DESCRIPTION
The ZNBG devices provide all the bias requirements
for external FETs, including the generation of the
negative supply required for gate biasing, from the
single supply voltage.
The diagram above shows a single stage from the
ZNBG series. The ZNBG2000/1 contains 2 such
stages.
The drain voltage of the external FET Q
N
is set by the
ZNBG device to its normal operating voltage. This is
determined by the on board V
D
Set reference, for the
ZNBG2000 this is nominally 2.2 volts whilst the
ZNBG2001 provides nominally 2 volts.
The drain current taken by the FET is monitored by
the low value resistor I
D
Sense. The amplifier driving
the gate of the FET adjusts the gate voltage of Q
N
so
that the drain current taken matches the current
called for by an external resistor R
CAL
. Both ZNBG
devices have the facility to program different drain
currents into selected FETs.
Since the FET is a depletion mode transistor, it is
usually necessary to drive its gate negative with
respect to ground to obtain the required drain
current. To provide this capability powered from a
single positive supply, the device includes a low
current negative supply generator. This generator
uses an internal oscillator and two external
capacitors, C
NB
and C
SUB
.
ISSUE 1 - AUGUST 2001
4
ZNBG2000
ZNBG2001
FUNCTIONAL DIAGRAM
7
APPLICATIONS
INFORMATION
The above is a partial application circuit for the ZNBG
series showing all external components required for
appropriate biasing. The bias circuits are
unconditionally stable over the full temperature
range with the associated FETs and gate and drain
capacitors in circuit.
Capacitors C
D
and C
G
ensure that residual power
supply and substrate generator noise is not allowed
to affect other external circuits which may be
sensitive to RF interference. They also serve to
suppress any potential RF feedthrough between
stages via the ZNBG device. These capacitors are
required for all stages used. Values of 10nF and 4.7nF
respectively are recommended however this is
design dependent and any value between 1nF and
100nF could be used.
The capacitors C
NB
and C
SUB
are an integral part of
the ZNBGs negative supply generator. The negative
bias voltage is generated on-chip using an internal
oscillator. The required value of capacitors C
NB
and
C
SUB
is 47nF. This generator produces a low current
supply of approximately -3 volts. Although this
generator is intended purely to bias the external
FETs, it can be used to power other external circuits
via the C
SUB
pin.
Resistor R
CAL1
sets the drain current at which all
external FETs are operated. If any bias control circuit
is not required, its related drain and gate connections
may be left open circuit without affecting the
operation of the remaining bias circuits. If all FETs
associated with a current setting resistor are omitted,
the particular R
CAL
should still be included. The
supply current can be reduced, if required, by using a
high value R
CAL
resistor (e.g. 470k).
The ZNBG devices have been designed to protect the
external FETs from adverse operating conditions.
With a JFET connected to any bias circuit, the gate
output voltage of the bias circuit can not exceed the
range -3.5V to 0.7V, under any conditions including
powerup and powerdown transients. Should the
negative bias generator be shorted or overloaded so
that the drain current of the external FETs can no
longer be controlled, the drain supply to FETs is shut
down to avoid damage to the FETs by excessive
drain current.
The following diagram show the ZNBG2000/1 in
typical LNB applications.
ISSUE 1 - AUGUST 2001
ZNBG2000
ZNBG2001
5
16k
TYPICAL APPLICATION CIRCUIT
8
ISSUE 1 - AUGUST 2001
6
ZNBG2000
ZNBG2001
9
ZNBG2000/1
INFORMATION CONT.
APPLICATIONS
Part Number
Package
Part Mark
QTY Reel
ZNBG2000X10
MSOP10
ZNBG2000
4000
ZNBG2001X10
MSOP10
ZNBG2001
4000
ORDERING INFORMATION
G1
GND
CNB1
VCC
D2
RCAL
G2
ZNBG2000/01 Pinout For MSOP10
Package Designator - X
1
D1
CNB2
CSUB
ISSUE 1 - AUGUST 2001
Zetex plc
Fields New Road
Chadderton
Oldham, OL9 8NP
United Kingdom
Telephone (44) 161 622 4422
Fax: (44) 161 622 4420
Zetex GmbH
Streitfeldstrae 19
D-81673 Mnchen
Germany
Telefon: (49) 89 45 49 49 0
Fax: (49) 89 45 49 49 49
Zetex Inc
Suite 315
700 Veterans Memorial Highway
Hauppauge NY11788
USA
Telephone: (631) 360 2222
Fax: (631) 360 8222
Zetex (Asia) Ltd
3701-04 Metroplaza, Tower 1
Hing Fong Road
Kwai Fong, Hong Kong
China
Telephone: (852) 26100 611
Fax: (852) 24250 494
These offices are supported by agents and distributors in major countries world-wide.
This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or
reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services
concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or
service.
For the latest product information, log on to
www.zetex.com
Zetex plc 2001
ZNBG2000
ZNBG2001
7
F
E
D
B
A
K
H
G
C
a
PACKAGE DIMENSIONS
DIM
Millimetres
tol.
DIM
Millimetres
tol.
A
1.10
MAX.
F
4.9
0.15
B
0.23
+0.07
-0.08
G
0.55
0.15
C
0.18
60.05
H
3.00
0.1
D
0.50
BSC
K
0.10
0.05
E
3.00
60.1
a
3.0
3.0