Document Outline
- Table of Contents
- List of Figures
- List of Tables
- Overview
- General Description
- Pin Descriptions
- Z85C30/Z80C30 Common Pin Functions
- CTSA, CTSB
- DCDA, DCDB
- DTR/REQA, DTR/REQB
- IEI
- IEO
- INT
- INTACK
- PCLK
- RxDA, RxDB
- RTxCA, RTxCB
- RTSA, RTSB
- SYNCA, SYNCB
- TxDA, TxDB
- TRxCA, TRxCB
- W/REQA, W/REQB
- Z85C30
- Z80C30
- Functional Description
- Electrical Characteristics
- Packaging and Ordering
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6 Bits
8 Bits
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Bit 7 Bit 6
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FIFO Enable
RR7 D5-D0 + RR6 D7-D0
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FIFO Overflow Status Bit
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1
1
0
1
1
0
0
0
1
1
0
1
1
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Null Code
Null Code
Null Code
Null Code
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Reset Rx CRC Checker
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Reset Tx Underrun/EOM Latch
Reset Ext/Status Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
Select Shift Left Mode
Select Shift Right Mode
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
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Write Register 0 (multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 0 (non-multiplexed bus mode)
Null Code
0
0
0
1
1
0
1
1
* With Point High Command
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Null Code
Point High
Reset Ext/Status Interrupts
Send Abort (SDLC)
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 1
0
0
0
0
1
1
1
1
Ext Int Enable
Tx Int Enable
Parity is Special Condition
Rx Int on Special Condition Only
Int on all Rx Characters or Special Condition
Rx Int on First Character or Special Condition
WAIT/DMA Request on
Receive /Transmit
Rx Int Disable
WAIT/DMA Request Function
WAIT/DMA Request
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 2
V0
V1
V2
V3
V4
V5
V6
V7
Interrupt
Vector
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 3
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
0
0
0
0
1
1
1
1
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
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Write Register 4
Parity Enable
Parity EVEN/ODD
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Sync Modes Enable
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 5
0
0
0
0
1
1
1
1
Tx CRC Enable
RTS
SDLC/CRC-16
Tx Enable
Send Break
DTR
Tx 5 Bits (or Less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
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Write Register 6
Sync7
Sync1
Sync7
Sync3
ADR7
ADR7
Sync6
Sync0
Sync6
Sync2
ADR6
ADR6
Sync5
Sync5
Sync5
Sync1
ADR5
ADR5
Sync4
Sync4
Sync4
Sync0
ADR4
ADR4
Sync3
Sync3
Sync3
1
x
ADR3
Sync2
Sync2
Sync2
1
x
ADR2
Sync1
Sync1
Sync1
1
x
ADR1
Sync0
Sync0
Sync0
1
x
ADR0
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
SDLC (Address Range)
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 7
Sync7
Sync5
Sync15
Sync11
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
0
Sync6
Sync4
Sync14
Sync10
1
Sync5
Sync3
Sync13
Sync9
1
Sync4
Sync2
Sync12
Sync8
1
Sync3
Sync1
Sync11
Sync7
1
Sync2
Sync0
Sync10
Sync6
1
Sync1
x
Sync9
Sync5
1
Sync0
x
Sync8
Sync4
0
D7 D6 D5 D4 D3 D2 D1 D0
WR 7' Prime (85C30 only)
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivation
Force TxD High
DTR/REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)
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0
0
0
0
1
1
1
1
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9
No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
VIS
NV
DLC
MIE
Status High/Status Low
Software INTACK Enable
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9
0
0
0
0
1
1
1
1
NRZ
NRZI
FM1 (Transition = 1)
FM1 (Transition = 0)
CRC Preset I/O
Go Active on Poll
Mark/Flag Idle
Abort/Flag on Underrun
Loop Mode
6-Bit/8-Bit Sync
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 11
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TRxC Out = Xtal Output
TRxC Out = Transmit Clock
TRxC Out = BR Generator Output
TRxC Out = DPLL Output
TRxC O/I
Transmit Clock = RTxC Pin
Transmit Clock = TRxC Pin
Transmit Clock = BR Generator Output
Transmit Clock = DPLL Output
Receive Clock = RTxC Pin
Receive Clock = TRxC Pin
Receive Clock = BR Generator Output
Receive Clock = DPLL Output
RTxC Xtal/No Xtal
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Lower Byte of
Time Constant
Upper Byte of
Time Constant
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 13
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 14
BR Generator Enable
BR Generator Source
DTR/Request Function
Auto Echo
Local Loopback
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source = RTxC
Set FM Mode
Set NRZI Mode
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 15
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
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Read Register 0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 1
All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error
Rx Overrun Error
CRC/Framing Error
End of Frame (SDLC)
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 2
V0
V1
V2
V3
V4
V5
V6
V7
Interrupt
Vector *
* Modified in B Channel
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 12
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Lower Byte
of Time Constant
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 10
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clocks Missing
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 3
Channel B Ext/Status IP
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Status IP
Channel A Tx IP
Channel A Rx IP
0
0
*
* Always 0 in B Channel
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TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
Upper Byte
of Time Constant
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 15
0
Zero Count IE
0
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
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