ChipFind - документация

Электронный компонент: Z84C9010ASC

Скачать:  PDF   ZIP

Document Outline

ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432
Telephone: 408.558.8500 Fax: 408.558.8300
http://www.ZiLOG.com
Product Specification
PS011802-0902
Z84C90
KIO Serial/Parallel Counter
Timer
PS011802-0902
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or
to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty
and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no
warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No licenses are
conveyed, implicitly or otherwise, by this document under any intellectual property rights.
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
iii
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Precautions & Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
iv
List of Figures
Figure 1.
KIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2.
Z84C90 84-Pin PLCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3.
100-Pin LQFP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4.
Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5.
PIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.
PIA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7.
CTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8.
Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9.
SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. I/O Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Serial I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Counter/Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Port I/O Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Op Code Fetch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
v
List of Tables
Table 1.
Z84C90 KIO Serial/Parallel/Counter/TimerPackages . . . . . . . . . . . . . . . . . . 1
Table 2.
KIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3.
DC Characteristics of the Z84C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4.
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5.
AC Characteristics of the Z84C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6.
Daisy Chain Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
1
Z84C90
KIO Serial/Parallel Counter/Timer
Product Specification
Features
General Description
ZiLOG's Z84C90 Serial/Parallel/Counter/Timer KIO is a multi-channel, multipurpose I/O
device designed to provide the end-user with a cost-effective and powerful solution to
meet peripheral needs. The Z84C90 combines the features of one Z84C30 CTC, one
Z84C20 PIO, a Z84C4x SIO, a 8-bit, bit-programmable I/O port, and a crystal-oscillator
into a single package (84-pin PLCC or 100-pin LQFP). Using fifteen internal registers for
data and programming information, the KIO can easily be configured to any given system
environment. Although the optimum performance is obtained with a Z84C00 CPU, the
KIO can just as easily be used with any other CPU.
Table 1. Z84C90 KIO Serial/Parallel/Counter/Timer Packages
Part Number
Package
Frequency (MHz)
Z84C9008ASC
100-pin LQFP
8
Z84C9010ASC
100-pin LQFP
10
Z84C9008VEC
84-pin PLCC
8
Z84C9008VSC
84-pin PLCC
8
Z84C9010VSC
84-pin PLCC
10
Z84C9012VSC
84-pin PLCC
12
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
2
Figure 1. KIO Block Diagram
Oscillator
Bus
Interface
and
Control
Interrupt
Control
PIO
PIA/
MUX
SIO
CTC
OSC
XTAL
1
XTAL
0
CLKOUT
D
0
-D
7
A
0
-A
3
CS
MI
RD
IORQ
RESET
CLK
INT
IE1
IE0
PA
0
-PA
7
ARDY
ASTB
PB
0
-PB
7
BRDY
BSTB
PC
0
-PCV
RXDA
RXCA
TXDA
TXCA
CTSA
DCDA
RXDB
RXCB
TXDB
TXCB
CTSB
DCDB
ZC/TO
0
CLK/TRG
0
ZC/TO
1
CLK/TRG
1
ZC/TO
2
CLK/TRG
2
ZC/TO
3
CLK/TRG
3
DA
T
A
B
U
S
CONT
ROL
B
U
S
INT
E
RRU
P
T
BUS
M
O
DEM
CO
NT
RO
L
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
3
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This rating is a stress rating only. Operation of the device at any
condition above those indicated in the operational sections of these specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Voltage on V
CC
with respect to V
SS
0.3V to +7.0V
Voltages on all inputs with respect to
V
SS
0.3V to V
CC
+0.3V
Operating Ambient Temperature
See Ordering
Information
Storage Temperature
65 C to +150 C
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
4
Pin Types
Figure 2. Z84C90 84-Pin PLCC Configuration
84-Pin PLCC
CLK/TRG2
CLK/TRG1
CLK/TRG0
D7
D6
D5
D4
GND
VCC
D3
D2
D1
D0
VCC
XTAL
1
XTAL
0
GND
CLOCK
CLKOUT
OSC
INT
PC1 (SYNCB)
PC2 (DTRB)
PC3 (RTSB)
TxDA
TxCA
RxCA
RxDA
PA0
PA1
PA2
V
CC
PA3
GND
PA4
PA5
PA6
PA7
PC4 (RTSA)
PC5 (DTRA)
PC6 (SYNCA)
PC7 (WT/RDYA)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
PCO
(WT
/RDYB
)
GN
D
CTSA
DCD
A
DCD
B
CTSB
TxDB
TxCB
Rx
CB
Rx
DB
A0
A1
A2
A3
CS
M1
RD
V
CC
IO
RQ
RESET
CL
K/TRG3
GN
D
GN
D
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
BRDY
BSTB
ARDY
ASTB
ZC/T
O
3
ZC/T
O
2
ZC/T
O
1
ZC/T
O
0
IE
1
IE
0
V
CC
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
5
Figure 3. 100-Pin LQFP Configuration
Pin Descriptions
A0A3. Address bus (inputs). Used to select the port/register for each bus cycle.
ARDY, BRDY. Port Ready (outputs, Active High). These signals indicate that the port is
ready for a data transfer. In Mode 0, the signal indicates that the port has data available to
the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data
from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for
the peripheral device, but that the data is not be placed onto PA0PA7 until the ASTB sig-
nal is Active. BRDY indicates that Port A is able to accept data from a peripheral device.
100-Pin LQFP
1
5
10
15
20
25
26
30
35
40
45
50
51
55
60
65
70
75
76
80
85
90
95
100
NC
NC
GND
GND
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
BRDY
BSTB
ARDY
ASTB
ZC/TO3
ZC/TO2
ZC/TO1
ZC/TO0
IE1
IE0
V
CC
NC
NC
NC
NC
PC1
(
SYNCB
)
PC2
(
D
TRB
)
PC3
(
R
TSB
)
Tx
D
A
Tx
C
A
Rx
CA
Rx
DA
PA
0
PA
1
PA
2
V
CC
PA
3
GN
D
PA
4
PA
5
PA
6
PA
7
PC4
(
R
TSA)
PC5
(
D
TRA
)
PC6
(
SYNCA
)
PC7
(
W
T
/RDY
A
)
NC
NC
NC
NC
PC0 (WT/RDYB)
GND
CSTA
DCDA
DCDB
CTSB
TxDB
TxCB
RxCB
RxDB
A0
A1
A2
A3
CS
M1
RD
V
CC
IORQ
RESET
CLK/TRG3
NC
NC
NC
NC
CL
K/T
R
G
2
CL
K/T
R
G
1
CL
K/T
R
G
0
D7
D6
D5
D4
GND
V
CC
D3
D2
D1
D0
V
CC
XT
A
L
1
XT
A
L
0
GND
CL
OCK
CL
KO
UT
OS
C
IN
T
NC
NC
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
6
Port B does not support Mode 2 operation and can only be used in
Mode 3 when Port A is programmed for Mode 2. BRDY is not
associated with Port B when it is operating in Mode 3.
ASTB, BSTB. Port Strobe (inputs, Active Low). These signals indicate that the peripheral
device has performed a transfer. In Mode 0, the signal indicates that the peripheral device
has accepted the data present on the port pins. In Mode 1, the signal causes the data on the
port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output
data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present
on the Port A pins to be latched into the Port A input data latch. The end of the current
transaction is noted by the rising edge of these signals.
Port B does not support Mode 2 operation, and can only be used in
Mode 3 when Port A is programmed for Mode 2. BSTB is not
associated with Port B when it is operating in Mode 3.
CLK/TRG0CLK/TRG3. External Clock/Timer Trigger (inputs, user-selectable Active
High or Low). These four pins correspond to the four counter/timer channels of the KIO.
In Counter mode, each active edge causes the downcounter to decrement. In Timer mode,
an active edge starts the timer.
CLKOUT. Clock Out (output). This output is a divide-by-two of the oscillator (XTAL)
input.
CLOCK. System Clock (input). This clock must be the same as (or a derivative of) the
CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be
connected together.
CS. Chip Select (input, Active Low). Used to activate the internal register decoding mech-
anism and allow the KIO to perform a data transfer to/from the CPU.
CTSA, CTSB. Clear to Send (inputs, Active Low). These signals are modem control sig-
nals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective transmitters. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
D
0
D
7
. Data Bus (bidirectional, Active High, 3-stated). Used for data exchanges between
the CPU and the KIO for programming and data transfer. The KIO also monitors the data
bus for RETI instructions to maintain its Interrupt Under Service (IUS) status.
DCDA, DCDB. Data Carrier Detect (inputs, Active Low). These signals are modem con-
trol signals for the serial channels. When programmed for Auto Enable, a Low on these
pins enables their respective receivers. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
DTRA, DTRB. Data Terminal Ready (outputs, Active Low). These signals are modem
control signals for the serial channels. They follow the state programmed into their respec-
tive serial channels, and are multiplexed with Port C, bits 5 and 2, respectively.
Note:
Note:
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
7
IEI. Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable
Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven
device. A High on this line indicates that no higher-priority device is requesting an inter-
rupt.
IEO. Interrupt Enable Out (output, Active High). This signal is used with Interrupt Enable
In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that this device is requesting an interrupt, and that no higher-
priority device, is not requesting an interrupt. A Low blocks any lower-priority devices
from requesting an interrupt.
IORQ. Input/Output Request (input, Active Low). IORQ is used with RD, A
0
A
3
, and CS
to transfer data between the KIO and the CPU. When IORQ, RD, and CS are Active Low,
the device selected by A
0
A
3
transfers data to the CPU. When IORQ and CS are Active
Low, but RD is Active High, the device selected by A
0
A
3
is written into by the CPU.
When IORQ and M1 are both Active Low, the KIO may respond with an interrupt vector
from its highest-priority interrupting device.
M1. Machine Cycle 1 (input, Active Low). When M1 and RD are Low, the Z80 CPU
fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI
instruction sequence is being executed. When M1 and IORQ are both active, the KIO
decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its
highest-priority interrupting device.
OSC. Oscillator (output). This output is a reference clock for the oscillator.
PA0PA7. Port A Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PA
0
is
the least-significant bit of the bus.
PB0PB7. Port B Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PB
0
is
the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Dar-
lington transistors.
PC0PC7. Port C Bus (bidirectional, tristated). PC
0
is the least-significant bit of the bus.
These pins are multiplexed between the 8-bit PIA and additional modem control signals
for the serial channels.
RD. Read (input, Active Low). When RD is active, a memory or I/O read operation is in
progress. RD is used with A
0
A
3
, CS and IORQ to transfer data between the KIO and
CPU.
RESET. Reset (input, Active Low). A Low on this pin forces the KIO into a Reset condi-
tion. This signal must be active for a minimum of three Clock cycles. The KIO resets so
that the PIO ports operate in Mode 1
With handshakes inactive and interrupts disabled
PIA port in Input mode and active
CTC channel counting terminated and interrupts disabled
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
8
SIO channels disabled
Marking with interrupts disabled.
All control registers must be rewritten after a hardware reset.
RTSA, RTSB. Request to Send (outputs, Active Low). These signals are modem control
signals for their serial channels. They follow the inverse state programmed into their
respective serial channels, and are multiplexed with Port C, bits 4 and 3, respectively.
RxCA, RxCB. Receive Clock (inputs, Active Low). These clocks are used to assemble
the data in the receiver shift register for their serial channels. Data is sampled on the rising
edge of the clock.
RxDA, RxDB. Receive Data (inputs, Active High). These pins are the input data pins to
the receive shift register for their serial channels.
SYNCA, SYNCB. Synchronization (bidirectional, Active Low). In the Asynchronous
mode of operation, these pins act much like the CTS and DCD pins. Transitions affect the
Sync/Hunt status bit for their respective serial channels, but serve no other purpose. These
pins are multiplexed with Port C, bits 6 and 1, respectively.
TxCA, TxCB. Transmit Clock (inputs, Active Low). These clocks are used to transmit
data from the transmit shift register for their serial channels. Data is transmitted on the
falling edge of the clock.
TxDA, TxDB. Transmit Data (outputs, Active High). These pins are the output data pins
from the transmitter for their serial channels.
WT/RDYA, WT/RDYB. Wait/Ready (outputs, open-drain when programmed as Wait;
tristated when programmed as Ready). These pins may be programmed as Ready lines for
a DMA controller or Wait lines for interfacing to a CPU. As a Ready line, these pins indi-
cate (when Active Low) that the transmitter or the receiver requests a transfer between the
serial channel and the DMA. As a Wait line, these pins dictate (when Low) that the CPU
must wait until the transmitter or receiver can complete the requested transaction. These
pins are multiplexed with Port C, bit 7 and 0, respectively.
XTALI. Crystal/Clock Connection. (input).
XTALO. Crystal Connection. (output).
ZC/TO0ZC/TO3. Zero count/Time-out (outputs, Active High). These four pins are out-
puts from the four counter/timer channels of the KIO. Each pin pulses High when its cor-
responding downcounter reaches 0.
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
9
Standard Test Conditions
The DC Characteristics and Capacitance sections below apply to the following standard
test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Posi-
tive current flows into the referenced pin.
Available operating temperature ranges are:
S = 0 C to +70 C
E = 40 C to +100 C
Voltage Supply Range: +5.0V 10%
All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF
increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address
and control lines. AC timing measurements are referenced to 1.5 volts (except for
CLOCK, which is referenced to the 10% and 90% points.
Table 2. KIO Registers
Address
A3
A2
A1
A0
Register 0: PIO Port A Data
0
0
0
0
Register 1: PIO Port A Command
0
0
0
1
Register 2: PIO Port B Data
0
0
1
0
Register 3: PIO Port B Command
0
0
1
1
Register 4: CTC Channel 0
0
1
0
0
Register 5: CTC Channel 1
0
1
0
1
Register 6:
0
1
1
0
Register 7:
0
1
1
1
Register 8: SIO Port A Data
1
0
0
0
Register 9: SIO Port A Command/Status
1
0
0
1
Register 10: SIO Channel B Data
1
0
1
0
Register 11: SIO Channel B Command/Status
1
0
1
1
Register 12: PIA Port C Data
1
1
0
0
Register 13: PIA Port C Command
1
1
0
1
Register 14: KIO Command
1
1
1
0
Register 15: Reserved
1
1
1
1
Note: Additionally, IORQ and CS must be Low. Registers are written to or read from by the CPU,
applying a 1 or a 0 respectively on the RD pin.
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
10
The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section. Refer to the Literature List for additional
documentation.
Figure 4. Test Load Diagram
Figure 5. PIO Block Diagram
250
From Output
Under Test
A
100 pF
+5V
2.1K
Data
Control
Data or
Control
Handshake
Interrupt Control Lines
Peripheral
Interface
Internal
Control
Logic
CPU
Bus I/O
Data or
Control
Handshake
Interrupt
Control
Port A
I/O
Port B
I/O
Internal Bus
8
3
8
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
11
Figure 6. PIA Block Diagram
Figure 7. CTC Block Diagram
Port C
Dir.
Ctrl.
Data Bus
PC0`PC7
Data
Control
INT
IE1
IE0
ZC/TO
CLK/TRG
Reset
Internal Bus
Internal
Control
Logic
Interrupt
Logic
Counter/
Timer
Logic
4
4
CPU
Bus
I/O
8
6
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
12
Figure 8. Crystal Connection
C1
C2
ZTALI
Crystal
Inputs
XTALO
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
13
Figure 9. SIO Block Diagram
Data
Control
Serial
Channel
Interrupt
Control
Lines
I
n
t
e
r
n
a
l
B
u
s
Data
Clocks
Sync
Wait/Ready
Modem or
Other
Control
Modem or
Other
Control
Serial
Channel
Data
Clocks
Sync
Wait/Ready
Channel A
Control
and
Status
Registers
Internal
Control
Logic
CPU
Bus
I/O
Interrupt
Control
Logic
Channel B
Control
and
Status
Registers
Channel A
Channel B
Channel A
Control
and
Status
Channel B
Control
and
Status
8
7
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
14
DC Characteristics
V
cc
= 5.0V +/ 10% unless otherwise specified.
Table 3. DC Characteristics of the Z84C90
Symbol
Item
Min
Max
Unit
Condition
V
ILC
Clock Input Low Voltage
0.3
+0.45
V
V
IHC
Clock Input High Voltage
V
CC
0.6 V
cc
+0.3
V
IL
Input Low Voltage
0.3
+0.8
V
V
IH
Input High Voltage
2.2
V
cc
V
V
OL
Output Low Voltage
+0.4
V
I
OL
= 2.0mA
V
OH1
Output High Voltage 1
2.4
V
I
OH
= 1.6mA
V
OH2
Output High Voltage 2
V
CC
0.8
V
I
OH
= 250mA
I
LI
Input Leakage Current
10.0
mA
V
in
= 0.4~V
cc
I
OL
3-State Leakage Current
10.0
mA
V
in
= 0.4~V
cc
I
L(SY)
SYNC
Pin Leakage
Current
+10
40
mA
V
in
= 0.4~V
cc
I
OHD
Darlington Drive Current
(Port B and ZC/T00~3)
1.5
mA
V
OH
= 1.5V
R
EXT
= 390 Ohms
I
CC
Power Supply Current*
8 MHz
10MHz
12.5MHz
15
15
15
mA
mA
V
CC
= 5 V
V
IH
= V
cc
.2V
V
IL
= .2V
*Measurement made with output floating over specified temperature and voltage ranges.
Table 4. Capacitance
Symbol
Parameter
Minimum Maximum Unit
C
CLOCK
CI
N
C
OUT
Clock Capacitance
Input Capacitance
Output Capacitance
10
10
15
cF
cF
cF
T
A
= 25C, f = 1MHz
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
15
AC Characteristics
Table 5. AC Characteristics of the Z84C90
8MHz
10MHz
1
12MHz
No. Symbol
Parameter
Min
Max
Min
Max
Min Max U/M
Bus Interface Timing
1
TcC
Clock Cycle Time
125
DC
100
DC
80
DC ns
2
TwCh
Clock Pulse Width (High)
55
DC
42
DC
32
DC ns
3
TwCl
Clock Pulse Width (Low)
55
DC
42
DC
32
DC ns
4
TfC
Clock Fall Time
10
10
10 ns
5
TrC
Clock Rise Time
10
10
10 ns
6
TsA(Rlf)
Address, CS Setup to RD, IORQ
Fall
50
40
30
ns
7
TsRl(Cr)
RD, IORQ to Clock
Rise Setup
50
50
40
ns
8
Th
Hold Time for Specified Setup
15
15
15
ns
9
TdCr(DO)
CLOCK Rise to Data Out Delay
100
80
65 ns
10 TdRlr(DOz)
RD, IORQ Rise to Data Out Float
Delay
75
60
55 ns
11 ThRDr(D)
M1,RD,IORQ Rise to Data Float
15
15
15
ns
12 TsD(Cr)
Data in to Clock Rise Setup
30
25
22
ns
13 TdIOI(DO)
IORQ Fall to Data Out Delay
(INTACK Cycle)
2
95
95
95 ns
14 ThIOr(D)
IORQ Rise to Data Float (INTACK)
15
15
15
ns
15 THIOr(A)
IORQ Rise to Address Hold
15
15
15
ns
16 TsM1f(Cr)
M1 Fall to Clock Rise Setup
40
40
40
ns
17 TsM1r(Cf)
M1 Rise to Clock Fall Setup
(M1 Cycle)
-15
-15
15
ns
18 TdM1f(IEOf)
M1 Fall to IEO Fall Delay (Interrupt
Immediately preceding M1 Fall)
3
ns
19 TsIEI(IOf)
IEI to IORQ Fall Setup
3
ns
20 TdIEIf(IEOf)
IEI Fall to IEO Fall Delay
3
160
150
125 ns
21 TdIEIf(IEOr)
IEI Rise to IEO Rise Delay
(after ED Decode)
3
160
150
125 ns
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
16
22 TsIEI(Cf)
IEI to Clock Fall Setup (for 4D
Decode)
50
40
30
ns
23 TsIOr(Cf)
IORQ Rise to Clock Fall Setup
(to activate RDY on next clock)
100
100
ns
PIO Timing
24 TdCf(RDYr)
Clock Fall to RDY Rise Delay
100
100
ns
25 TdCf(RDYf)
Clock
Fall to RDY
Fall Delay
100
100
ns
26 TwSTB
STB Pulse Width
100
80
ns
27 TsSTBr(Cf)
STB
Rise to Clock
Fall Setup
(to activate RDY on next clock
cycle)
100
100
ns
28 TdIOf(PD)
IORQ
Fall to Port Data Valid
(Mode 0)
140
120
ns
29 TsPD(STBr)
Port A,B Data to STB Rise Setup
Time (Mode 1)
140
75
ns
30 TdSTBI(PD)
STB Fall to Port A,B Data Valid
Delay (Mode 2)
150
120
ns
31 TdSTBr(PDz)
STB Rise to Port Data Float Delay
(Mode 2)
140
120
ns
32 TdPD(INTf)
Port Data Match to INT Fall Delay
(Mode 3)
250
200
ns
33 TdSTBr(INTf)
STB Rise to INT Fall Delay
290
220
ns
34 TsPD(RIf)
PIA Port Data to RD, IORQ Fall
Setup
TBD
TBD
35 TdCr(PD)
Clock Rise to Port Data Valid Delay
80
80
ns
CTC Timing
36 TdCr(INTf)
Clock Rise to INT Rise Delay
TcC+100
TcC+80
ns
37 TsCTRr(Cr)c
CLK/TRG Rise to Clock Rise Setup
(for immediate count, Counter
mode)
90
90
ns
38 TsCTRr(Cr)t
CLK/TRG Rise to Clock Rise Setup
(for enabling prescaler on following
Clock
Rise, Timer mode)
90
90
ns
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
10MHz
1
12MHz
No. Symbol
Parameter
Min
Max
Min
Max
Min Max U/M
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
17
39 TdCTRr(INTf) CLK/TRG Rise to INT Fall Delay
TsCTRr(Cr) satisfied
TsCTRr(Cr) not satisfied
(36)+(38)
(1)+(36)+(38)
(36)+(38)
(1)+(36)+(38)
40 TcCTR
CLK/TRG Cycle Time
4
(2TcC)
DC
(2TcC)
DC
ns
41 TwCTRh
CLK/TRG Width High
90
DC
90
DC
ns
42 TwCTRI
CLK/TRG Width Low
90
DC
90
DC
ns
43 TrCTR
CLK/TRG Rise Time
30
30
ns
44 TfCTR
CLK/TRG Fall Time
30
30
ns
45 TdCr(ZCr)
Clock Rise to ZC/TO Rise Delay
80
80
ns
46 TdCf(ZCf)
Clock Fall to ZC/TO Fall Delay
80
80
ns
SIO Timing
47 TdIOf(W/Rf)
IORQ Fall to WT/RDY Fall Delay
(Wait Mode)
130
110
ns
48 TdCr(W/Rf)
Clock Rise to WT/RDY Delay
(Ready Mode)
85
85
ns
49 TdCf(W/Rz)
Clock Fall to WT/RDY Float Delay
(Wait Mode)
90
80
ns
50 TwPh
Pulse Width High
150
120
ns
51 TwPI
Pulse Width Low
150
120
ns
52 TcTxC
TxC Cycle Time
250
DC
200
DC
ns
53 TwTxCh
TxC Width High
85
DC
80
DC
ns
54 TwTxCl
TxC Width Low
85
DC
80
DC
ns
55 TrTxC
TxC Rise Time
60
60
ns
56 TfTxC
TxC Fall Time
60
60
ns
57 TdTxCf(TxD)
TxC Fall to TxD Delay (x1 mode)
160
120
ns
58 TdTxCf(W/Rf) TxC Fall to WT/RDY Fall Delay
(Ready Mode)
5
5
9
5
9
ns
59 TdTxCf(INTf)
TxC Fall to INT Fall Delay
5
5
9
5
9
ns
60 TcRxC
RxC Cycle Time
250
DC
200
DC
ns
61 TwRxCh
RxC Width High
85
DC
80
DC
ns
62 TwRxCl
RxC Width Low
85
DC
80
DC
ns
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
10MHz
1
12MHz
No. Symbol
Parameter
Min
Max
Min
Max
Min Max U/M
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
18
63 TrRxC
RxC Rise Time
60
60
ns
64 TfRxC
RxC Fall Time
60
60
ns
65 TsRxD(RxCr)
RxD to RxC Rise Setup
0
0
ns
66
ThRxCr(RxD)
RxC
Rise
to RxD Hold Time
80
60
ns
67
TdRxCr(W/Rf) RxC Rise to W/RDY Fall Delay
(Ready Mode)
5
10
13
10
13
ns
68
TdRxCf(INTf)
RxC to INT Fall Delay
5
10
13
10
13
ns
69
TdRxCr
(SYNCf)
RxC Rise to SYNC Fall Delay
(Output Mode)
4
7
4
7
ns
70
TsSYNCf
(RxCr)
SYNC Fall to RxC Rise Setup
(External Sync Mode)
-100
-100
ns
71
TdCf(IEOr)
Clock Fall to IEO Rise Delay
90
75
ns
72
TdCf(IEOf)
Clock Fall to IEO Fall Delay
110
90
ns
73
ThDI(M1r,Rdr) Data Hold Time to M1 Rise or RD
Rise
0
0
ns
74
TsM1/RD(C)
Setup time for M1 and RD to clock
Rising (with Data Valid)
20
20
Notes:
1. Maximum SIO data rate is f(CLOCK) divided by 5.
2. For a Z80 CPU above 8 MHz, one Wait state is required to meet this parameter.
3. These daisy chain parameters include contributions from the PIO, SIO, and CTC cells, and vary slightly
depending on how these are ordered by the KIO command register. See Table 5.
4. Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
5. units are TcC.
Table 6.Daisy Chain Parameters
8 MHz
10 MHz
12 MHz
No. Symbol
Parameter
Min
Max
Min
Max
Min
Max U/M
18
1
TdM1(IEO)
(PIO at #1)
160
150
125 ns
(CTC at #1)
180
150
125 ns
(SIO at #1)
230
200
200 ns
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
10MHz
1
12MHz
No. Symbol
Parameter
Min
Max
Min
Max
Min Max U/M
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
19
19
2
TsIEI (IO)
(PIO at #3)
170
140
115
ns
(CTC at #3)
170
160
130
ns
(SIO at #3)
180
160
130
ns
20
3
TdIEI(IEOf)
160
150
125 ns
21
4
TdIEI(IEOr)
160
150
125 ns
Notes: to calculate Z80 KIO daisy-chain timing, use the Z80 PIO, CTC, and SIO with I/O buffers on the chain. The
following are calculation formulas:
1. Parameter 18: M1 falling to IEO delay TdM1(IEO) = TdM1(IO)#1 + TdIEI(IEO)#2 + TdIEI(IEO)#3 + Output Buffer
Delay).
2. Parameter 19: IEI to IORQ falling setup time TsIEI(IO) = TdIEI(IEO)#1 + TdIEI(IEO)#2 + TdIEI(IEO)#3 + Input
Buffer Delay).
3. Parameter 20: IEI falling delay = TdIEI(IEOf) - TdIEI(IEOf)PIO + TdIEI(IEOf)CTC + TdIEI(IEOf)SIO + (Input buffer
Delay) + (Output Buffer Delay).
4. Parameter 21: IEI rising to IEO rising delay (after ED decode) - TdIEI(IEOr) = TdIEI(IEOr)PIO + TdIEI(IEOr)CTC
+ TdIEI(IEOr)SIO + ((Input buffer Delay) + (Output Buffer Delay).
Table 6.Daisy Chain Parameters (Continued)
8 MHz
10 MHz
12 MHz
No. Symbol
Parameter
Min
Max
Min
Max
Min
Max U/M
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
20
Figure 10. I/O Read/Write Timing (M1 = 1)
1
2
3
4
5
6
7
8
9
10
11
15
10
8
12
7
6
47
48
48
49
Clock
A0A3
CS
IORQ
RD
D0D7
RD
WT/RDY
Wait Mode
WT/RDY
Ready Mode
Read Cycle
Write Cycle
D0D7
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
21
Figure 11. Serial I/O Timing
CTS DCD
SYNC
TxC
TxD
WT/RDY
RxC
RxD
SYNC
WT/RDY
INT
INT
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
22
Figure 12. Counter/Timer Timing
37
38
39
40
41
42
43
44
45
46
36
Clock
CLK/TRG
Counter
CLK/TRG
Timer
ZC/TO
INT
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
23
Figure 13. Port I/O Read/Write Timing
Clock
IORQ
RD
Port C
Input
Port C
Output
RDY
STB
Mode 0
Mode 1
Mode 2
Mode 3
INT
34
35
23
24
25
29
26
28
30
27
8
32
31
33
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
24
Figure 14. Interrupt Acknowledge Cycle
Figure 15. Op Code Fetch Cycle
36
18
14
16
19
11
7
13
17
Clock
INT
M1
IORQ
D
0
D
7
IE1
IE0
T2
Two
Two
T3
T4
T1
Clock
M1
RD
D
0
D
7
IE1
IE0
72
71
17
16
12
21
20
73
73
22
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
25
Precautions & Limitations
The following describe the limitations of Revision A of the Z84C90 KIO.
Problem:
Daisy-chain. If the KIO has an Interrupt Pending during and Interrupt Acknowledge
cycle, KIO misses the status of the IE1 pin. This produces vector contention if there is a
higher interrupting device. It works fine if only one device is in the system.
Work Around:
There is no problem if the application has only one peripheral in the daisy chain. For two
or more peripherals in the system, a "hardware workaround circuit" is needed. Please con-
tact your local Zilog representatives to get more detailed information.
Problem:
Reset. KIO requires the M1 signal to exit from Reset state. If the M1 signal is not
received, the KIO can not be programmed. This is not a problem for users of the Z80
CPU.
Workaround:
If the CPU is other than a Z80, an M1 signal is needed to exit RESET status. Otherwise,
the KIO can not be programmed.
Problem:
Port C. When Port C is used as Parallel I/O (not as SIO's modem signals) and there is a
status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes.
Work Around:
Before using Port C as a parallel port, set the SIO modem signal mode back to Port C. This
procedure avoids the problem.
Problem:
Interrupt Acknowledge cycle. The KIO modifies the contents of the KIO control register
(specifically, the KIO modifies the daisy-chain configuration) if the CE pin is active dur-
ing the Interrupt Acknowledge cycle (with other conditions satisfied).
Z84C90
KIO Serial/Parallel Counter Timer
PS011802-0902
26
Work Around:
This problem could happen under the following narrowly defined conditions:
CE signal is active throughout the Interrupt Acknowledge cycle.
The address on the bus, A3A0, is "110b".
During this time, bit D3 is 1.
At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ
signal.
At the time period of CE active, IORQ active, and M1 returns to the inactive state; all
during the rising edge of the clock.
This problem is not the case with the Z80 CPU. However, other CPUs could be affected.
One of the possible workarounds is to add the condition M1 not active to generate a CE
signal.