1
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
GENERAL DESCRIPTION
Z86127
L
OW
-C
OST
D
IGITAL
T
ELEVISION
C
ONTROLLER
(LDTC)
The Z86127 Low-Cost Digital Television Controller (LDTC)
introduces a new level of sophistication to single-chip
architecture. The Z86127 is a member of the Z8
single-
chip microcontroller family with 8 Kbytes of ROM and 236
bytes of RAM. The device is housed in a 64-pin DIP
package, in which only 52 are active, and are CMOS
compatible. The LDTC offers mask programmed ROM
which enables the Z8 microcontroller to be used in a high
volume production application device embedded with a
custom program (customer supplied program).
Zilog's LDTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation
capabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The
device provides an ideal performance and reliability solution
for consumer and industrial television applications.
The Z86127 architecture is characterized by utilizing Zilog's
advanced SuperintegrationTM design methodology. The
device has an 8-bit internal data path controlled by a Z8
microcontroller and On Screen Display (OSD) logic circuits/
Pulse Width Modulators (PWM). On-chip peripherals
include two register mapped I/O ports (Ports 2 and Port 3),
interrupt control logic (one software, two external and three
internal interrupts) and a standby mode recovery input
port (Port 3, pin P30).
The OSD control circuits support 8 rows by 20 columns of
characters. The character color is specified by row. One of
the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying either low resolution (5x7 dot pattern)
or high resolution (11x15 dot pattern) characters. The
Z86C97 currently supports high resolution characters only.
DC-4063-00
(10-16-91)
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Five 8-bit
PWM ports are used to vary picture levels.
The LDTC applications demand powerful I/O capabilities.
The Z86127 fulfills this with 27 I/O pins dedicated to input
and output. These lines are grouped into four ports, and
are configurable under software control to provide timing,
status signals, parallel I/O and an address/data bus for
interfacing to external memory.
There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general purpose registers, two I/O Port
registers, 15 control and status registers and three reserved
registers.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the LDTC offers two on-chip counter/timers with a large
number of user selectable modes (Functional Block
Diagram).
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
4
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Symbol
Parameters
Min
Max
Units
Notes
V
CC
Power Supply Voltage*
-0.3
+7
V
V
I
Input Voltage
-0.3
V
CC
+0.3
V
V
I
Input Voltage
-0.3
V
CC
+0.3
V
[1]
V
O
Output Voltage
-0.3
V
CC
+8.0
V
[2]
I
OH
Output Current High
-10
mA
1 pin
I
OH
Output Current High
-100
mA
All total
I
OL
Output Current Low
20
mA
1 pin
I
OL
Output Current Low
40
mA
[3] (1 pin)
I
OL
Output Current Low
200
mA
All total
T
A
Operating Temperature
T
STG
Storage Temperature
-65
+150
C
Notes:
[1] Port 2 open drain
[2] PWM open-drain outputs
[3] Port 5
* Voltage on all pins with respect to GND.
See Ordering Information
Parameter
Max
Units
Input capacitance
10
pF
Output capacitance
20
pF
I/O capacitance
25
pF
AFC
IN
input capacitance
10
pF
From Output
Under Test
RLL
VDD
RLH
150 pF
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load
Diagram).
Test Load Diagram
CAPACITANCE
T
A
=25
C; V
CC
=GND=0V; Freq=1.0 MHz; unmeasured pins to GND.
5
DC CHARACTERISTICS
T
A
=0
C to +70
C; V
CC
=+4.5V to +5.5V; F
OSC
=4 MHz
Sym
Parameter
T
A
=0
C to +70
C
Typical Units
Conditions
Min
Max
@ 25
C
V
IL
Input Voltage Low
0
0.2 V
CC
1.48
V
V
ILC
Input XTAL/Osc In Low
0.07 V
CC
0.98
V
External Clock Generator Driven
V
IH
Input Voltage XTAL/Osc In High
0.7 V
CC
V
CC
3.2
V
External Clock Generator Driven
V
IHC
Input XTAL/Osc in High
0.8 V
CC
V
CC
3.0
V
External Clock Generator Driven
V
HY
Schmitt Hysteresis
0.1 V
CC
0.8
V
V
PU
Maximum Pull-up Voltage
12
V
[2]
V
OL
Output Voltage Low
0.4
0.16
V
I
OL
=1.00mA
0.4
0.19
V
I
OL
=3.2mA, [1]
0.4
0.19
V
I
OL
=0.75mA [2]
1.5
1.00
V
I
OL
=10mA [1]
V
00-01
AFC Level 01 In
0.45 V
CC
1.9
V
V
01-11
AFC Level 11 In
0.5 V
CC
0.75 V
CC
3.12
V
V
OH
Output Voltage High
V
CC
-0.4
4.75
V
I
OH
=-0.75mA
I
IR
Reset Input Current
-80
-46
A
V
RL
=0V
I
IL
Input Leakage
-3.0
3.0
0.01
A
0V,V
CC
I
OL
Tri-State Leakage
-3.0
3.0
0.02
A
0V,V
CC
I
CC
Supply Current
20
13.2
mA
All inputs at rail
I
CC1
6
3.2
mA
All inputs at rail
I
CC2
10
0
A
All inputs at rail
Notes:
[1] Port 5
[2] PWM open drain
8
AC CHARACTERISTICS
T
A
=0
C to +70
C; V
CC
=+4.5V to +5.5V; F
OSC
=4 MHz,
No
Symbol
Parameter
Min
Max
Unit
1
TpC
Input Clock Period
250
1000
ns
2
TrC,TfC
Clock Input Rise and Fall
15
ns
3
TwC
Input Clock Width
70
ns
4
TwTinL
Timer Input Low Width
70
ns
5
TwTinH
Timer Input High Width
3TpC
6
TpTin
Timer Input Period
8TpC
7
TrTin,TfTin
Timer Input Rise and Fall
100
ns
8a
TwIL
Int Req Input Low
70
ns
8b
TwIL
3TpC
9
TwIH
Int Request Input High
3TpC
10
TdPOR
Power On Reset Delay
25
100
ms
11
TdLVIRES
Low Voltage Detect to
200
ns
Internal RESET Condition
12
TwRES
Reset Minimum Width
5TpC
13
TdHsOI
H
sync
Start to V
osc
Stop
2TpV
3TpV
14
TdHsOh
H
sync
End to V
osc
Start
1TpV
15
TdWDT
WDT Refresh Time
12
ms
Note:
Refer to DC Characteristics for details on switching levels.
1991 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 171-980 A/B ZILOG CPTO
FAX 408 370-8056/8027
PDF 
ZIP
