1
Z86247
CPS DC-9027-00
GENERAL DESCRIPTION
Z86247
40-P
IN
L
OW
-C
OST
D
IGITAL
T
ELEVISION
C
ONTROLLER
(4LDTC)
The Z86247 40-pin Low-Cost Digital Television Controller
(4LDTC) introduces a new level of sophistication to single-
chip architecture. The Z86247 is a member of the Z8
single-chip microcontroller family with 8 Kbytes of ROM
and 236 bytes of RAM. The device is offered in a 40-pin
package and is CMOS compatible. The 4LDTC offers
mask programmed ROM which enables the Z8
microcontroller to be used in a high volume production
application device embedded with a custom program
(customer supplied program) and combines together with
the Z86C27 (DTC) and Z86127 (LDTC) to provide support
for high end, mid range and low end TV applications.
Zilog's 4LDTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation
capabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The
device provides an ideal performance and reliability solution
for consumer and industrial television applications.
The Z86247 architecture is characterized by utilizing Zilog's
advanced SuperintegrationTM design methodology. The
device has an 8-bit internal data path controlled by a Z8
microcontroller and On Screen Display (OSD) logic circuits
and Pulse Width Modulators (PWM). On-chip peripherals
include two register mapped I/O ports (Ports 2 and Port 3),
interrupt control logic (one software, two external and three
internal interrupts) and a standby mode recovery input
port (Port 3, pin P30).
The OSD control circuits support 8 rows by 20 columns of
characters. The character color is specified by row. One of
the eight rows is assigned to show two kinds of colors for
bar type displays such as volume control. The OSD is
capable of displaying high resolution (11x15 dot pattern)
characters.
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Three
8-bit PWM ports used to vary picture levels.
The 4LDTC applications demand powerful I/O capabilities.
The Z86247 fulfills this with 24 pins dedicated to input or
output. These lines are grouped into three ports, and are
configurable under software control to provide timing,
status signals, parallel I/O and an address/data bus for
interfacing to external memory.
There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general purpose registers, two I/O Port
registers, 15 control and status registers and three reserved
registers.
To unburden the program from coping with the real-time
problems such as counting/timing and data communication,
the 4LDTC offers two on-chip counter/timers with a large
number of user selectable modes (Figure 1).
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
DC 9027-00
(7-27-94)
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
2
Z86247
CPS DC-9027-00
GENERAL DESCRIPTION
(Continued)
Counter
Timer
Counter
Timer
8 KByte
Program ROM
RESET
Oscillator
WDT
Port 3/
Interrupt
Port 6
(Control)
Z8 CPU
Core
Port 2
256 Byte
Register File
Port 1
A8-15
AD0-7
PWM 1
14 -bit
PWM 6
to
PWM 8
6-bit
On Screen
Display
Port 0
128 Byte
Character RAM
4 KByte
Character ROM
P27
P26
P25
P24
P23
P22
P21
P20
PWM 6
PWM 7
PWM 8
OSCIN
OSCOUT
HSYNC
VSYNC
VRED
VGREEN
VBLUE
VBLANK
XTAL1
XTAL2
/RESET
P30
P31
P34
P35
P36
P60
P61
P62
P63
P64
P65
AFCIN
PWM 1
PWM 9
to
PWM11
PWM 9
PWM 10
PWM 11
Functional Block Diagram
3
Z86247
CPS DC-9027-00
PIN CONFIGURATION
40-Pin Mask-ROM Plastic DIP
/RESET
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P27
P26
P25
P24
P23
P22
P20
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC
P21
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
Z86247
(LDTC)
1
2
9
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
PWM1
P35
P36
P34
P31
P30
XTAL1
XTAL2
P60
GND
P61
P62
VCC
P63
P64
P65
AFCIN
OSCIN
OSCOUT
4
Z86247
CPS DC-9027-00
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Symbol
Parameters
Min
Max
Units
Notes
V
CC
Power Supply Voltage*
0.3
+ 7
V
V
I
Input Voltage
0.3
V
CC
+0.3
V
V
I
Input Voltage
0.3
V
CC
+0.3
V
[1]
V
O
Output Voltage
0.3
V
CC
+8.0
V
[2,3]
I
OH
Output Current High
10
mA
1 pin
I
OH
Output Current High
100
mA
All total
I
OL
Output Current Low
2 0
mA
1 pin
I
OL
Output Current Low
200
mA
All total
T
A
Operating Temperature
T
STG
Storage Temperature
65
+150
C
Notes:
[1] Port 2 open-drain
[2] PWM open-drain outputs
[3] PWM breakdown is 13.2V (normal operation). Will withstand
16V max. (non-momentary operating).
* Voltage on all pins with respect to GND.
See Ordering Information
From Output
Under Test
RLL
VDD
RLH
150 pF
Test Load Diagram
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load
Diagram).
5
Z86247
CPS DC-9027-00
DC CHARACTERISTICS
T
A
=0
C to +70
C; V
CC
=+4.5V to +5.5V; F
OSC
=4 MHz
T
A
=0
C to +70
C
Typical
Sym
Parameter
Min
Max
@ 25
C Units
Conditions
V
IL
Input Voltage Low
0
0.2 V
CC
1.48
V
V
ILC
Input XTAL/Osc In Low
0.07 V
CC
0.98
V
External Clock Generator Driven
V
IH
Input Voltage XTAL/Osc In High
0.7 V
CC
V
CC
3.2
V
External Clock Generator Driven
V
IHC
Input XTAL/Osc In High
0.8 V
CC
V
CC
3.0
V
External Clock Generator Driven
V
HY
Schmitt Hysteresis
0.1 V
CC
0.8
V
V
PU
Maximum Pull-Up Voltage
1 2
V
[1]
V
OL
Output Voltage Low
0.4
0.16
V
I
OL
=1.00 mA
0.4
0.19
V
I
OL
=0.75 mA [1]
V
00-01
AFC Level 01 In
0.45 V
CC
1.9
V
V
01-11
AFC Level 11 In
0.5 V
CC
0.75 V
CC
3.12
V
V
OH
Output Voltage High
V
CC
0.4
4.75
V
I
OH
=0.75 mA
I
IR
Reset Input Current
80
46
A
V
RL
=0V
I
IL
Input Leakage
3.0
3.0
0.01
A
0V,V
CC
I
OL
Tri-State Leakage
3.0
3.0
0.02
A
0V,V
CC
I
CC
Supply Current
2 0
13.2
mA
All inputs at rail
I
CC1
6
3.2
mA
All inputs at rail
I
CC2
1 0
2.0
A
All inputs at rail
Note:
[1] PWM open-drain
CAPACITANCE
T
A
=25
C; V
CC
=GND=0V; Freq=1.0 MHz; unmeasured pins to GND.
Parameter
Max
Units
Input capacitance
1 0
p F
Output capacitance
2 0
p F
I/O capacitance
2 5
p F
AFC
IN
input capacitance
1 0
p F
6
Z86247
CPS DC-9027-00
AC CHARACTERISTICS
Timing Diagrams
XTAL1
1
2
2
3
3
External Clock
Counter Timer
IRQn
8
9
Interrupt Request
Tin
7
5
4
6
7
Z86247
CPS DC-9027-00
AC CHARACTERISTICS
Timing Diagrams (Continued)
External /RESET
10
11
12
Internal /RESET
Vcc
Power-On Reset
HSYNC
14
13
OSC2
On-Screen Display
8
Z86247
CPS DC-9027-00
AC CHARACTERISTICS
T
A
=0
C to +70
C; V
CC
=+4.5V to +5.5V; F
OSC
=4 MHz
No
Symbol
Parameter
Min
Max
Unit
1
TpC
Input Clock Period
250
1000
n s
2
TrC,TfC
Clock Input Rise and Fall
1 5
n s
3
TwC
Input Clock Width
7 0
n s
4
TwTinL
Timer Input Low Width
7 0
n s
5
TwTinH
Timer Input High Width
3TpC
6
TpTin
Timer Input Period
8TpC
7
TrTin,TfTin
Timer Input Rise and Fall
100
n s
8 a
TwIL
Int Req Input Low
7 0
n s
8 b
TwIL
3TpC
9
TwIH
Int Request Input High
3TpC
1 0
TdPOR
Power On Reset Delay
2 5
100
m s
1 1
TdLVIRES
Low Voltage Detect to
200
n s
Internal RESET Condition
1 2
TwRES
Reset Minimum Width
5TpC
1 3
TdHsOI
H
sync
Start to V
osc
Stop
2TpV
3TpV
1 4
TdHsOh
H
sync
End to V
osc
Start
1TpV
1 5
TdWDT
WDT Refresh Time
1 2
m s
Note:
Refer to DC Characteristics for details on switching levels.
1994 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-con-
formance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
Low Margin:
Customer is advised that this product does not meet
Zilog's internal guardbanded test policies for the specifi-
cation requested and is supplied on an exception basis.
Customer is cautioned that delivery may be uncertain and
that, in addition to all other limitations on Zilog liability
stated on the front and back of the acknowledgement,
Zilog makes no claim as to quality and reliability under the
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