DS97KEY1605

P R E L I M I N A R Y

RELIMINARY

RODUCT

PECIFICATION

Z86319

PS/2 M

OUSE

ONTROLLER

FEATURES

C to + 40

C Operating Temperature Range

Low-Power Consumption: 25 mW (Typical)

P24-P27 Can Be Configured with a Voltage Divider
During Input Mode

On-Chip Oscillator (Tolerance =

10%)

Fast Instruction Pointer: 1.5

s @ 4 MHz

ESD Protection Circuitry

Hardwired Watch-Dog Timer (WDT)

Excellent System Level EMI/EFT/ESD

GENERAL DESCRIPTION

The Z86319 is a member of the Z8 family of CMOS micro-
controllers architecture to be used in mouse applications.
These devices offer on-board pull-up and pull-down resis-
tors, a trip-point buffer to accommodate opto-transistor
outputs, and high drive ports capable of up to 10 mA cur-
rent sinking per pin (3 pins maximum).

A permanently enabled Watch-Dog Timer ensures opera-
tional reliability across a broad range of mouse application
environments. The precision RC oscillator filters out high-
frequency noise from the oscillator input pin. When config-
ured as inputs, P24-P27 have built in voltage dividers (25K
pull-up /7.5K pull-down). The input levels are designed for
connection to the emitters of the opto-transistors and

switch at a voltage level of 0.4 V

For applications requiring powerful I/O capabilities, the
Z86319 provides dedicated input and output lines that are
grouped into three ports. There are two basic address
spaces available to support this configuration: Program
Memory, and 125 bytes of general-purpose registers.

The Z86319 device provides two on-chip 8-bit programma-
ble counter/timers with a large number of user-selectable
modes. Each counter/timer is driven by its own 6-bit pro-
grammable prescaler. The Z86319 counter/timers off-load
system real-time tasks such as counting/timing and in-
put/output data communications for increased system effi-
ciency.

Device

ROM

(KB)

RAM*

(Bytes)

I/O

Lines

Voltage

Range

Z86319

125

4.5V to 5.5V

Note:

*General-Purpose (144K Total RAM)

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P R E L I M I N A R Y

PIN DESCRIPTIONS

Figure 2. 18-Pin DIP/SOIC Pin Configuration

Table 1. 18-Pin DIP/SOIC Pin Identification

Pin #

Symbol

Function

Direction

1-4

P24-P27

Port 2, Pins 4,5,6,7

In/Output

Power Supply

Power

RCIN

RC Oscillator

Input

AGND

Analog Ground

Ground

P31

Port 3, Pin 1

Input

GND

Ground

Input

P33

Port 3, Pin 3,

Input

11-13

P00-P02

Port 0, Pins 0,1,2

In/Output

GND

Ground

15-18

P20-P23

Port 2, Pins 0,1,2,3

In/Output

P24
P25
P26
P27

VDD

RCIN

AGND

P31

GND

P23
P22
P21
P20
GND
P02
P01
P00
P33

18 - Pin

DIP/SOIC

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PIN FUNCTIONS

RCIN.

A precision 1% resistor is connected to RCIN,

generating oscillation with an internal capacitor.

Resistor values and corresponding typical frequencies are
shown in Table 2 and graph chart (Figure 3).

Table 2. Resistor Values and Corresponding

Typical Frequencies

External Resistor

Average Frequency

14.0K

5.01 MHz

15.0K

4.70 MHz

16.0K

4.43 MHz

17.0K

4.19 MHz

18.0K

3.97 MHz

19.0K

3.78 MHz

20.0K

3.60 MHz

21.0K

3.44 MHz

22.0K

3.30 MHz

23.0K

3.16 MHz

Figure 3. Z86319 RC Frequency in Function of the External Resistance

(typical numbers)

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

RESISTOR VALUE (K OHMS)

FREQUENCY (MHz)

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STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 4).

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the device.
This rating is a stress rating only; operation of the device
at any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

CAPACITANCE

= GND = 0V, f = 1.0 MHz, unmeasured pins returned to Ground.

SPECIFICATION

= 4.5V to 5.5V

Using the precision RC oscillator feature, f = 4.0 MHz

10% under the following conditions:

= 5.0V

10%

Temp 0 to 40

Application board capacitance:

2.0 pF max.

0.5 pF min.

Figure 4. Test Load Diagram

From Output

Under Test

150 pF

Sym

Parameter

Min

Max

Units

Supply Voltage*

0.3

STG

Storage Temp

+150

Oper Ambient
Temp

Notes:

*Voltages on all pins with respect to Ground.

Parameter

Min

Max

Input Capacitance

10 pF

Output Capacitance

20 pF

I/O Capacitance

25 pF

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DC ELECTRICAL CHARACTERISTICS

4.5V

5.5V

= 0

C to +40

Sym

Parameter

Min

Max

Units

Conditions

Rising Input
Schmitt-Triggered

2.3

3.2

Note 1

Falling Input
Schmitt-Triggered

1.3

2.2

Note 1

Input Low Voltage CMOS Input

Output High Voltage

0.4

= 2.0 mA;

=4.5V

OL1

Output Low Voltage

0.4

= +4.0 mA;

=5.5V

OL2

Output Low Voltage

0.8

= 10.0 mA,

3 Pin Max; V

=5.5V

Low Voltage Protection

2.25

2.95

@ 4 MHz Max, Note 2

Trip Point Voltage
(P24-P27)

1.9

2.5

P24-P27; V

=5.5V

1.5

2.1

=4.5V

Input Leakage

1.0

= 0V, or V

Note 4

Output Leakage

1.0

= 0V, or V

Note 4

Supply Current

4.5

@ 4 MHz, Note 3;
V

=5.5V

DD1

Standby Current

2.2

@ 4 MHz, Note 3;
V

=5.5V

Pull-Up Current (100K)

@ 1V

P00-02, P31, P33

@ 1V

Pull-Down Current (100K)

+20

@ 3V

P00-02, P31, P33

+85

@ 4V

Pull-Up Current (10K)

370

= 0V

P20, P22

670

= 0V

Notes:

1. The min. and max. values of the Schmitt-Trigger input voltages track each other over temperature, V

, and

process variations.

2. The device is functional from V

down to V

voltage. The minimum operational V

is determined by the value of the V

voltage at ambient temperature. The V

voltage increases as the temperature decreases.

3. All input pins are tied to GND and all output pins are floating.

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AC ELECTRICAL CHARACTERISTICS
Timing Diagrams

Figure 5. Electrical Timing Diagram

IRQ

= 0

C to +40

Symbol

Parameter

Min

Max

Units

Notes

TrTin, TtTin

Timer Input Rise and Fall Time

5.5V

100

TwTinL

Timer Input Low Width

5.5V

TwTinH

Timer Input High Width

5.5V

2.5TpC

TpTin

Timer Input Period

5.5V

4TpC

TwIL

Int. Request Input Low Time

5.5V

1,2

TwIH

Int. Request Input High Time

5.5V

2.5TpC

1,2

Twdt

Watch-Dog Timer Time Out

5.5V

TPOR

Power-On Reset Time

5.5V

TpC

RC Oscillator Clock Period

5.5V

220

5000

Notes:

1. Timing Reference uses 0.9 V

for a logic 1 and 0.1 V

for a logic 0.

2. Interrupt request through Port 3 (P33-P31)

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PIN FUNCTIONS

Port 0 (P02-P00). Port 0 is a 3-bit, I/O programmable, bi-
directional, CMOS-compatible I/O port. These three I/O
lines can be configured under software control to be input
or output (Figure6). When Port 0 is configured as an input
port, all lines have the capability to either sink or source
(ROM mask selectable) current emulating a 100K pull-

down or pull-up resistor. Port 00-02 can be accessed
through the P0 register (register address 00). The upper 5
bits of this 8-bit register always reads "11111." Writing to
the upper 5 bits has no effect (see Figure 34). The lower 3
bits of the P0 register are read/write. Current versus pin
voltage graphs are shown in Figures 7 and 8.

Figure 6. Port 0 Configuration

Out

Pad

Pull-Down / Enable

(Mask Option)

Pull-Up Enable

(Mask Option)

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PIN FUNCTIONS (Continued)

Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bi-
directional, CMOS-compatible I/O port. These eight I/O
lines can be configured under software control to be input
or output, independently. Bits programmed as outputs
may be globally programmed as either push-pull or open-
drain. When configured as inputs, P20 and P22 have 10
kOhm (typical) pull-up resistors (Figure 9). However, P21
and P23 do not have resistors (Figure 10).

When configured as inputs, P24-P27 are configured with a
voltage divider. The voltage divider consists of an internal
25K pull-up resistor (Figure 11), and a 7.5K pull-down re-
sistor. The input levels on P24-P27 are adjusted for con-
nection to the emitters of the opto-transistors and switch at
a voltage level of 0.4 V

(

300 mV). For input voltages

on P24-P27, refer to Table 3.

Table 3. P24-P27 Input Open Circuit Voltage

(No off-chip resistance)

Min

Max

4.5V

0.95V

1.15V

5.0V

1.05V

1.25V

5.5V

1.15V

1.39V

Figure 9. Port 2 P20, P22 Configuration

Out

Open-Drain

Pad

10 Kohm,

20%

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PIN FUNCTIONS (Continued)

Port 3 (P33, P31). Port 3 is a 2-bit, CMOS-compatible
port with two fixed input lines (P33, P31). These two lines
can also be used as the interrupt sources IRQ2 and IRQ1.
P31 can also be configured as a timer input. Both lines can
be configured through ROM mask selection to sink or
source current emulating a 100K pull-up or pull-down re-

sistor (Figure 12). Port 33-31 can be accessed through
the P3 register. The upper 4 bits of this 8-bit register al-
ways reads "1111." Bit D2 reads 0 and Bit D0 reads 1. Bits
D3 and D1 represent P33 and P31 respectively (see Fig-
ure 36).

Figure 12. Port 3 P33, P31 Configuration

P31

Pad

P33

IRQ2, TIN

Data Latch

IRQ1

Pad

Pull-Up Enable
(Mask Option)

Pull-Down/Enable
(Mask Option)

Pull-Up Enable
(Mask Option)

Pull-Down/Enable
(Mask Option)

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FUNCTIONAL DESCRIPTION

The Z86319 MCU incorporates the following special fea-
tures to enhance the Z8 architectural core for use in mice,
trackballs, and other consumer applications.

Reset. Upon power-up, the Power-On Reset circuit waits
for TPOR, plus 18 clock cycles, then starts program exe-
cution at address 000CH (Figure 13). The Z86319 control
registers' reset values are shown in Table 4.

Figure 13. Internal Reset Configuration

Table 4. Z86319 Control Registers

Reset Values

Addr.

Reg.

Comments

TMR

PRE1

PRE0

P2M

Inputs after reset

P3M

P01M

IPR

IRQ

IMR

FLAGS

SPL

Delay

TPOR

18 CLK

Reset Filter

Chip

Reset

RC OSC

POR

(Cold Start)

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FUNCTIONAL DESCRIPTION (Continued)

Program Memory. The Z86319 can address up to 2 KB
of internal program memory (Figure 14). The first 12 bytes
of program memory are reserved for the interrupt vectors.
These locations contain four 16-bit vectors that corre-
spond to the four available interrupts. Bytes 0-2047 are
on-chip mask-programmed ROM.

Register File. The Register File consists of three I/O
port registers, 125 general-purpose registers, and 14 con-
trol and status registers, R0-R3, R4-R127 and R241-
R255, respectively (Figure 15). The Z86319 instructions
can access registers directly or indirectly via an 8-bit ad-
dress field. This field allows short, 4-bit register addressing
using the Register Pointer. In the 4-bit mode, the register
file is divided into eight working register groups, each oc-
cupying 16 continuous locations. The Register Pointer ad-
dresses the starting location of the active working-register
group.

Figure 14. Program Memory Map

On-Chip

ROM

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

IRQ5

IRQ4

Reserved

IRQ2

IRQ1

Reserved

IRQ5

2047

Figure 15. Register File

Stack Pointer (Bits 7-0)

R255

General-Purpose

Program Control Flags

Interrupt Mask Register

Interrupt Request Register

Interrupt Priority Register

Ports 0-1 Mode

Port 3 Mode

Port 2 Mode

T0 Prescaler

Timer/Counter0

T1 Prescaler

Timer/Counter1

Timer Mode

General-Purpose

Registers

Port 3

Port 2

Reserved

Port 0

R254

R253

R252

R251

R250

R249

R248

R247

R246

R245

R244

R243

R242

R241

R240

R127

SPL

FLAGS

IMR

IRQ

IPR

P01M

P3M

P2M

PRE0

PRE1

TMR

LOCATION

IDENTIFIERS

Not Implemented

GPR

R128

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P R E L I M I N A R Y

Stack Pointer. The Z86319 features an 8-bit Stack
Pointer (R255) used for the internal stack that resides with-
in the general-purpose registers.

Counter/Timer. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler can be driven
by internal or external clock sources, however, the T0 can
be driven by the internal clock source only (Figure 16).

The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When
both counter and prescaler reach the end of count, a timer
interrupt request IRQ4 (T0) or IRQ5 (T1) is generated.

The counter can be programmed to start, stop, continue,
or restart from the initial value. The counters can also be
programmed to stop upon reaching zero (single pass
mode) or to automatically reload the initial value and contin-
ue counting (modulo-n continuous mode).

The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and can be either the inter-
nal microprocessor clock divided by four, or an external
signal input via Port 3. The Timer Mode register configures
the external timer input (P31) as an external clock, a trigger
input that is retriggerable or not retriggerable, or as a gate
input for the internal clock.

Figure 16. Counter/Timers Block Diagram

PRE0

Initial Value

Current Value

6-Bit

Down

Counter

8-Bit

Down

Counter

OSC

6-Bit

Down

Counter

8-Bit

Down

Counter

PRE1

Initial Value

Current Value

Clock

Logic

IRQ4

IRQ5

Internal Data Bus

Write

Read

Internal Clock
Gated Clock
Triggered Clock

Write

Read

Internal Data Bus

External Clock

Internal
Clock

T P31

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FUNCTIONAL DESCRIPTION (Continued)

Interrupts. The Z86319 features four interrupts from
four different sources. These interrupts are maskable and
prioritized (Figure 17). The four sources are divided as fol-
lows: the falling edge of P31, P33, and the two
counter/timers. The Interrupt Mask Register globally or in-
dividually enables or disables the four interrupt requests
(Table 5).

When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z86319 inter-
rupts are vectored through locations in program memory.
When an interrupt machine cycle is activated, an interrupt
request is granted, thereby disabling all subsequent inter-
rupts, saving the Program Counter and Status Flags, and
branching to the program memory vector location reserved

for that interrupt. This memory location and the next byte
contain the 16-bit starting address of the Interrupt Service
Routine for that particular interrupt request.

To accommodate polled interrupt systems, interrupt inputs
are masked and the Interrupt Request Register is polled to
determine which of the interrupt requests requires service.

Table 5. Interrupt Types, Sources, and Vectors

Source

Name

Vector

Location Comments

P33

IRQ1

2,3

External

Falling Edge

P31

IRQ2 4,5

External

Falling

Edge

IRQ4

8,9

Internal

IRQ5 10,11

Internal

Figure 17. Interrupt Block Diagram

IRQ

IMR

IPR

Priority

Logic

Vector Select

Global

Interrupt

Enable

Interrupt
Request

IRQ1 - IRQ5

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RC Oscillator. The Z86319 features an on-chip RC pre-
cision oscillator that requires a 1% precision resistor exter-
nally connected between V

and pin 6 (Figure 18). The

tolerance of the RC oscillator is less than

10% over the

voltage range of 4.5V to 5.5V and over a temperature
range of 0-40

C. Pin 7 is the Analog Ground for the oscilla-

tor.

Increased parasitic board capacitance will slow down the
RC oscillator and deteriorate the RC frequency tolerance.
The minimum and maximum parasitic board capacitances
are 0.5 pF and 2 pF, respectively.

HALT Mode. This instruction turns off the internal CPU
clock but not the precision RC oscillator. The counter/tim-
ers, their interrupts, and external interrupts IRQ1 and IRQ2
remain active. The device can be recovered by interrupts,
either externally or internally generated. An interrupt must
be enabled prior to the HALT Mode, and executed to exit
the HALT Mode. After the interrupt service routine, the
program continues from the instruction after the HALT.

In order to enter HALT Mode, it is necessary to first flush
the instruction pipeline to avoid suspending execution in
mid-instruction. To flush the pipeline, the user must exe-
cute a NOP (Opcode=FFH) immediately before the HALT
instruction. i.e.:

In HALT Mode, the value of each output line prior to the
HALT instruction is retained.

Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled upon power-up of the MCU and is clocked by its own
internal RC oscillator. The WDT instruction does not affect
the Zero (Z), Sign (S), and Overflow (V) flags.

Opcode WDT (5FH). Execution of WDT clears the WDT
counter. The time interval between any 2 consecutive
WDT instructions has to be smaller than T

WDT

min.

Low Voltage Protection (V

). The device will func-

tion normally between 5.5V and 4.5V under all specified
conditions. Below 4.5V, the device is still internally func-
tional until the Low Voltage trip point (V

) is reached,

however, it is not guaranteed to meet all AC and DC Char-
acteristics. When the supply voltage drops below V

, an

automatic hardware reset occurs as V

returns above

. Essentially, this action helps in reinitializing the

Z86319.

The actual V

is a function of temperature, operating fre-

quency and process parameters. The typical V

is a

function of the ambient temperature for a frequency of 4
MHz. The device is functional down to V

voltage. The

min. operational V

is determined by the value of the V

voltage at ambient temperatures. The V

voltage in-

creases as the temperature decreases (Figure 19).

Figure 18. Oscillator Configuration

NOP

; clear the pipeline

HALT

; enter the HALT Mode

VDD

RCIN

AGND

Precision

RC Oscillator

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Z8 CONTROL REGISTERS

Figure 20. Timer Mode Register

(F1H: Read/Write)

Figure 21. Counter Timer 1 Register

(F2H: Read/Write)

Figure 22. Prescaler 1 Register

(F3H: Write Only)

D7 D6

D3 D2

0 Disable T0 Count
1 Enable T0 Count

0 No Function
1 Load T0

0 No Function
1 Load T1

0 Disable T1 Count
1 Enable T1 Count

TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)

Reserved (Must be 0)

R241 TMR

T1 Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T1 Current Value
(When READ)

R242 T1

Count Mode
0 T1 Single Pass
1 T1 Modulo

Clock Source
1 T1 Internal
0 T1 External Timing Input
(TIN) Mode

Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)

R243 PRE1

Figure 23. Counter/Timer 0 Register

(F4H: Read/Write)

Figure 24. Prescaler 0 Register

(F5H: Write Only)

Figure 25. Port 2 Mode Register

(F6H: Write Only)

Figure 26. Port 3 Mode Register

(F7H: Write Only)

T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When READ)

R244 T0

0 T0 Single Pass
1 T0 Modulo N

D5 D4

Count Mode

Reserved (Must be 0)

Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)

R245 PRE0

P27- P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT

R246 P2M

0 Port 2 Open-Drain
1 Port 2 Push-Pull

D7 D6

D3 D2

Reserved (Must be 0)

R247 P3M

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Z8 CONTROL REGISTERS (Continued)

Figure 27. Port 0 and 1 Mode Register

(F8H: Write Only)

Figure 28. Interrupt Priority Register

(F9H: Write Only)

Figure 29. Interrupt Request Register

(FAH: Read/Write)

R248 P01M

P00-P03 Mode
0 Output
1 Input

Reserved (Must be 0)

Don't care

Reserved (Must be 0)

D7 D6

Reserved
(Must be 0.)

R249 IPR

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Reserved
IRQ1>4>5>2
Reserved
IRQ4>1>5>2
IRQ5>2>1>4
IRQ5>1>4>2
IRQ5>2>4>1
IRQ5>4>1>2
IRQ2>1>4>5
IRQ1>4>2>5
IRQ2>4>1>5
IRQ4>1>2>5
IRQ2>5>1>4
Reserved
IRQ2>5>4>1
Reserved

D7 D6

D3 D2

R250 IRQ

IRQ2 = P31 Input

IRQ1 = P33 Input

IRQ4 = T0

IRQ5 = T1

Reserved (Must be 0)

Figure 30. Interrupt Mask Register

(FBH: Read/Write)

Figure 31. Flag Register

(FCH: Read/Write)

Figure 32. Register Pointer

(FDH: Read/Write)

Figure 33. Stack Pointer

(FFH: Read/Write)

D7 D6

1 Enables IRQ
(DX = IRQX)

Reserved (Must be 0)

1 Enable Interrupts

R251 IMR

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

R252 Flags

Don't Care

R253 RP

Stack Pointer Lower
Byte (SP0-SP7)

R255 SPL

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ORDERING INFORMATION

For fast results, contact your local Zilog sales offices for assistance in ordering the part required.

CODES

Package
P = DIP
S = SOIC

Temperature
S = 0

C to +40

Speed
04 = 4 MHz

Environmental
C = Plastic Standard

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components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com

Z86319

Z8631904PSC

Z8631904SSC

Example:

Z 86319 0 4 P S C is a Z86319, 4 MHz, DIP, 0

to +40

C, Plastic Standard Flow

Environmental Flow

Temperature

Package
Speed
Product Number
Zilog Prefix

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z8631904PSC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z8631904PSC