DS97DZ80502
P R E L I M I N A R Y
1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86C04/C08
1
CMOS 8-B
IT
L
OW
-C
OST
1K/2K-ROM M
ICROCONTROLLERS
FEATURES
s
18-Pin DIP and SOIC Packages
s
3.0V to 5.5V Operating Range
s
Available Temperature Ranges
A = 40
C to +125
C
E = 40
C to +105
C
S = 0
C to +70
C
s
14 Input / Output Lines
s
Six Vectored, Prioritized Interrupts from Six Different
Sources
s
Two On-Board Comparators
s
ROM Mask Options:
Low Noise
ROM Protect
Auto Latch
System Clock Driving WDT (Z86C04 only)
Permanent Watch-Dog Timer (WDT)
RC Oscillator
32 kHz Operation
s
Two Programmable 8-Bit Counter/Timers,
Each with 6-Bit Programmable Prescaler
s
Power-On Reset (POR) Timer
s
On-Chip Oscillator that Accepts RC, Crystal,
Ceramic Resonance, LC, or External Clock Drive
s
Clock-Free WDT Reset
s
Low-Power Consumption (50mw)
s
Fast Instruction Pointer
(1.0
s @ 12 MHz)
s
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
s
Software Enabled Watch-Dog Timer
s
Programmable Interrupt Polarity
s
Two Standby Modes: STOP and HALT
s
Low-Voltage Protection
GENERAL DESCRIPTION
Zilog's Z86C04/C08 are members of the Z8
MCU single-
chip microcontroller family which offer easy software/hard-
ware system expansion
.
For applications demanding powerful I/O capabilities, the
Z86C04/C08's dedicated input and output lines are
grouped into three ports, and are configurable under soft-
ware control to provide timing, status signals, or parallel
I/O.
Two on-chip counter/timers, with a large number of user
selectable modes, off-load the system of administering
real-time tasks such as counting/timing and I/O data com-
munications. Additionally, two on-board comparators pro-
cess analog signals with a common reference voltage (Fig-
ure 1).
Part
Number
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Auto
Latch
Permanent
WDT
Z86C04
Z86C08
1
2
125
125
12
12
Optional
Optional
Optional
Optional
Note:
* General-Purpose
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
2
P R E L I M I N A R Y
DS97DZ80502
GENERAL DESCRIPTION
(Continued)
Note:
All Signals with a preceding front slash, "/", are
active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
V
SS
Figure 1. Z86C04/C08
Functional Block Diagram
Port 3
Counter/
Timers (2)
Interrupt
Control
Two Analog
Comparators
Port 2
I/O
(Bit Programmable)
ALU
FLAG
Register
Pointer
Register File
Machine
Timing & Inst.
Control
Prg. Memory
Program
Counter
Vcc
GND
XTAL
Vcc
Input
Port 0
I/O
Z86C04/C08
Zilog
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
DS97DZ80502
P R E L I M I N A R Y
3
1
PIN DESCRIPTIONS
Figure 2. 18-Pin DIP Configuration
1
2
9
3
4
5
6
7
8
18
17
16
15
14
13
12
11
10
P23
P22
P33
P21
P20
GND
P02
P01
P00
P24
P25
P32
P26
P27
VCC
XTAL2
XTAL1
P31
DIP
Table 1: 18-Pin DIP and SOIC Pin Identification
Pin #
Symbol
Function
Direction
1-4
5
6
7
8
P24-P27
V
CC
XTAL2
XTAL1
P31
Port 2, Pins 4, 5, 6, 7
Power Supply
Crystal Oscillator Clock
Crystal Oscillator Clock
Port 3, Pin 1, AN1
In/Output
Output
Input
Input
9
10
11-13
14
15-18
P32
P33
P00-P02
GND
P20-P23
Port 3, Pin 2, AN2
Port 3, Pin 3, REF
Port 0, Pins 0, 1, 2
Ground
Port 2, Pins 0, 1, 2, 3
Input
Input
In/Output
In/Output
Figure 3. 18-Pin SOIC Pin Configuration
1
18
P24
P27
Vcc
XTAL2
XTAL1
P31
P32
P23
P22
P21
P20
GND
P02
P01
P00
P33
SOIC
P25
P26
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
4
P R E L I M I N A R Y
DS97DZ80502
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability. Total power
dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:
Total Power dissipation = V
DD
x [I
DD
(sum of I
OH
)] + sum of
[(V
DD
V
OH
) x I
OH
] + sum of (V
0L
x I
0L
).
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 4).
Parameter
Min
Max
Units
Ambient Temperature under Bias
40
+105
C
Storage Temperature
65
+150
C
Voltage on any Pin with Respect to V
SS
[Note 1]
0.7
+12
V
Voltage on V
DD
Pin with Respect to V
SS
0.3
+7
V
Voltage on Pin 7 with Respect to V
SS
[Note 2]
0.7
V
DD
+1
V
Total Power Dissipation
462
mW
Maximum Current out of V
SS
84
mA
Maximum Current into V
DD
84
mA
Maximum Current into an Input Pin [Note 3]
600
+600
A
Maximum Current into an Open-Drain Pin [Note 4]
600
+600
A
Maximum Output Current Sinked by Any I/O Pin
12
mA
Maximum Output Current Sourced by Any I/O Pin
12
mA
Total Maximum Output Current Sinked by Port 2
70
mA
Total Maximum Output Current Sourced by Port 2
70
mA
Notes:
1. This applies to all pins except where otherwise noted. Maximum current into pin must be
600
A.
2. There is no input protection diode from pin to V
DD
.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
Figure 4. Test Load Diagram
From Output
Under Test
150 pF
Z86C04/C08
Zilog
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
DS97DZ80502
P R E L I M I N A R Y
5
1
CAPACITANCE
T
A
= 25
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
DC ELECTRICAL CHARACTERISTICS
Parameter
Min
Max
Input capacitance
0
15 pF
Output capacitance
0
20 pF
I/O capacitance
0
25 pF
T
A
= 40
C
to +125
C
Typical
Sym
Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
V
CH
Clock Input High
Voltage
3.0V
0.8 V
CC
V
CC
+0.3
1.7
V
Driven by External
Clock Generator
5.5V
0.8 V
CC
V
CC
+0.3
2.8
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
3.0V
V
SS
0.3
0.2 V
CC
0.8
V
Driven by External
Clock Generator
5.5V
V
SS
0.3
0.2 V
CC
1.7
V
Driven by External
Clock Generator
V
IH
Input High Voltage
3.0V
0.7 V
CC
V
CC
+0.3
1.8
V
1
5.5V
0.7 V
CC
V
CC
+0.3
2.8
V
1
V
IL
Input Low Voltage
3.0V
V
SS
0.3
0.2 V
CC
0.8
V
1
5.5V
V
SS
0.3
0.2 V
CC
1.5
V
1
V
OH
Output High
Voltage
3.0V
V
CC
0.4
3.0
V
I
OH
= 2.0 mA
5
5.5V
V
CC
0.4
4.8
V
I
OH
= 2.0 mA
5
3.0V
V
CC
0.4
3.0
V
Low Noise @ I
OH
= 0.5 mA
5.5V
V
CC
0.4
4.8
V
Low Noise @ I
OH
= 0.5 mA
V
OL1
Output Low Voltage
3.0V
0.8
0.2
V
I
OL
= +4.0 mA
5
5.5V
0.6
0.1
V
I
OL
= +4.0 mA
5
3.0V
0.6
0.2
V
Low Noise @ I
OL
= 1.0 mA
5.5V
0.6
0.1
V
Low Noise @ I
OL
= 1.0 mA
V
OL2
Output Low Voltage
3.0V
1.2
0.8
V
I
OL
= +12 mA
5
5.5V
1.0
0.3
V
I
OL
= +12 mA
5
V
OFFSET
Comparator Input
Offset Voltage
3.0V
25
10
mV
5.5V
25
10
mV
V
LV
V
CC
Low Voltage
Auto Reset
1.8
3.0
2.6
V
Int. CLK Freq @ 2 MHz Max.
I
IL
Input Leakage
(Input Bias
Current of
Comparator)
3.0V
1.0
1.0
A
V
IN
= 0V, V
CC
5.5
1.0
1.0
A
V
IN
= 0V, V
CC
I
OL
Output Leakage
3.0V
1.0
1.0
A
V
IN
= 0V, V
CC
5.5V
1.0
1.0
A
V
IN
= 0V, Vcc
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