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Электронный компонент: Z86C3316SSC

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Z8 M
ICROCONTROLLER
U
SER
'
S
M
ANUAL
UM001601-0803
ii
UM001601-0803
2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica-
tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN
ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN
OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or tech-
nology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly
or otherwise, by this document under any intellectual property rights.
U
SER
'
S
M
ANUAL

T
ABLE
OF
C
ONTENTS
Chapter Title and Subsections
Page
UM001601-0803
iii
Chapter 1. Z8 MCU Product Overview
Z8 MCU Family Overview
Key Product Line Features .................................................................................................. 1-1
Product Development Support ............................................................................................. 1-3
Chapter 2. Address Space
Introduction ................................................................................................................................. 2-1
Z8 MCU Standard Register File ..................................................................................................2-1
General-Purpose Registers ................................................................................................. 2-2
RAM Protect ......................................................................................................................... 2-2
Working Register Groups ..................................................................................................... 2-2
Error Conditions ................................................................................................................... 2-4
Z8 Expanded Register File ....................................................................................................... 2-5
Z8 Control And Peripheral Registers .......................................................................................... 2-8
Standard Z8 Registers ......................................................................................................... 2-8
Expanded Z8 Registers ....................................................................................................... 2-8
Program Memory ...................................................................................................................... 2-10
Z8 External Memory ................................................................................................................. 2-11
External Data Memory ....................................................................................................... 2-11
Z8 STACKS .............................................................................................................................. 2-12
Chapter 3. Clock
Clock ........................................................................................................................................... 3-1
Frequency Control ............................................................................................................... 3-1
Clock Control .............................................................................................................................. 3-1
SCLK/TCLK Divide-By-16 Select (D0) ................................................................................. 3-2
External Clock Divide-By-Two (D1) ...................................................................................... 3-2
Oscillator Control ........................................................................................................................ 3-2
Z8 Microcontrollers
Table of Contents
ZiLOG
Chapter Title and Subsections
Page
iv
UM001601-0803
Chapter 3. Clock
(Continued)
Oscillator Operation .................................................................................................................... 3-3
Layout .................................................................................................................................. 3-3
Indications of an Unreliable Design ..................................................................................... 3-3
Circuit Board Design Rules .................................................................................................. 3-4
Crystals and Resonators ...................................................................................................... 3-5
LC Oscillator ............................................................................................................................... 3-6
RC Oscillator .............................................................................................................................. 3-6
Chapter 4. Reset--Watch-Dog Timer
Reset .......................................................................................................................................... 4-1
Reset Pin, Internal POR Operation ............................................................................................ 4-1
Watch-Dog Timer (WDT) ............................................................................................................ 4-7
Power-On-Reset (POR) .............................................................................................................. 4-8
Chapter 5. I/O Ports
I/O Ports ..................................................................................................................................... 5-1
Mode Registers .................................................................................................................... 5-1
Input and Output Registers .................................................................................................. 5-1
Port 0 .......................................................................................................................................... 5-2
General I/O Mode ................................................................................................................ 5-3
Read/Write Operations ........................................................................................................ 5-4
Handshake Operation .......................................................................................................... 5-4
Port 1 .......................................................................................................................................... 5-5
General I/O Mode ................................................................................................................ 5-5
Read/Write Operations ........................................................................................................ 5-8
Handshake Operations ........................................................................................................ 5-8
PORT 2 ....................................................................................................................................... 5-9
General Port I/O ................................................................................................................... 5-9
Read/Write Operations ...................................................................................................... 5-12
Handshake Operation ........................................................................................................ 5-12
PORT 3 ..................................................................................................................................... 5-13
General Port I/O ................................................................................................................. 5-13
Read/Write Operations ...................................................................................................... 5-18
Special Functions ............................................................................................................... 5-18
Port Handshake ........................................................................................................................ 5-19
I/O Port Reset Conditions ......................................................................................................... 5-24
Full Reset ........................................................................................................................... 5-24
Chapter 5. I/O Ports
Analog Comparators ................................................................................................................. 5-26
Z8 Microcontrollers
ZiLOG
Table of Contents
Chapter Title and Subsection
Page
UM001601-0803
v
Comparator Description ..................................................................................................... 5-26
Comparator Programming ................................................................................................. 5-28
Comparator Operation ....................................................................................................... 5-29
Interrupts ............................................................................................................................ 5-29
Comparator Definitions ...................................................................................................... 5-29
RUN Mode ......................................................................................................................... 5-29
HALT Mode ........................................................................................................................ 5-29
STOP Mode ....................................................................................................................... 5-29
Open-Drain Configuration ......................................................................................................... 5-30
Low EMI Emission .................................................................................................................... 5-30
Input Protection ........................................................................................................................ 5-31
CMOS Z8 Auto Latches ............................................................................................................ 5-32
Chapter 6. Counter/Timers
Introduction ................................................................................................................................. 6-1
Prescalers and Counter/Timers .................................................................................................. 6-2
Counter/Timer Operation ............................................................................................................ 6-3
Load and Enable Count Bits ................................................................................................ 6-3
Prescaler Operations ........................................................................................................... 6-4
T
OUT
Modes ............................................................................................................................... 6-5
T
IN
Modes ................................................................................................................................... 6-7
External Clock Input Mode ................................................................................................... 6-8
Gated Internal Clock Mode .................................................................................................. 6-9
Triggered Input Mode ......................................................................................................... 6-10
Retriggerable Input Mode .................................................................................................. 6-11
Cascading Counter/Timers ....................................................................................................... 6-11
Reset Conditions ...................................................................................................................... 6-12
Chapter 7. Interrupts
Introduction ................................................................................................................................. 7-1
Interrupt Sources ........................................................................................................................ 7-2
External Interrupt Sources ................................................................................................... 7-2
Internal Interrupt Sources .................................................................................................... 7-3
Interrupt Request (IRQ) Register Logic and Timing ................................................................... 7-4
Interrupt Initialization .................................................................................................................. 7-5
Interrupt Priority Register (IPR) Initialization ........................................................................ 7-5
Interrupt Mask Register (IMR) Initialization .......................................................................... 7-6
Interrupt Request (IRQ) Register Initialization ..................................................................... 7-7
IRQ Software Interrupt Generation ............................................................................................. 7-9
Chapter 7. Interrupts
(Continued)
Z8 Microcontrollers
Table of Contents
ZiLOG
Chapter Title and Subsections
Page
vi
UM001601-0803
Vectored Processing .................................................................................................................. 7-9
Vectored Interrupt Cycle Timing ........................................................................................ 7-11
Nesting of Vectored Interrupts ........................................................................................... 7-12
Polled Processing ..................................................................................................................... 7-12
Reset Conditions ...................................................................................................................... 7-12
Chapter 8. Power-Down Modes
Introduction ................................................................................................................................. 8-1
HALT Mode Operation ................................................................................................................ 8-1
STOP Mode Operation ............................................................................................................... 8-2
STOP-Mode Recovery Register (SMR) ...................................................................................... 8-3
Chapter 9. Serial I/O
UART Introduction ...................................................................................................................... 9-1
UART Bit-Rate Generation ......................................................................................................... 9-2
UART Receiver Operation .......................................................................................................... 9-4
Receiver Shift Register 9-4
Overwrites ............................................................................................................................ 9-5
Framing Errors ..................................................................................................................... 9-5
Parity .................................................................................................................................... 9-5
Transmitter Operation ................................................................................................................. 9-6
Overwrites ............................................................................................................................ 9-6
Parity .................................................................................................................................... 9-6
UART Reset Conditions ............................................................................................................. 9-7
Serial Peripheral Interface (SPI) ................................................................................................. 9-8
SPI Operation ............................................................................................................................. 9-9
SPI Compare .............................................................................................................................. 9-9
SPI Clock .................................................................................................................................... 9-9
Receive Character Available and Overrun ............................................................................... 9-11
Chapter 10. External Interface
Introduction ............................................................................................................................... 10-1
Pin Descriptions ........................................................................................................................ 10-2
AS ...................................................................................................................................... 10-2
DS ...................................................................................................................................... 10-2
R/W .................................................................................................................................... 10-2
DM ..................................................................................................................................... 10-2
P07 - P00 ........................................................................................................................... 10-2
P17 - P10 .......................................................................................................................... 10-2
RESET ............................................................................................................................... 10-2
XTAL1, XTAL2 ................................................................................................................... 10-2
Z8 Microcontrollers
ZiLOG
Table of Contents
Chapter Title and Subsection
Page
UM001601-0803
vii
External Addressing Configuration ........................................................................................... 10-3
External Stacks ......................................................................................................................... 10-4
Data Memory ............................................................................................................................ 10-4
Bus Operation ........................................................................................................................... 10-5
Address Strobe .................................................................................................................. 10-6
Data Strobe ........................................................................................................................ 10-6
Extended Bus Timing ............................................................................................................... 10-7
Instruction Timing ..................................................................................................................... 10-9
Z8 Reset Conditions ............................................................................................................... 10-10
Chapter 11. Addressing Modes
Introduction ............................................................................................................................... 11-1
Z8 Addressing Modes ........................................................................................................ 11-1
Z8 Register Addressing (R) ...................................................................................................... 11-2
Z8 Indirect Register Addressing (IR) ........................................................................................ 11-3
Z8 Indexed Addressing (X) ....................................................................................................... 11-5
Z8 Direct Addressing (DA) ........................................................................................................ 11-6
Z8 Relative Addressing (RA) .................................................................................................... 11-7
Z8 Immediate Data Addressing (IM) ......................................................................................... 11-8
Chapter 12. Instruction Set
Z8 Functional Summary ........................................................................................................... 12-1
Processor Flags..........................................................................................................................12-2
Condition Codes .........................................................................................................................12-5
Notation and Binary Coding........................................................................................................12-6
Z8 Instruction Summary .............................................................................................................12-8
Instruction Description and Formats.........................................................................................12-11
viii
UM001601-0803
U
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ANUAL
L
IST
OF
F
IGURES
Figure Title
Page
UM001601-0803
ix
Chapter 1. Z8 MCU Product Overview
Z8 MCU Block Diagram ...............................................................................................................1-2
Chap[ter 2. Address Space
16-Bit Register Addressing ......................................................................................................... 2-2
Accessing Individual Bits (Example) ............................................................................................2-2
Working Register Addressing Examples .....................................................................................2-3
Register Pointer ...........................................................................................................................2-4
Expanded Register File Architecture ...........................................................................................2-5
Register Pointer (FDH) Example .................................................................................................2-6
Z8 Program Memory Map ..........................................................................................................2-10
External Memory Map ...............................................................................................................2-11
Stack Pointer .............................................................................................................................2-12
Stack Operations .......................................................................................................................2-12
Chapter 3. Clock
Z8 Clock Circuit ...........................................................................................................................3-1
Stop-Mode Recovery Register
(Write-Only Except D7, Which is Read-Only) ...................................................................3-1
External Clock Circuit ..................................................................................................................3-2
Port Configuration Register (PCON) (Write-Only) .......................................................................3-2
Pierce Oscillator with Internal Feedback Circuit ..........................................................................3-3
Circuit Board Design Rules .........................................................................................................3-4
Crystal/Ceramic Resonator Oscillator .........................................................................................3-5
LC Clock ......................................................................................................................................3-5
Chapter 3. Clock
(Continued)
External Clock .............................................................................................................................3-5
Z8 Microcontrollers
List of Figures
ZiLOG
Figure Title
Page
x
UM001601-0803
RC Clock .....................................................................................................................................3-6
Chapter 4. Reset--Watch-Dog Timer
Reset Timing ...............................................................................................................................4-2
Example of External Power-On Reset Circuit ..............................................................................4-3
Example of Z8 Reset with /RESET Pin, WDT, SMR, and POR ..................................................4-5
Example of Z8 Reset with WDT, SMR, and POR ........................................................................4-6
Example of Z8 Watch-Dog Timer Mode Register (Write-Only) ...................................................4-7
Example of Z8 with Simple SMR and POR .................................................................................4-8
Chapter 5. I/O Ports
I/O Ports and Mode Registers .....................................................................................................5-1
Ports 0, 1, 2 Generic Block Diagram ..........................................................................................5-2
Port 0 Configuration with Open-Drain Capability, Auto Latch,
and Schmitt-Trigger ..........................................................................................................5-3
Port 0 Configuration with TTL Level Shifter ................................................................. 5-4
Port 0 I/O Operation ....................................................................................................................5-5
Port 0 Handshake Operation .......................................................................................................5-5
Port 1 Configuration with Open-Drain Capability, Auto Latch,
and Schmitt-Trigger ..........................................................................................................5-6
Port 1 Configuration with TTL Level Shifter .................................................................................5-7
Port 1 I/O Operation ....................................................................................................................5-8
Handshake Operation ..................................................................................................................5-8
Port 2 I/O Mode Configuration .....................................................................................................5-9
Port 2 Configuration with Open-Drain Capability, Auto Latch,
and Schmitt-Trigger ..........................................................................................................5-9
Port 2 Configuration with TTL Level Shifter ...............................................................................5-10
Port 2 Configuration with Open-Drain Capability, Auto Latch,
Schmitt-Trigger and SPI ..................................................................................................5-11
Port 2 Handshake Configuration 5 ..............................................................................................-12
Port 2 Handshaking ...................................................................................................................5-12
Port 3 Block Diagram .................................................................................................................5-13
Port 3 Configuration with Comparator, Auto Latch, and Schmitt-Trigger ..................................5-14
Port 3 Configuration with Comparator .......................................................................................5-15
Chapter 5. I/O Ports
(Continued)
Port 3 Configuration with SPI and Comparator Outputs
Using P34 and P35 .........................................................................................................5-16
Port 3 Configuration with TTL Level Shifter and Auto Latch ......................................................5-17
Port 3 Mode Register Configuration ..........................................................................................5-18
Z8 Input Handshake ..................................................................................................................5-20
Z8 Microcontrollers
ZiLOG
List of Figures
Figure Title
Page
UM001601-0803
xi
Z8 Output Handshake ...............................................................................................................5-21
Output Strobed Handshake on Port 2 .......................................................................................5-23
Input Strobed Handshake on Port 2 ..........................................................................................5-23
Port 0/1 Reset ............................................................................................................................5-24
Port 2 Reset ...............................................................................................................................5-25
Port 3 Mode Reset .....................................................................................................................5-25
Port 3 Input Analog Selection ....................................................................................................5-26
Port 3 Comparator Output Selection .........................................................................................5-26
Port Configuration of Comparator Inputs on P31, P32, and P33 ...............................................5-27
Port 3 Configuration ...................................................................................................................5-28
Port 2 Configuration ...................................................................................................................5-30
Port Configuration Register (PCON) (Write-Only) .....................................................................5-30
Diode Input Protection ...............................................................................................................5-31
OTP Diode Input Protection .......................................................................................................5-31
Simplified CMOS Z8 I/O Circuit .................................................................................................5-32
Auto Latch Equivalent Circuit ...................................................................................... 5-33
Effect of Pulldown Resistors on Auto Latches ...........................................................................5-33
Chapter 6. Counter/Timers
Counter/Timer Block Diagram .....................................................................................................6-1
Counter/Timer Register Map .......................................................................................................6-2
Prescaler 0 Register ....................................................................................................................6-2
Prescaler 1 Register ....................................................................................................................6-2
Counter / Timer 0 and 1 Registers ..............................................................................................6-2
Timer Mode Register ...................................................................................................................6-3
Starting The Count ......................................................................................................................6-3
Counting Modes ..........................................................................................................................6-3
Timer Mode Register (T
OUT
Operation) .......................................................................................6-5
Port 3 Mode Register (T
OUT
Operation) .......................................................................................6-5
T0 and T1 Output Through T
OUT
.................................................................................................6-6
Chapter 6. Counter/Timers
(Continued)
Internal Clock Output Through T
OUT
........................................................................................... 6-6
Timer Mode Register (T
IN
Operation) ..........................................................................................6-7
Prescaler 1 Register (T
IN
Operation) ...........................................................................................6-7
External Clock Input Mode ..........................................................................................................6-8
Gated Clock Input Mode ..............................................................................................................6-9
Triggered Clock Mode ...............................................................................................................6-10
Cascaded Counter/Timers .........................................................................................................6-11
Counter/Timer Reset .................................................................................................................6-12
Prescaler 1 Register Reset ........................................................................................................6-12
Z8 Microcontrollers
List of Figures
ZiLOG
Figure Title
Page
xii
UM001601-0803
Prescaler 0 Reset ......................................................................................................................6-12
Timer Mode Register Reset .......................................................................................................6-12
Chapter 7. Interrupts
Interrupt Control Registers ..........................................................................................................7-1
Interrupt Block Diagram ...............................................................................................................7-1
Interrupt Sources IRQ0-IRQ2 Block Diagram ..............................................................................7-2
Interrupt Source IRQ3 Block Diagram .........................................................................................7-3
IRQ Register Logic ......................................................................................................................7-4
Interrupt Request Timing .............................................................................................................7-4
Interrupt Priority Register ............................................................................................... 7-5
Interrupt Mask Register ...............................................................................................................7-6
Interrupt Request Register ..........................................................................................................7-7
IRQ Reset Functional Logic Diagram ..........................................................................................7-8
Effects of an Interrupt on the STACK ..........................................................................................7-9
Interrupt Vectoring .....................................................................................................................7-10
Z8 Interrupt Acknowledge Timing .............................................................................................7-11
Chapter 8. Power-Down Modes
STOP-Mode Recovery Register
(Write-Only Except Bit D7, Which Is Read-Only) ..............................................................8-3
STOP-Mode Recovery Source ....................................................................................................8-4
Chapter 9. Serial I/O
UART Block Diagram ..................................................................................................................9-1
Port 3 Mode Register (P3M) and Bit-Rate Generation ................................................................9-2
Bit Rate Divide Chain ..................................................................................................... 9-2
Prescaler 0 Register (PRE0) Bit-Rate Generation ......................................................................9-3
Timer Mode Register (TMR) Bit Rate Generation .......................................................................9-4
Receiver Timing ...........................................................................................................................9-4
Receiver Data Formats .................................................................................................... 9-5
Port 3 Mode Register (P3M) Parity ..............................................................................................9-5
Transmitter Data Formats ............................................................................................................9-6
SIO Register Reset ......................................................................................................................9-7
P3M Register Reset ....................................................................................................................9-7
SPI Control Register (SCON) ......................................................................................................9-8
SPI System Configuration .........................................................................................................9-10
SPI Timing .................................................................................................................................9-11
SPI Logic ...................................................................................................................................9-12
SPI Data In/Out Configuration ...................................................................................................9-13
SPI Clock / SPI Slave Select Output Configuration ...................................................................9-14
Z8 Microcontrollers
ZiLOG
List of Figures
Figure Title
Page
UM001601-0803
xiii
Chapter 10. External Interface
Z8 External Interface Pins .........................................................................................................10-1
External Address Configuration .................................................................................................10-3
Z8 Stack Selection .....................................................................................................................10-4
Port 3 Data Memory Operation ..................................................................................................10-4
External Instruction Fetch or Memory Read Cycle ....................................................................10-5
External Memory Write Cycle ....................................................................................................10-6
Extended External Instruction Fetch or Memory Read Cycle ....................................................10-7
Extended External Memory Write Cycle ....................................................................................10-8
Extended Bus Timing ................................................................................................................10-8
Instruction Cycle Timing (One-Byte Instructions) ......................................................................10-9
Instruction Cycle Timing (Two and Three Byte Instructions) ...................................................10-10
Chapter 11. Addressing Modes
8-Bit Register Addressing ..........................................................................................................11-2
4-Bit Register Addressing ..........................................................................................................11-2
4-Bit Register Addressing ..........................................................................................................11-3
Indirect Register Addressing to Program or Data Memory ........................................................11-4
Indexed Register Addressing ....................................................................................................11-5
Direct Addressing ......................................................................................................................11-6
Relative Addressing ...................................................................................................................11-7
Immediate Data Addressing ......................................................................................................11-8
Z8 Microcontrollers
List of Figures
ZiLOG
Figure Title
Page
xiv
UM001601-0803
U
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L
IST
OF
T
ABLES
Table Title
Page
UM001601-0803
xv
Chapter 1. Z8 MCU Product Overview
ZiLOG General-Purpose Microcontroller Product Family ........................................................... 1-3
Chapter 2. Address Space
Z8 Standard Register File ........................................................................................................... 2-1
Working Register Groups ........................................................................................................... 2-3
ERF Bank Address ..................................................................................................................... 2-6
Z8 Expanded Register File Bank Layout .................................................................................... 2-7
Expanded Register File Register Bank C, WR Group 0 ............................................................. 2-8
Expanded Register File Bank 0, WR Group 0 ............................................................................ 2-9
Expanded Register File Bank F, WR Group 0 ............................................................................ 2-9
Chapter 4. Reset--Watch-Dog Timer
Sample Control and Peripheral Register Reset Values (ERF Bank 0) ....................................... 4-2
Expanded Register File Bank 0 Reset Values at RESET ........................................................... 4-3
Sample Expanded Register File Bank C Reset Values .............................................................. 4-4
Sample Expanded Register File Bank F Reset Values .............................................................. 4-4
Time-Out Period of the WDT ...................................................................................................... 4-7
Chapter 5. I/O Ports
Port 3 Line Functions ................................................................................................................ 5-19
Chapter 7. Interrupts
Interrupt Types, Sources, and Vectors ....................................................................................... 7-2
Interrupt Priority .......................................................................................................................... 7-5
Interrupt Group Priority ............................................................................................................... 7-6
IRQ Register Configuration ........................................................................................................ 7-8
Z8 Microcontrollers
List of Tables
ZiLOG
Table Title
Page
xvi
UM001601-0803
Chapter 8. Power-Down Modes
STOP-Mode Recovery Source ................................................................................................... 8-4
Chaper 9. Serial I/O
UART Register Map ................................................................................................................... 9-2
Bit Rates ..................................................................................................................................... 9-3
SPI Pin Configuration ................................................................................................................. 9-8
UM001601-0803
1-1
U
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ANUAL
C
HAPTER
1
Z8 MCU P
RODUCT
O
VERVIEW
1.1 Z8 MCU FAMILY OVERVIEW
The ZiLOG Z8 microcontroller (MCU) product line continues to
expand with new product introductions. ZiLOG MCU products
are targeted for cost-sensitive, high-volume applications includ-
ing consumer, automotive, security, and HVAC. It includes
ROM-based products geared for high-volume production (where
software is stable) and one-time programmable (OTP) equiva-
lents for prototyping as well as volume production where time to
market or code flexibility is critical (Table 1-1). A variety of
packaging options are available including plastic DIP, SOIC,
PLCC, and QFP.
A generalized Z8 MCU
block diagram is shown in Figure 1-1.
The same on-chip peripherals are used across the MCU product
line with the primary differences being the amount of
ROM/RAM, number of I/O lines present, and packaging/temper-
ature ranges available. This allows code written for one MCU
device to be easily ported to another family member.
1.1.1 Key Product Line Features
General-Purpose Register (GPR) File: Every RAM register
acts like an accumulator, speeding instruction execution and
maximizing coding efficiency. Working register groups allow
fast context switching.
Flexible I/O: I/O byte, nibble, and/or bit programmable as
inputs or outputs. Outputs are software programmable as
open-drain or push-pull on a port basis. Inputs are Schmitt-
triggered with auto latches to hold unused inputs at a known
voltage state.
Analog Inputs: Three input pins are software programmable
as digital or analog inputs. When in the analog mode, two
comparator inputs are provided with a common reference
input. These inputs are ideal for a variety of common
functions, including threshold level detection, analog-to-
digital conversion, and short circuit detection. Each analog
input provides a unique maskable interrupt input.
Timer/Counter(T/C): The T/C consists of a programmable
6-bit prescaler and 8-bit downcounter, with maskable interrupt
upon end-of-count. Software controls T/C load/start/stop,
countdown read (at any time on the fly), and maskable end-of-
count interrupt. Special functions available include T
IN
(external counter input, external gate input, or external trigger
input) and T
OUT
(external access to timer output or the internal
system clock.) These special functions allow accurate
hardware input pulse measurement and output waveform
generation.
Interrupts: There are six vectored interrupt sources with
software-programmable enable and priority for each of the six
sources.
Watch-Dog Timer (WDT): An internal WDT circuit is
included as a fail-safe mechanism so that if software strays
outside the bounds of normal operation, the WDT will timeout
and reset the MCU. To maximize circuit robustness and
reliability, the default WDT clock source is an internal RC
circuit (isolated from the device clock source).
Auto Reset/Low-Voltage Protection: All family devices
have internal Power-On Reset. ROM devices add low-voltage
protection. Low-voltage protection ensures the MCU is in a
known state at all times (in active RUN mode or RESET)
without external hardware (or a device reset pin).
Low-EMI Operation: Mode is programmable via software or
as a mask option. This new option provides for reduced
radiated emission via clock and output drive circuit changes.
Z8 Microcontrollers
Z8 MCU Product Overview
ZiLOG
1-2
UM001601-0803
1.1 Z8 MCU FAMILY OVERVIEW
(Continued)
Low-Power: CMOS with two standby modes; STOP and
HALT.
Full Z8 Instruction Set: Forty-eight basic instructions,
supported by six addressing modes with the ability to operate
on bits, nibbles, bytes, and words.
Figure 1-1. Z8 MCU Block Diagram
Port 3
Counter/
Timers (2)
Interrupt
Control
Analog
Comparators (2)
Output
Input
ALU
FLAG
Register
Pointer
Register File
256 x 8-Bit
Machine Timing
& Instruction Control
RESET, WDT,
POR
Prg. Memory
512/K x 8-Bit
Program
Counter
VCC
GND
XTAL
Address or I/O
(Nibble Programmable)
Port 2
Port 0
Port 1
/AS /DS R//W /RESET
4
4
8
Address/Data or I/O
(Byte Programmable)
I/O
(Bit Programmable)
Z8 Microcontrollers
ZiLOG
Z8 MCU Product Overview
UM001601-0803
1-3
1.1.2 Product Development Support
The Z8 MCU product line is fully supported with a range of
cross assemblers, C compilers, ICEBOX emulators, single and
gang OTP/EPROM programmers, and software simulators.
The Z86CCP01ZEM low-cost Z8 CCPTM real-time emula-
tor/programmer kit was designed specifically to support all the
products outlined in Table 1-1.
The Z86CCP01ZEM kit comes with:
Z8 CCP Evaluation Board
Z8 CCP Power Cable
ZiLOG Developer's Studio (ZDS) CD-ROM , Including
Windows-Based
1
GUI Host Software
1999 ZiLOG Technical Library
Z8 CCP User's Manual
A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also
available and provides an RS-232 cable and power cable along
with the 28- and 40- pin ZIF sockets and 28- and 40- pin target
connector cables required to emulate/program 28/40 pin devices.
1. Windows is a trademark of the Microsoft Corporation.
Table 1-1. ZiLOG General-Purpose Microcontroller Product Family
PRODUCT
ROM/RAM
I/0
T/C
AN
INT
WDT
POR
V
BO
RC
SPEED
PIN
IN
(MHz)
COUNT
Z86C03
512/60
14
1
2
6
F
Y
Y
Y
8
18
Z86E03
512/60
14
1
2
6
F
Y
N
Y
8
18
Z86C04
1K/124
14
2
2
6
F
Y
Y
Y
8
18
Z86E04
1K/124
14
2
2
6
F
Y
N
Y
8
18
Z86C06
1K/124
14
2
2
6
P
Y
Y
Y
12
18
Z86E06
1K/124
14
2
2
6
P
Y
N
Y
12
18
Z86C08
2K/124
14
2
2
6
F
Y
Y
Y
12
18
Z86E08
2K/124
14
2
2
6
F
Y
N
Y
12
18
Z86C30
4K/236
24
2
2
6
P
Y
Y
Y
12
28
Z86E30
4K/236
24
2
2
6
P
Y
N
Y
12
28
Z86C31
2K/124
24
2
2
6
P
Y
Y
Y
8
28
Z86E31
2K/124
24
2
2
6
P
Y
N
Y
8
28
Z86C40
4K/236
32
2
2
6
P
Y
Y
Y
16
40/44
Z86E40
4K/236
32
2
2
6
P
Y
N
Y
16
40/44
Note: Z86Cxx signify ROM devices; 86xx signify EPROM devices; F = fixed; P = programmable
1-4
UM001601-0803
2-1
U
SER
'
S
M
ANUAL
C
HAPTER
2
A
DDRESS
S
PACE
2.1 INTRODUCTION
Four address spaces are available for the Z8 MCU
:
The Z8 Standard Register File contains addresses for
peripheral, control, all general-purpose, and all I/O port
registers. This is the default register file specification.
The Z8 Expanded Register File (ERF) contains addresses for
control and data registers for additional peripherals/features.
Z8 External Program Memory contains addresses for all
memory locations having executable code and/or data.
Z8 External Data Memory contains addresses for all memory
locations that hold data only, whether internal or external.
2.2 Z8 MCU STANDARD REGISTER FILE
The Z8 Standard Register File totals up to 256 consecutive bytes
(Registers). The register file consists of 4 I/O ports (00H-03H),
236 General-Purpose Registers (04H-EFH), and 16 control reg-
isters (F0H-FFH). Table 2-1 shows the layout of the register file,
including register names, locations, and identifiers.
Table 2-1. Z8 Standard Register File
Hex
Register
Register
Address
Description
Identifier
FF
Stack Pointer Low Byte
SPL
FE
Stack Pointer High Byte
SPH
FD
Register Pointer
RP
FC
Program Control Flags
FLAGS
FB
Interrupt Mask Register
IMR
FA
Interrupt Request Register
IRQ
F9
Interrupt Priority Register
IPR
F8
Port 0-1 Mode Register
P01M
F7
Port 3 Mode Register
P3M
F6
Port 2 Mode Register
P2M
F5
T0 Prescaler
PRE0
F4
Timer/Counter 0
T0
F3
T1 Prescaler
PRE1
F2
Timer/Counter 1
T1
F1
Timer Mode
TMR
F0
Serial I/O
SIO
EF
R239
.
General-Purpose
.
.
Registers (GPR)
.
.
.
04
R4
03
Port 3
P3
02
Port 2
P2
01
Port 1
P1
00
Port 0
P0
Table 2-1. Z8 Standard Register File
Hex
Register
Register
Address
Description
Identifier
Z8 Microcontrollers
Address Space
ZiLOG
2-2
UM001601-0803
2.2 Z8 MCU STANDARD REGISTER FILE
(Continued)
Registers can be accessed as either 8-bit or 16-bit registers using
Direct, Indirect, or Indexed Addressing. All 236 general-purpose
registers can be referenced or modified by any instruction that
accesses an 8-bit register, without the need for special
instructions. Registers accessed as 16 bits are treated as even-
odd register pairs (there are 118 valid pairs). In this case, the
data's Most Significant Byte (MSB) is stored in the even
numbered register, while the Least Significant Byte (LSB) goes
into the next higher odd numbered register (Figure 2-1).
By using a logical instruction and a mask, individual bits within
registers can be accessed for bit set, bit clear, bit complement, or
bit test operations. For example, the instruction AND R15,
MASK performs a bit clear operation. Figure 2-2 shows this ex-
ample.
When instructions are executed, registers are read when defined
as sources and written when defined as destinations. All Gener-
al-Purpose Registers function as accumulators, address pointers,
index registers, stack areas, or scratch pad memory.
2.2.1 General-Purpose Registers
General-Purpose Registers (GPR) are undefined after the device
is powered up. The registers keep their last value after any reset,
as long as the reset occurs in the V
CC
voltage-specified operating
range. It will not keep its last state from a V
LV
reset if V
CC
drops
below 1.8v.
Note: Registers in Bank E0-EF may only be accessed through
the working register and indirect addressing modes. Direct
access cannot be used because the 4-bit working register address
mode already uses the format [E | dst], where dst represents the
working register number from 0H to FH.
2.2.2 RAM Protect
The upper portion of the register file address space 80H to EFH
(excluding the control registers) may be protected from reading
and writing. The RAM Protect bit option is mask-programmable
and is selected by the customer when the ROM code is submit-
ted. After the mask option is selected, the user activates this fea-
ture from the internal ROM code to turn off/on the RAM Protect
by loading either a 0 or 1 into the IMR register, bit D6. A 1 in D6
enables RAM Protect. Only devices that use registers 80H to
EFH offer this feature.
2.2.3 Working Register Groups
Z8 instructions can access 8-bit registers and register pairs (16-
bit words) using either 4-bit or 8-bit address fields. 8-bit address
fields refer to the actual address of the register. For example,
Register 58H is accessed by calling upon its 8-bit binary equiv-
alent, 01011000 (58H).
With 4-bit addressing, the register file is logically divided into
16 Working Register Groups of 16 registers each, as shown in
Table 2-2. These 16 registers are known as Working Registers.
A Register Pointer (one of the control registers, FDH) contains
the base address of the active Working Register Group. The high
nibble of the Register Pointer determines the current Working
Register Group.
When accessing one of the Working Registers, the 4-bit address
of the Working Register is combined within the upper four bits
(high nibble) of the Register Pointer, thus forming the 8-bit ac-
tual address. Figure 2-3 illustrates this operation. Since working
registers are typically specified by short format instructions,
there are fewer bytes of code needed, which reduces execution
time. In addition, when processing interrupts or changing tasks,
the Register Pointer speeds context switching. A special Set
Register Pointer (SRP) instruction sets the contents of the Reg-
ister Pointer.
Figure 2-1. 16-Bit Register Addressing
Figure 2-2. Accessing Individual Bits (Example)
MSB
LSB
Rn Rn+1
n = Even Address
0 1 0 1 0 0 0 0
R15
0 1 1 1 0 0 0 0
1 1 0 1 1 1 1 1
MASK
R15
AND R15, DFH ;Clear Bit 5 of Working Register 15
Z8 Microcontrollers
ZiLOG
Address Space
UM001601-0803
2-3
Table 2-2. Working Register Groups
Register Pointer
Working
Actual
(FDH)
Register Group
Registers
High Nibble
(HEX)
(HEX)
1111(B)
F
F0FF
1110(B)
E
E0EF
1101(B)
D
D0DF
1100(B)
C
C0CF
1011(B)
B
B0BF
1010(B)
A
A0AF
1001(B)
9
909F
1000(B)
8
808F
0111(B)
7
707F
0110(B)
6
606F
0101(B)
5
505F
0100(B)
4
404F
0011(B)
3
303F
0010(B)
2
202F
0001(B)
1
101F
0000(B)
0
000F
Figure 2-3. Working Register Addressing Examples
0 1 1 1 0 1 1 0
Register Pointer (FHD), Standard Register File
0 1 1 1 0 0 0 0
1 1 0 1 1 1 1 1
INC R6 (Instruction, Short Format)
Actual Register Address (76H)
Z8 Microcontrollers
Address Space
ZiLOG
2-4
UM001601-0803
2.2 Z8 MCU STANDARD REGISTER FILE
(Continued)
Note: The full register file is shown. Please refer to the selected device product specification for actual file size.
2.2.4 Error Conditions
Registers in the Z8 Standard Register File must be correctly used
because certain conditions produce inconsistent results and
should be avoided.
Registers F3H and F5H-F9H are write-only registers. If an
attempt is made to read these registers, FFH is returned.
Reading any write-only register will return FFH.
When register FDH (Register Pointer) is read, the least
significant four bits (lower nibble) will indicate the current
Expanded Register File Bank. (Example: 0000 indicates the
Standard Register File, while 1010 indicates Expanded
Register File Bank A.)
When Ports 0 and 1 are defined as address outputs, registers
00H and 01H will return 1s in each address bit location when
read.
Writing to bits that are defined as timer output, serial output,
or handshake output will have no effect.
The Z8 instruction DJNZ uses any general-purpose working
register as a counter.
Logical instructions such as OR and AND require that the
current contents of the operand be read. They therefore will
not function properly on write-only registers.
The WDTMR register must be written within the first 60
internal system clocks (SCLK) of operation after a reset.
Figure 2-4. Register Pointer
FF
F0
R7 R6 R5 R4 R3 R2 R1 R0
Specified Working Register Group
R253
I/O Ports
Working Register Group 1
Working Register Group 0
Working Register Group F
EF
80
7F
70
6F
60
5F
50
4F
40
3F
30
2F
20
1F
10
0F
00
The lower nibble
of the register
file address
(provided by the
instruction) points
to the specified
register.
The upper nibble of the register file address,
provided by the register pointer, specifies
the active working-register group.
(Register Pointer)
R15 to R0
R15 to R4
R3 to R0
Z8 Microcontrollers
ZiLOG
Address Space
UM001601-0803
2-5
2.3 Z8 EXPANDED REGISTER FILE
The standard register file of the Z8 has been expanded to form
16 Expanded Register File (ERF) Banks (Figure 2-5). Each ERF
Bank consists of up to 256 registers (the same amount as in the
Standard Register File) that can then be divided into 16 Working
Register Groups. This expansion allows for access to additional
feature/peripheral control and data registers.
Note: The fully implemented register file is shown. Please refer to the specific product specification for actual register file architecture implemented.
Currently, three out of the possible sixteen Z8 ERF Banks have
been implemented. ERF Bank 0, also known as the Z8 Standard
Register File, has all 256 bytes defined (Figure 2-1). Only Work-
ing Register Group 0 (register addresses 00H to 0FH) have been
Figure 2-5. Expanded Register File Architecture
Z8 Register File
(F) 0F WDTMR
Expanded Register
FF
0F
7F
F0
00
Expanded Register File
Bank (F)
(F) 0E Reserved
(F) 0D Reserved
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 0E Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
(0) 0F GPR
Expanded Register File
Bank (0)
(0) 0E GPR
(0) 0D GPR
(0) 0C GPR
(0) 0B GPR
(0) 0A GPR
(0) 09 GPR
(0) 08 GPR
(0) 07 GPR
(0) 06 GPR
(0) 05 GPR
(0) 04 GPR
(0) 03 P3
(0) 02 P2
(0) 01 P1
(0) 00 P0
(C) 0F Reserved
Expanded Register File
Bank (C)
(C) 0E Reserved
(C) 0D Reserved
(C) 0C Reserved
(C) 0B Reserved
(C) 0A Reserved
(C) 09 Reserved
(C) 08 Reserved
(C) 07 Reserved
(C) 06 Reserved
(C) 05 Reserved
(C) 04 Reserved
(C) 03 Reserved
(C) 02 SCON
(C) 01 RXBUF
(C) 00 SCOMP
D7 D6 D5 D4 D3 D2 D1 D0
Working Register
Group Pointer
Group Pointer
Register Pointer
Z8 Microcontrollers
Address Space
ZiLOG
2-6
UM001601-0803
2.3 Z8 EXPANDED REGISTER FILE
(Continued)
defined for ERF Bank C and ERF Bank F (Table 2-4). All other
working register groups in ERF Banks C and F, as well as the re-
maining thirteen ERF Banks, are not implemented. All are re-
served for future use.
When an ERF Bank is selected, register addresses 00H to 0FH
access those sixteen ERF Bank registers in effect replacing the
first sixteen locations of the Z8 Standard Register File.
For example, if ERF Bank C is selected, the Z8 Standard Regis-
ters 00H through 0FH are no longer accessible. Registers 00H
through 0FH are now the 16 registers from ERF Bank C, Work-
ing Register Group 0. No other Z8 Standard Registers are effect-
ed since only Working Register Group 0 is implemented in ERF
Bank C.
Access to the ERF is accomplished through the Register Pointer
(FDH). The lower nibble of the Register Pointer determines the
ERF Bank while the upper nibble determines the Working Reg-
ister Group within the register file (Figure 2-6).
The value of the lower nibble in the Register Pointer (FDH) cor-
responds to the ERF Bank identification. Table 2.3 shows the
lower nibble value and the register file assigned to it.
Figure 2-6. Register Pointer (FDH) Example
0 1 1 1
1 1 0 0
Working
Select ERF Bank C(H)
Register
Group
Expanded
Register
Bank
Working Register Group 7(H)
Table 2-3. ERF Bank Address
Register Pointer
(FDH)
Low Nibble
Hex
Register File
0000(B)
0
Z8 Standard Register File *
0001(B)
1
Expanded Register File Bank 1
0010(B)
2
Expanded Register File Bank 2
0011(B)
3
Expanded Register File Bank 3
0100(B)
4
Expanded Register File Bank 4
0101(B)
5
Expanded Register File Bank 5
0110(B)
6
Expanded Register File Bank 6
0111(B)
7
Expanded Register File Bank 7
1000(B)
8
Expanded Register File Bank 8
1001(B)
9
Expanded Register File Bank 9
1010(B)
A
Expanded Register File Bank A
1011(B)
B
Expanded Register File Bank B
1100(B)
C
Expanded Register File Bank C
1101(B)
D
Expanded Register File Bank D
1110(B)
E
Expanded Register File Bank E
1111(B)
F
Expanded Register File Bank F
Note: The Z8 Standard Register File is equivalent to Expanded Reg-
ister File Bank 0.
Z8 Microcontrollers
ZiLOG
Address Space
UM001601-0803
2-7
The upper nibble of the register pointer selects which group of
16 bytes in the Register File, out of the full 256, will be accessed
as working registers.
For example:
(See Figure 2-4)
Since enabling an ERF Bank (C or F) only changes register ad-
dresses 00H to 0FH, the working register pointer can be used to
access either the selected ERF Bank (Bank C or F, Working
Register Group 0) or the Z8 Standard Register File (ERF Bank
0, Working Register Groups 1 through F).
Note: When an ERF Bank other than Bank 0 is enabled, the first
16 bytes of the Z8 Standard Register File (I/O ports 0 to 3,
Groups 4 to F) are no longer accessible (the selected ERF Bank,
Registers 00H to 0FH are accessed instead). It is important to re-
initialize the Register Pointer to enable ERF Bank 0 when these
registers are required for use.
The SPI register is mapped into ERF Bank C. Access is easily
done using the following example:
Please refer to the specific product specification to determine the
above registers are implemented.
R253 RP = 00H
;ERF Bank 0, Working Reg. Group 0.
R0 = Port 0 = 00H
R1 = Port 1 = 01H
R2 = Port 2 = 02H
R3 = Port 3 = 03H
R11 = GPR 0BH
R15 = GPR 0FH
If:
R253 RP = 0FH
;ERF Bank F, Working Reg. Group 0.
R0 = PCON = 00H
R1 = Reserved = 01H
R2 = Reserved = 02H
R11 = SMR = 0BH
R15 = WDTMR = 0FH
If:
R253 RP = FFH
;ERF Bank F, Working Reg. Group F.
00H = PCON
R0 = SI0
01H= Reserved
R1 = TMR
02H= Reserved
...
R2 = T1
0BH = SMR
...
R15 = SPL
0FH = WDTMR
LD
RP, #0CH
;Select ERF Bank C working
;register group 0 for access.
LD
R2,#xx
;access SCON
LD
R1, #xx
;access RXBUF
LD
RP, #00H
;Select ERF Bank 0 so I/O ports
;are again accessible.
Table 2-4. Z8 Expanded Register File Bank Layout
Expanded
Register File
Bank
ERF
F(H)
PCON, SMR, WDT,
(00H, 0BH, 0FH),
Working Register Group 0
only implemented.
E(H)
Not Implemented
(Reserved)
D(H)
Not Implemented
(Reserved)
C(H)
SPI Registers: SCOMP,
RXBUF,
SCON (00H, 01H, 02H),
Working Register Group 0
only implemented.
B(H)
Not Implemented
(Reserved)
A(H)
Not Implemented
(Reserved)
9(H)
Not Implemented
(Reserved)
8(H)
Not Implemented
(Reserved)
7(H)
Not Implemented
(Reserved)
6(H)
Not Implemented
(Reserved)
5(H)
Not Implemented
(Reserved)
4(H)
Not Implemented
(Reserved)
3(H)
Not Implemented
(Reserved)
2(H)
Not Implemented
(Reserved)
1(H)
Not Implemented
(Reserved)
0(H)
Z8 Ports 0, 1, 2, 3,
and General-Purpose Registers
04H to EFH, and control registers
F0H to FFH.
Z8 Microcontrollers
Address Space
ZiLOG
2-8
UM001601-0803
2.4 Z8 CONTROL AND PERIPHERAL REGISTERS
2.4.1 Standard Z8 Registers
The standard Z8 control registers govern the operation of the
CPU. Any instruction which references the register file can ac-
cess these control registers. Available control registers are:
Interrupt Priority Register (IPR)
Interrupt Mask Register (IMR)
Interrupt Request Register (IRQ)
Program Control Flags (FLAGS)
Register Pointer (RP)
Stack Pointer High-Byte (SPH)
Stack Pointer Low-Byte (SPL)
The Z8 uses a 16-bit Program Counter (PC) to determine the se-
quence of current program instructions. The PC is not an addres-
sable register.
Peripheral registers are used to transfer data, configure the oper-
ating mode, and control the operation of the on-chip peripherals.
Any instruction that references the register file can access the pe-
ripheral registers. The peripheral registers are:
Serial I/O (SIO)
Timer Mode (TMR)
Timer/Counter 0 (T0)
T0 Prescaler (PRE0)
Timer/Counter 1 (T1)
T1 Prescaler (PRE1)
Port 01 Mode (P01M)
Port 2 Mode (P2M)
Port 3 Mode (P3M)
In addition, the four port registers (P0P3) are considered to be
peripheral registers.
2.4.2 Expanded Z8 Registers
The expanded Z8 control registers govern the operation of addi-
tional features or peripherals. Any instruction which references
the register file can access these registers.
The ERF contains the control registers for WDT, Port Control,
Serial Peripheral Interface (SPI), and the SMR functions. Figure
2-4 shows the layout of the Register Banks in the ERF. Register
Bank C in the ERF consists of the registers for the SPI. Table 2-
5 shows the registers within ERF Bank C, Working Register
Group 0.
Table 2-5. Expanded Register File Register Bank C,
WR Group 0
Register
Working
Register
Function
Register
F
Reserved
R15
E
Reserved
R14
D
Reserved
R13
C
Reserved
R12
B
Reserved
R11
A
Reserved
R10
9
Reserved
R9
8
Reserved
R8
7
Reserved
R7
6
Reserved
R6
5
Reserved
R5
4
Reserved
R4
3
Reserved
R3
2
SPI Control (SCON)
R2
1
SPI Tx/Rx Data (Roxburgh)
R1
0
SPI Compare (SCOMP)
R0
Z8 Microcontrollers
ZiLOG
Address Space
UM001601-0803
2-9
Working Register Group 0 in ERF Bank 0 consists of the regis-
ters for Z8 General-Purpose Registers and ports. Table 2-6
shows the registers within this group.
Working Register Group 0 in ERF Bank F consists of the control
registers for STOP mode, WDT, and port control. Table 2-7
shows the registers within this group.
The functions and applications of the control and peripheral reg-
isters are described in subsequent sections of this manual.
Table 2-6. Expanded Register File Bank 0,
WR Group 0
Register
Working
Register
Function
Register
F
General-Purpose Register
R15
E
General-Purpose Register
R14
D
General-Purpose Register
R13
C
General-Purpose Register
R12
B
General-Purpose Register
R11
A
General-Purpose Register
R10
9
General-Purpose Register
R9
8
General-Purpose Register
R8
7
General-Purpose Register
R7
6
General-Purpose Register
R6
5
General-Purpose Register
R5
4
General-Purpose Register
R4
3
Port 3
R3
2
Port 2
R2
1
Port 1
R1
0
Port 0
R0
Table 2-7. Expanded Register File Bank F,
WR Group 0
Register
Working
Register
Function
Register
F
WDTMR
R15
E
Reserved
R14
D
Reserved
R13
C
Reserved
R12
B
SMR
R11
A
Reserved
R10
9
Reserved
R9
8
Reserved
R8
7
Reserved
R7
6
Reserved
R6
5
Reserved
R5
4
Reserved
R4
3
Reserved
R3
2
Reserved
R2
1
Reserved
R1
0
PCON
R0
Z8 Microcontrollers
Address Space
ZiLOG
2-10
UM001601-0803
2.5 PROGRAM MEMORY
The first 12 bytes of Program Memory are reserved for the inter-
rupt vectors (Figure 2-7). These locations contain six 16-bit vec-
tors that correspond to the six available interrupts. Address 12 up
to the maximum ROM address consists of on-chip mask-pro-
grammable ROM. See the product data sheet for the exact pro-
gram, data, register memory size, and address range available.
At addresses outside the internal ROM, the Z8 executes external
program memory fetches through Port 0 and Port 1 in Ad-
dress/Data mode for devices with Port 0 and Port 1 featured.
Otherwise, the program counter will continue to execute NOPs
up to address FFFFH, roll over to 0000H, and continue to fetch
executable code (Figure 2-7).
The internal program memory is one-time programmable (OTP)
or mask programmable dependent on the specific device. A
ROM protect feature prevents dumping of the ROM contents by
inhibiting execution of the LDC, LDCI, LDE, and LDEI
instructions to Program Memory in all modes. ROM look-up
tables cannot be used with this feature.
The ROM Protect option is mask-programmable, to be selected
by the customer when the ROM code is submitted. For the OTP
ROM, the ROM Protect option is an OTP programming option.
Figure 2-7. Z8 Program Memory Map
Interrupt
External
On - Chip
65535
ROM and RAM
ROM
IRQ
5
4096
Interrupt
Location of
IRQ
0
IRQ
0
IRQ
1
IRQ
1
IRQ
2
IRQ
2
IRQ
3
IRQ
3
IRQ
4
IRQ
4
IRQ
5
4095
12
1
2
3
4
5
6
7
8
9
10
11
0
First Byte of
Instruction
Executed
After RESET
Vector
(Lower Byte)
Vector
(Upper Byte)
Z8 Microcontrollers
ZiLOG
Address Space
UM001601-0803
2-11
2.6 Z8 EXTERNAL MEMORY
The Z8, in some cases, has the capability to access external pro-
gram memory with the 16-bit Program Counter. To access exter-
nal program memory the Z8 offers multiplexed address/data
lines (AD7-AD0) on Port 1 and address lines (A15-A8) on Port
0. This feature only applies to devices that offer Port 0 and Port
1. The maximum external address is FFFF. This memory inter-
face is supported by the control lines AS (Address Strobe), DS
(Data Strobe), and R/W (Read/Write). The origin of the external
program memory starts after the last address of the internal
ROM. Figure 2-8 shows an example of external program mem-
ory for the Z8.
2.6.1 External Data Memory (/DM)
The Z8, in some cases, can address up to 60 Kbytes of external
data memory beginning at location 4096. External Data Memory
may be included with, or separated from, the external Program
Memory space. DM, an optional I/O function that can be pro-
grammed to appear on pin P34, is used to distinguish between
data and program memory space. The state of the DM signal is
controlled by the type of instruction being executed. An LDC
opcode references Program (DM inactive) Memory, and an LDE
instruction references Data (DM active Low) Memory. The user
must configure Port 3 Mode Register (P3M) bits D3 and D4 for
this mode.
Note: For additional information on using external memory, see Chapter 10 of this manual. For exact memory addressing options available, see the
device product specification.
Figure 2-8. External Memory Map
External
65535
Memory
4096
Not Addressable
4095
0
Z8 Microcontrollers
Address Space
ZiLOG
2-12
UM001601-0803
2.7 Z8 STACKS
Stack operations can occur in either the Z8 MCU Standard Reg-
ister File or external data memory. Under software control, Port
01 Mode register (F8H) selects the stack location. Only the
General-Purpose Registers can be used for the stack when the in-
ternal stack is selected.
The register pair FEH and FFH form the 16-bit Stack Pointer
(SP), that is used for all stack operations. The stack address is
stored with the MSB in FEH and LSB in FFH (Figure 2-9).
The stack address is decremented prior to a PUSH operation and
incremented after a POP operation. The stack address always
points to the data stored on the top of the stack. The Z8 stack is
a return stack for CALL instructions and interrupts, as well as a
data stack.
During a CALL instruction, the contents of the PC are saved on
the stack. The PC is restored during a RETURN instruction. In-
terrupts cause the contents of the PC and Flag registers to be
saved on the stack. The IRET instruction restores them (Figure
2-10).
When the Z8 is configured for an internal stack (using the Z8
Standard Register File), register FFH serves as the Stack Pointer.
The value in FEH is ignored. FEH can be used as a general-pur-
pose register in this case only.
An overflow or underflow can occur when the stack address is
incremented or decremented during normal stack operations.
The programmer must prevent this occurrence or unpredictable
operation will result.
Figure 2-9. Stack Pointer
UPPER Byte
LOWER Byte
Stack Pointer High
FFH
Stack Pointer Low
FEH
Figure 2-10. Stack Operations
PCL
Top of Stack
Stack Contents
PCH
PCL
PCH
FLAGS
After an
Interrupt Cycle
Stack Contents
After a Call
Instruction
Top of Stack
UM001601-0803
3-1
U
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S
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ANUAL
C
HAPTER
3
C
LOCK
3.1 CLOCK
The Z8 MCU
derives its timing from on-board clock circuitry
connected to pins XTAL1 and XTAL2. The clock circuitry con-
sists of an oscillator, a divide-by-two shaping circuit, and a clock
buffer. Figure 3-1 illustrates the clock circuitry. The oscillator's
input is XTAL1 and its output is XTAL2. The clock can be driv-
en by a crystal, a ceramic resonator, LC clock, RC, or an external
clock source.
3.1.1 Frequency Control
In some cases, the Z8 has an EPROM/OTP option or a Mask
ROM option bit to bypass the divide-by-two flip flop in Figure
3-1. This feature is used in conjunction with the low EMI option.
When low EMI is selected, the device output drive and oscillator
drive is reduced to approximately 25 percent of the standard
drive and the divide-by-two flip flop is bypassed such that the
XTAL clock frequency is equal to the internal system clock fre-
quency. In this mode, the maximum frequency of the XTAL
clock is 4 MHz. Please refer to specific product specification for
availability of options and output drive characteristics.
3.2 CLOCK CONTROL
In some cases, the Z8 offers software control of the internal sys-
tem clock via programming register bits. The bits are located in
the Stop-Mode Recovery Register in Expanded Register File
Bank F, Register 0BH. This register selects the clock divide val-
ue and determines the mode of Stop-Mode Recovery (Figure 3-
2). Please refer to the specific product specification for availabil-
ity of this feature/register.
3.2.1 SCLK/TCLK Divide-By-16 Select (D0)
This bit of the SMR controls a divide-by-16 prescalar of
SCLK/TCLK. The purpose of this control is to selectively reduce
device power consumption during normal processor execution
Figure 3-1. Z8 Clock Circuit
2
OSC
XTAL2
Internal
Buffer
XTAL1
Clock
Figure 3-2. Stop-Mode Recovery Register
(Write-Only Except D7, Which is Read-Only)
D7 D6 D5 D4 D3 D2 D1 D0
SMR (F) OB
SCLK/TCLK Divide by 16
0 OFF **
1 ON

External Clock Divide Mode by 2
0 = SCLK/TCLK = XTAL/2*
1 = SCLK/TCLK = XTAL
* Default setting after RESET.
**Default setting after RESET and STOP-Mode Recovery.
Z8 Microcontrollers
Clock
ZiLOG
3-2
UM001601-0803
(SCLK control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
3.2.2 External Clock Divide-By-Two (D1)
This bit can eliminate the oscillator divide-by-two circuitry.
When this bit is 0, SCLK (System Clock) and TCLK (Timer
Clock) are equal to the external clock frequency divided by two.
The SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1 = 1). Using this bit, together with D7 of PCON,
further helps lower EMI (D7 (PCON) = 0, D1 (SMR) = 1). The
default setting is 0. Maximum frequency is 4 MHz with D1=1
(Figure 3-3).
3.3 OSCILLATOR CONTROL
In some cases, the Z8 MCU offers software control of the oscil-
lator to select low EMI drive or standard drive. The selection is
done by programming bit D7 of the Port Configuration (PCON)
register (Figure 3-4). The PCON register is located in Expanded
Register File Bank F, Register 00H.
A 1 in bit D7 configures the oscillator with standard drive, while
a 0 configures the oscillator with Low EMI drive. This only af-
fects the drive capability of the oscillator and does not affect the
relationship of the XTAL clock frequency to the internal system
clock (SCLK).
Figure 3-3. External Clock Circuit
2
OSC
External Clock
D1 (SMR)
16
D0 (SMR)
Figure 3-4. Port Configuration Register (PCON)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
PCON (FH) 00H
Low EMI Oscillator
0 Low EMI
1 Standard
Z8 Microcontrollers
ZiLOG
Clock
UM001601-0803
3-3
3.4 OSCILLATOR OPERATION
The Z8
MCU uses a Pierce oscillator with an internal feedback
(Figure 3-5). The advantages of this circuit are low cost, large
output signal, low-power level in the crystal, stability with re-
spect to V
CC
and temperature, and low impedances (not dis-
turbed by stray effects).
One draw back is the need for high gain in the amplifier to com-
pensate for feedback path losses. The oscillator amplifies its own
noise at start-up until it settles at the frequency that satisfies the
gain/phase requirements A x B = 1, where A = V
0
/V
I
is the gain
of the amplifier and B = V
I
/V
0
is the gain of the feedback ele-
ment. The total phase shift around the loop is forced to zero (360
degrees). Since VIN must be in phase with itself, the amplifi-
er/inverter provides 180 degree phase shift and the feedback el-
ement is forced to provide the other 180 degrees of phase shift.
R1 is a resistive component placed from output to input of the
amplifier. The purpose of this feedback is to bias the amplifier in
its linear region and to provide the start-up transition.
Capacitor C
2
combined with the amplifier output resistance pro-
vides a small phase shift. It will also provide some attenuation of
overtones.
Capacitor C
1
combined with the crystal resistance provides ad-
ditional phase shift.
C
1
and C
2
can affect the start-up time if they increase dramati-
cally in size. As C
1
and C
2
increase, the start-up time increases
until the oscillator reaches a point where it does not start up any
more.
It is recommended for fast and reliable oscillator start-up (over
the manufacturing process range) that the load capacitors be
sized as low as possible without resulting in overtone operation.
3.4.1 Layout
Traces connecting crystal, caps, and the Z8 oscillator pins
should be as short and wide as possible. This reduces parasitic
inductance and resistance. The components (caps, crystal, resis-
tors) should be placed as close as possible to the oscillator pins
of the Z8.
The traces from the oscillator pins of the IC and the ground side
of the lead caps should be guarded from all other traces (clock,
V
CC
, address/data lines, system ground) to reduce cross talk and
noise injection. This is usually accomplished by keeping other
traces and system ground trace planes away from the oscillator
circuit and by placing a Z8 device V
SS
ground ring around the
traces/components. The ground side of the oscillator lead caps
should be connected to a single trace to the Z8 V
SS
(GND) pin.
It should not be shared with any other system ground trace or
components except at the Z8 device V
SS
pin. This is to prevent
differential system ground noise injection into the oscillator
(Figure 3-6).
3.4.2 Indications of an Unreliable Design
There are two major indicators that are used in working designs
to determine their reliability over full lot and temperature varia-
tions. They are:
Start-up Time. If start -up time is excessive, or varies widely
from unit to unit, there is probably a gain problem. C1/C2 needs
to be reduced; the amplifier gain is not adequate at frequency, or
crystal Rs is too large.
Output Level. The signal at the amplifier output should swing
from ground to V
CC
. This indicates there is adequate gain in the
amplifier. As the oscillator starts up, the signal amplitude grows
until clipping occurs, at which point the loop gain is effectively
reduced to unity and constant oscillation is achieved. A signal of
less than 2.5 volts peak-to-peak is an indication that low gain
may be a problem. Either C
1
or C
2
should be made smaller or a
low-resistance crystal should be used.
Figure 3-5. Pierce Oscillator with Internal Feedback
Circuit
XTAL2
Z8
V
SS
XTAL1
C1
C2
R
I
V
1
A
V
0
Z8 Microcontrollers
Clock
ZiLOG
3-4
UM001601-0803
3.4.3 Circuit Board Design Rules
The following circuit board design rules are suggested:
To prevent induced noise the crystal and load capacitors
should be physically located as close to the Z8 as possible.
Signal lines should not run parallel to the clock oscillator
inputs. In particular, the crystal input circuitry and the internal
system clock output should be separated as much as possible.
V
CC
power lines should be separated from the clock oscillator
input circuitry.
Resistivity between XTAL1 or XTAL2 and the other pins
should be greater than 10 Mohms.
Figure 3-6. Circuit Board Design Rules
XTAL2
V
SS
XTAL1
Board Design Example
V
SS
2
3
1
Layout Should
Avoid High
Lighted Areas
Signal Line
20 mm
max
Z8
Z8
Z8
C1
C2
3
2
Clock Generator Circuit
Signals A B
Signal C
(Connection to System Group
Must Be Avoided)
(Parallel Traces
Must Be Avoided)
(Top View)
Z8 Microcontrollers
ZiLOG
Clock
UM001601-0803
3-5
3.4.4 Crystals and Resonators
Crystals and ceramic resonators (Figure 3-7) should have the
following characteristics to ensure proper oscillator operation:
Depending on operation frequency, the oscillator may require
the addition of capacitors C1 and C2 (shown in Figures 3-7). The
capacitance values are dependent on the manufacturer's crystal
specifications.
In most cases, the R
D
is 0 Ohms and R
F
is infinite. It is deter-
mined and specified by the crystal/ceramic resonator manufac-
turer. The R
D
can be increased to decrease the amount of drive
from the oscillator output to the crystal. It can also be used as an
adjustment to avoid clipping of the oscillator signal to reduce
noise. The R
F
can be used to improve the start-up of the crys-
tal/ceramic resonator. The Z8 oscillator already has an internal
shunt resistor in parallel to the crystal/ceramic resonator.
It is recommended in Figures 3-7, 3-8, and 3-9 to connect the
load capacitor ground trace directly to the V
SS
(GND) pin of the
Z8
. This ensures that no system noise is injected into the Z8
clock. This trace should not be shared with any other compo-
nents except at the V
SS
pin of the Z8.
In some cases, the Z8 XTAL1 pin also functions as one of the
EPROM high-voltage mode programming pins or as a special
factory test pin. In this case, applying 2 V above V
CC
on the
XTAL1 pin will cause the device to enter one of these modes.
Since this pin accepts high voltages to enter these respective
modes, the standard input protection diode to V
CC
is not on
XTAL1. It is recommended that in applications where the Z8 is
exposed to much system noise, a diode from XTAL1 to V
CC
be
used to prevent accidental enabling of these modes. This diode
will not affect the crystal/ceramic resonator operation.
Please note that a parallel resonant crystal or resonator data sheet
will specify a load capacitor value that is the series combination
of C
1
and C
2
, including all parasitics (PCB and holder).
Crystal Cut
AT (crystal only)
Mode
Parallel, Fundamental Mode
Crystal Capacitance
<7pF
Load Capacitance
10pF < CL < 220 pF,
15 typical
Resistance
100 ohms max
Figure 3-7. Crystal/Ceramic Resonator Oscillator
Figure 3-8. LC Clock
XTAL2
Z8
V
SS
XTAL1
C1
C2
R
F
R
D
XTAL2
Z8
V
SS
XTAL1
C1
C2
L
Figure 3-9. External Clock
XTAL2
Z8
V
SS
XTAL1
Z8 Microcontrollers
Clock
ZiLOG
3-6
UM001601-0803
3.5 LC OSCILLATOR
The Z8 oscillator can use a LC network to generate a XTAL
clock (Figure 3-8).
The frequency stays stable over V
CC
and temperature. The oscil-
lation frequency is determined by the equation:
where L is the total inductance including parasitics and C
T
is the
total series capacitance including the parasitics.
Simple series capacitance is calculated using the following equa-
tion:
Sample calculation of capacitance C
1
and C
2
for 5.83 MHz fre-
quency and inductance value of 27 uH:
3.6 RC OSCILLATOR
In some cases, the Z8 has a RC oscillator option. Please refer to
the specific product specification for availability. The RC oscil-
lator requires a resistor across XTAL1 and XTAL2. An addition-
al load capacitor is required from the XTAL1 input to V
SS
pin
(Figure 3-10).
1
Frequency =
2
(LCT)1/2
1
=
1 + 1
C
T
= C
1
C
2
If C
1
=
C
2
1
=
2
C
T
=
C
1
C
1
=
2CT
5.83 (10^6) =
1
2
[2.7 (10
-6
) CT] 1/2
CT = 27.6 pf
Thus C
1
= 55.2 pf and C
2
= 55.2 pf.
Figure 3-10. RC Clock
XTAL2
Z8
V
SS
XTAL1
C1
R
UM001601-0803
4-1
U
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ANUAL
C
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4
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--W
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-D
OG
T
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4.1 RESET
This section describes the Z8 MCU
reset conditions, reset tim-
ing, and register initialization procedures. Reset is generated by
Power-On Reset (POR), Reset Pin, Watch-Dog Timer (WDT),
and Stop-Mode Recovery.
A system reset overrides all other operating conditions and puts
the Z8 into a known state. To initialize the chip's internal logic,
the RESET input must be held Low for at least 21 SCP or 5
XTAL clock cycles. The control register and ports are reset to
their default conditions after a POR, a reset from the RESET pin,
or Watch-Dog Timer timeout while in RUN mode and HALT
mode. The control registers and ports are not reset to their default
conditions after Stop- Mode Recovery and WDT timeout while
in STOP mode.
While RESET pin is Low, AS is output at the internal clock rate,
DS is forced Low, and R//W remains High. The program counter
is loaded with 000CH. I/O ports and control registers are config-
ured to their default reset state.
Resetting the Z8 does not effect the contents of the general-
purpose registers.
4.2 RESET PIN, INTERNAL POR OPERATION
In some cases, the Z8 hardware RESET pin initializes the control
and peripheral registers, as shown in Tables 4-1, 4-2, 4-3, and 4-
4. Specific reset values are shown by 1 or 0, while bits whose
states are unknown are indicated by the letter U. The Tables 4-1,
4-2, 4-3, and 4-4 show the reset conditions for the generic Z8.
Note: The register file reset state is device dependent. Please
refer to the selected device product specifications for register
availability and reset state.
Z8 Microcontrollers
Reset--Watch-Dog Timer
ZiLOG
4-2
UM001601-0803
4.2 RESET PIN, INTERNAL POR OPERATION
(Continued)
Program execution starts 5 to 10 clock cycles after internal
RESET has returned High. The initial instruction fetch is from
location 000CH. Figure 4-1 shows reset timing.
After a reset, the first routine executed should be one that initial-
izes the control registers to the required system configuration.
The RESET pin is the input of a Schmitt-triggered circuit. Reset-
ting the Z8 will initialize port and control registers to their de-
Table 4-1. Sample Control and Peripheral Register Reset Values (ERF Bank 0)
Register
Register
Bits
(HEX)
Name
7
6
5
4
3
2
1
0 Comments
F0
Serial I/O
U
U
U
U
U
U U U
F1
Timer Mode
0
0
0
0
0
0
0
0 Counter/Timers Stopped
F2
Counter/Timer1
U
U
U
U
U
U U U
F3
T1 Prescaler
U
U
U
U
U
U
0
0 Single-Pass Count Mode, External Clock Source
F4
Counter/Timer0
U
U
U
U
U
U U U
F5
T0 Prescaler
U
U
U
U
U
U U
0 Single-Pass Count Mode
F6
Port 2 Mode
1
1
1
1
1
1
1
1 All Inputs
F7
Port 3 Mode
0
0
0
0
0
0
0
0 Port 2 Open-Drain, P33P30 Input, P37P34 Output
F8
Port 01 Mode
0
1
0
0
1
1
0
1 Internal Stack, Normal Memory Timing
F9
Interrupt Priority
U
U
U
U
U
U U U
FA
Interrupt Request
0
0
0
0
0
0
0
0 All Interrupts Cleared
FB
Interrupt Mask
0
U
U
U
U
U U U Interrupts Disabled
FC
Flags
U
U
U
U
U
U U U
FD
Register Pointer
0
0
0
0
0
0
0
0
FE
Stack Pointer (High)
U
U
U
U
U
U U U
FF
Stack Pointer (Low)
U
U
U
U
U
U U U
Figure 4-1. Reset Timing
First Machine Cycle
T1
Clock
RESET
AS
DS
R/W
First Instruction Fetch
Hold Low For 4 SCLK
Periods (Minimum)
SCLK
Z8 Microcontrollers
ZiLOG
Reset--Watch-Dog Timer
UM001601-0803
4-3
fault states. To form the internal reset line, the output of the trig-
ger is synchronized with the internal clock. The clock must
therefore be running for RESET to function. It requires 4 internal
system clocks after reset is detected for the Z8 to reset the inter-
nal circuitry. An internal pull-up, combined with an external ca-
pacitor of 1 uf, provides enough time to properly reset the Z8
(Figure 4-2). In some cases, the Z8 has an internal POR timer
circuit that holds the Z8 in reset mode for a duration (T
POR
) be-
fore releasing the device out of reset. On these Z8 devices, the
internally generated reset drives the reset pin low for the POR
time. Any devices driving the reset line must be open-drained in
order to avoid damage from possible conflict during reset condi-
tions. This reset time allows the on-board clock oscillator to sta-
bilize.
To avoid asynchronous and noisy reset problems, the Z8 is
equipped with a reset filter of four external clocks (4TpC). If the
external reset signal is less than 4TpC in duration, no reset oc-
curs. On the fifth clock after the reset is detected, an internal
RST signal is latched and held for an internal register count of
18 external clocks, or for the duration of the external reset,
whichever is longer. During the reset cycle, DS is held active
low while AS cycles at a rate of the internal system clock. Pro-
gram execution begins at location 000CH, 5-10 TpC cycles after
RESET is released. For the internal Power-On Reset, the reset
output time is specified as T
POR
. Please refer to specific product
specifications for actual values.
Figure 4-2. Example of External Power-On Reset Circuit
1
F
+5V
100 K
/RESET
1K
to
200 K
10 V
Table 4-2. Expanded Register File Bank 0 Reset Values at RESET
Register
Register
Bits
(HEX)
Name
7
6
5
4
3
2
1
0
Comments
00
Port 0
U U U U U U U U
Input mode, output set to push-pull
01
Port 1
U U U U U U U U
Input mode, output set to push-pull
02
Port 2
U U U U U U U U
Input mode, output set to open drain
03
Port 3
1
1
1
1 U U U U
Standard Digital input and output
Z86L7X Family Device Port P34-P37 = 0
(Except Z86L70/71/75)
All other Z8 = 1
04EF
General-
Purpose
Registers
04-EF
U U U U U U U U
Undefined
Z8 Microcontrollers
Reset--Watch-Dog Timer
ZiLOG
4-4
UM001601-0803
4.2 RESET PIN, INTERNAL POR OPERATION
(Continued)
Table 4-3. Sample Expanded Register File Bank C Reset Values
Register
Register
Bits
(HEX)
Name
7
6
5
4
3
2
1
0 Comments
00
SPI Compare
0
0
0
0
0
0
0
0
(SCOMP)
01
Receive Buffer
U U U U U U U U
(RxBUF)
02
SPI Control
U U U U 0
0
0
0
(SCON)
Table 4-4. Sample Expanded Register File Bank F Reset Values
Register
Register
Bits
(HEX)
Name
7
6
5
4
3
2
1
0 Comments
00
Port Configuration
1
1
1
1
1
1
1
0 Comparator outputs disabled on Port 3
(PCON)
Port 0 and 1 output is push-pull
Port 0, 1, 2, 3, and oscillator with standard output
drive
0B
STOP-Mode Recovery
0
0
1
0
0
0
0
0 Clock divide by 16 off
(SMR)
XTAL divide by 2
POR and / OR External Reset
Stop delay on
Stop recovery level is low, STOP flag is POR
0F
Watch-Dog Timer
Mode (WDTMR)
U U U 0
1
1
0
1 512 TPC for WDT time out, WDT runs during
STOP
Z8 Microcontrollers
ZiLOG
Reset--Watch-Dog Timer
UM001601-0803
4-5
Figure 4-3. Example of Z8 Reset with RESET Pin, WDT, SMR, and POR
256 TpC 256 512 1024 4096
WDT/POR Counter Chain
POR TpC TpC TpC TpC
+
-
M
WDT TAP SELECT
Clear 18 Clock RESET RESET
CLK Generator
4 Clock
Filter
CK CLR
RC
OSC.
U
X
Internal
RESET
2.6V Operating
Voltage Det.
/RESET
From Stop Mode
Recovery Source
Stop Delay
Select (SMR)
/WDT
.
VDD
XTAL
WDT Select
(WDTMR)
CLK Source
Select (WDTMR)
2.6V REF
Z8 Microcontrollers
Reset--Watch-Dog Timer
ZiLOG
4-6
UM001601-0803
4.2 RESET PIN, INTERNAL POR OPERATION
(Continued)
Figure 4-4. Example of Z8 Reset with WDT, SMR, and POR
5ms POR 5ms 15ms 25ms 100ms
WDT/POR Counter Chain
CLK
+
-
M
WDT TAP SELECT
4 Clock
Filter
CLR
Internal
RC OSC.
U
X
2V Operating
Voltage Det.
From Stop Mode
Recovery Source
Stop Delay
Select (SMR)
WDT
.
V
DD
XTAL
WDT Select
(WDTMR)
CLK Source
Select (WDTMR)
V
LV
Internal
RESET
CLEAR
CLK
18 Clock RESET
Generator
RESET
Z8 Microcontrollers
ZiLOG
Reset--Watch-Dog Timer
UM001601-0803
4-7
4.3 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. When operating in the RUN or HALT
modes, a WDT reset is functionally equivalent to a hardware
POR reset. The WDT is initially enabled by executing the WDT
instruction and refreshed on subsequent executions of the WDT
instruction. The WDT cannot be disabled after it has been initial-
ly enabled. Permanently enabled WDTs are always enabled and
the WDT instruction is used to refresh it. The WDT circuit is
driven by an on-board RC oscillator or external oscillator from
the XTAL1 pin. The POR clock source is selected with bit 4 of
the Watch-Dog Timer Mode register (WDTMR). In some cases,
a Z8 that offers the WDT but does not have a WDTMR register,
has a fixed WDT timeout and uses the on board RC oscillator as
the only clock source. Please refer to specific product specifica-
tions for selectability of timeout, WDT during HALT and STOP
modes, source of WDT clock, and availability of the permanent-
ly-on WDT option.
Note: Execution of the WDT instruction affects the Z (zero), S
(sign), and V (overflow) flags.
Note: The WDTMR register is accessible only during the first
60 processor cycles from the execution of the first instruction
after Power-On Reset, Watch-Dog Reset or a Stop-Mode
Recovery. After this point, the register cannot be modified by
any means, intentional or otherwise. The WDTMR is a write-
only register.
The WDTMR is located in Expanded Register File Bank F, reg-
ister 0FH. The control bits are described as follows:
WDT Time Select (D1, D0). Bits 0 and 1 control a tap circuit
that determines the time-out period. Table 4-5 shows the differ-
ent values that can be obtained. The default value of D1 and D0
are 0 and 1, respectively.
WDT During HALT (D2). This bit determines whether or not
the WDT is active during HALT mode. A 1 indicates active dur-
ing HALT. The default is 1. A WDT time out during HALT
mode will reset control register ports to their default reset condi-
tions.
WDT During STOP (D3). This bit determines whether or not
the WDT is active during STOP mode. Since XTAL clock is
stopped during STOP Mode, unless as specified below, the on-
board RC must be selected as the clock source to the POR
counter. A 1 indicates active during STOP. The default is 1. If
bits D3 and D4 are both set to 1, the WDT only, is driven by the
external clock during STOP mode. This feature makes it possi-
ble to wake up from STOP mode from an internal source. Please
refer to specific product specifications for conditions of control
and port registers when the Z8 comes out of STOP mode. A
WDT time out during STOP mode will not reset all control reg-
isters. The reset conditions of the ports from STOP mode due to
WDT time out is the same as if recovered using any of the other
STOP mode sources.
Figure 4-5. Example of Z8 Watch-Dog Timer Mode
Register (Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDTMR (F) 0F
INT
00 5 128
01** 10 256
10 20 512
11 80 2048
WDT RC SYS
TAP* OSC CLK
WDT During STOP
0 OFF
1 ON *
WDT During HALT
0 OFF
1 ON *
XTAL1/INT RC
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
Select for WDT
* Must be 0 for Z86C03
Reserved (Must be 0)
** Default setting after RESET
Table 4-5. Time-Out Period of the WDT
Typical
Time-Out of
Time-Out of
D1
D0
Internal RC OSC
SYS Clock
0
0
5 ms min
256TpC
0
1
15 ms min
512TpC
1
0
25 ms min
1024TpC
1
1
100 ms min
4096TpC
Notes:
TpC = XTAL clock cycle
The default on reset is, D0 = 1 and D1 = 0.
The values given are for VCC = 5.0V.
See the device product specification for exact WDTMR time
out select options available.
Z8 Microcontrollers
Reset--Watch-Dog Timer
ZiLOG
4-8
UM001601-0803
Clock Source for WDT (D4). This bit determines which oscil-
lator source is used to clock the internal POR and WDT counter
chain. If the bit is a 1, the internal RC oscillator is bypassed and
the POR and WDT clock source is driven from the external pin,
XTAL1. The default configuration of this bit is 0, which selects
the internal RC oscillator.
Bits 5, 6 and 7. These bits are reserved.
V
CC
Voltage Comparator. An on-board voltage comparator
checks that V
CC
is at the required level to insure correct opera-
tion of the device. Reset is globally driven if V
CC
is below the
specified voltage. This feature is available in select ROM Z8 de-
vices. See the device product specification for feature availabil-
ity and operating range.
4.4 POWER-ON-RESET (POR)
A timer circuit clocked by a dedicated on-board RC oscillator is
used for the Power-On Reset (POR) timer (T
POR
) function. The
POR time allows V
CC
and the oscillator circuit to stabilize before
instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of
three conditions:
1. Power fail to Power OK status (cold start).
2. STOP-Mode Recovery (if bit 5 of SMR=1).
3. WDT timeout.
The POR time is specified as TPOR. On Z8 devices that feature
a Stop-Mode Recovery register (SMR), bit 5 selects whether the
POR timer is used after Stop-Mode Recovery or by-passed. If bit
D5 = 1 then the POR timer is used. If bit 5 = 0 then the POR timer
is by-passed. In this case, the Stop-Mode Recovery source must
be held in the recovery state for 5 T
P
C or 5 crystal clocks to pass
the reset signal internally. This option is used when the clock is
provided with an RC/LC clock. See the device product specifi-
cation for timing details.
POR (cold start) will always reset the Z8 control and port regis-
ters to their default condition. If a Z8 has a SMR register, the
warm start bit will be reset to a 0 to indicate POR.
Figure 4-6. Example of Z8 with Simple SMR and POR
INT OSC
Chip
POR
Reset
P27
(Stop Mode)
(Cold Start)
VBO
WDT
Delay Line
T
POR
ms
18 CLK
Reset Filter
XTAL OSC
UM001601-0803
5-1
U
SER
'
S
M
ANUAL
C
HAPTER
5
I/O P
ORTS
5.1 I/O PORTS
The Z8 has up to 32 lines dedicated to input and output. These
lines are grouped into four 8-bit ports known as Port 0, Port 1,
Port 2, and Port 3. Port 0 is nibble programmable as input, out-
put, or address. Port 1 is byte configurable as input, output, or ad-
dress/data. Port 2 is bit programmable as either inputs or outputs,
with or without handshake and SPI. Port 3 can be programmed
to provide timing, serial and parallel input/output, or comparator
input/output.
All ports have push-pull CMOS outputs. In addition, the push-
pull outputs of Port 2 can be turned off for open-drain operation.
5.1.1 Mode Registers
Each port has an associated Mode Register that determines the
port's functions and allows dynamic change in port functions
during program execution. Port and Mode Registers are mapped
into the Standard Register File as shown in Figure 5-1.
Because of their close association, Port and Mode Registers are
treated like any other general-purpose register. There are no spe-
cial instructions for port manipulation. Any instruction which
addresses a register can address the ports. Data can be directly
accessed in the Port Register, with no extra moves.
5.1.2 Input and Output Registers
Each bit of Ports 0, 1, and 2, have an input register, an output reg-
ister, associated buffer, and control logic. Since there are sepa-
rate input and output registers associated with each port, writing
to bits defined as inputs stores the data in the output register. This
data cannot be read as long as the bits are defined as inputs. How-
ever, if the bits are reconfigured as outputs, the data stored in the
output register is reflected on the output pins and can then be
read. This mechanism allows the user to initialize the outputs pri-
or to driving their loads (Figure 5-2).
Since port inputs are asynchronous to the Z8 internal clock, a
READ operation could occur during an input transition. In this
case, the logic level might be uncertain (somewhere between a
logic 1 and 0). To eliminate this meta-stable condition, the Z8
latches the input data two clock periods prior to the execution of
the current instruction. The input register uses these two clock
periods to stabilize to a legitimate logic level before the instruc-
tion reads the data.
Note: The following sections describe the generic function of
the Z8 ports. Any additional features of the ports such as SPI,
C/T, and Stop-Mode Recovery are covered in their own section.
Figure 5-1. I/O Ports and Mode Registers
Register
HEX
Port 3 Mode
Port 2 Mode
Identifier
F8H
F7H
F6H
P01M
P3M
P2M
Port 3
Port 0-1 Mode
Port 2
Port 1
Port 0
03H
02H
01H
00H
P3
P2
P1
P0
Z8 Microcontrollers
I/O Ports
ZiLOG
5-2
UM001601-0803
5.2 PORT 0
This section deals with only the I/O operation of Port 0. The
port's external memory interface operation is covered later in
this manual. Figure 5-2 shows a block diagram of Port 0. This di-
agram also applies to Ports 1 and 2.
Figure 5-2. Ports 0, 1, 2 Generic Block Diagram
Handshake
Logic
Internal
Timing
Handshake
Selected
RDY//DAV
/DAV/RDY
Port I/O
Lines
Input
Buffer
Input
Register
Handshake
Logic
Output
Buffer
Output
Register
Output
Enable
Internal
Bus
Write
Port
Read
Port
E
8
8
8
8
8
8
8
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-3
5.2.1 General I/O Mode
Port 0 can be an 8-bit, bidirectional, CMOS or TTL compatible
I/O port. These eight I/O lines can be configured under software
control as a nibble I/O port (P03-P00 input/output and P07-P04
input/output), or as an address port for interfacing external mem-
ory. The input buffers can be Schmitt-triggered, level shifted, or
a single-trip point buffer and can be nibble programmed. Either
nibble output can be globally programmed as push-pull or open-
drain. Low EMI output buffers in some cases can be globally
programmed by the software, as an OTP program option, or as a
ROM mask option. In some, the Z8 has Auto Latches hardwired
to the inputs. Please refer to specific product specifications for
exact input/output buffer type features that are available (Figures
5-3 and 5-4).
Figure 5-3. Port 0 Configuration with Open-Drain Capability, Auto Latch, and Schmitt-Trigger
OEN
Port 1
(I/O or AD15 - AD08)
Handshake Controls
/DAV0 and RDY0
4
Z8
(P32 and P35)
PIN
OUT
IN
2.3V Hysteresis
OPEN-DRAIN
1.5
R
500 K
Auto Latch
4
Z8 Microcontrollers
I/O Ports
ZiLOG
5-4
UM001601-0803
5.2 PORT 0
(Continued)
5.2.2 Read/Write Operations
In the nibble I/0 Mode, Port 0 is accessed as general-purpose
register P0 (00H) with ERF Bank set to 0. The port is written by
specifying P0 as an instruction's destination register. Writing to
the port causes data to be stored in the port's output register.
The port is read by specifying P0 as the source register of an in-
struction. When an output nibble is read, data on the external
pins is returned. Under normal loading conditions this is equiv-
alent to reading the output register. However, for Port 0 outputs
defined as opendrain, the data returned is the value forced on
the output by the external system. This may not be the same as
the data in the output register. Reading a nibble defined as input
also returns data on the external pins. However, input bits under
handshake control return data latched into the input register via
the input strobe.
The Port 01 Mode resister bits D
1
D
0
and D
7
D
6
are used to con-
figure Port 0 nibbles. The lower nibble (P0
0
P0
3
) can be defined
as inputs by setting bits D
1
to 0 and D
0
to 1, or as outputs by set-
ting both D
1
and D
0
to 0. Likewise, the upper nibble (P0
4
P0
7
)
can be defined as inputs by setting bits D
7
to 0 and D
6
to 1, or as
outputs by setting both D
6
and D
7
to 0 (Figure 5-5).
5.2.3 Handshake Operation
When used as an I/0 port, Port 0 can be placed under handshake
control by programming the Port 3 Mode register bit D
2
to 1. In
this configuration, handshake control lines are DAV
0
(P3
2
) and
RDY
0
(P3
5
) when Port 0 is an input port, or RDY
0
(P3
2
) and
DAV
0
(P3
5
) when Port 0 is an output port. (See Figure 5-6)
Handshake direction is determined by the configuration (input or
output) assigned to the Port 0 upper nibble, P0
4
P0
7
. The lower
nibble must have the same I/0 configuration as the upper nibble
to be under handshake control. Figure 5-3 illustrates the Port 0
upper and lower nibbles and the associated handshake lines of
Port 3.
Figure 5-4. Port 0 Configuration with TTL Level Shifter
OEN
PIN
OUT
IN
TTL Level Shifter
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-5
5.3 PORT 1
This section deals only with the I/0 operation. The port's external
memory interface operation is discussed later in this manual.
Figure 5-2 shows a block diagram of Port 1.
5.3.1 General I/O Mode
Port 1 can be an 8-bit, bidirectional, CMOS or TTL compatible
port with multiplexed Address (A7A0) and Data (D7D0)
ports. These eight I/O lines can be byte programmed as inputs or
outputs or can be configured under software control as an Ad-
dress/Data port for interfacing to external memory. The input
buffers can be Schmitt-triggered, level- shifted, or a single-point
buffer. In some cases, the output buffers can be globally pro-
grammed as either push-pull or open-drain. Low-EMI output
buffers can be globally programmed by software, as an OTP pro-
gram option, or as a ROM Mask Option. In some cases, the
Z8can have auto latches hardwired to the inputs. Please refer to
specific product specifications for exact input/output buffer-type
features available (Figures 5-7 and 5-8).
Figure 5-5. Port 0 I/O Operation
Figure 5-6. Port 0 Handshake Operation
D7 D6 D1 D0
(Write-Only)
01 = Input
1X = A
8
- A
11
P0
0
- P0
3
Mode
00 = Output

Port 0-1 Mode Register (P01M)
Register F8H (P01M)
P0
4
- P0
7
Mode
00 = Output
01 = Input
1X = A
12
- A
15
D2
(Write-Only)
0 P3
2
= Input
P3
5
= Output
Port 3 Mode Register (P3M)
Register F7H
1 P3
2
= DAV0/RDY0
P3
5
= RDY0/DAV0
Z8 Microcontrollers
I/O Ports
ZiLOG
5-6
UM001601-0803
5.3 PORT 1
(Continued)
Figure 5-7. Port 1 Configuration with Open-Drain Capability, Auto Latch, and Schmitt-Trigger
OEN
Port 1
(I/O or AD7 - AD0)
Handshake Controls
/DAV1 and RDY1
8
Z8
(P33 and P34)
PIN
OUT
IN
2.3V Hysteresis
OPEN-DRAIN
1.5
R
500 K
Auto Latch
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-7
Figure 5-8. Port 1 Configuration with TTL Level Shifter
OEN
Port 1
(I/O or AD7 - AD0)
8
Z8
(P33 and P34)
PIN
OUT
IN
TTL Level Shifter
Handshake Controls
DAV1
and RDY1
Z8 Microcontrollers
I/O Ports
ZiLOG
5-8
UM001601-0803
5.3.2 Read/Write Operations
In byte input or byte output mode, the port is accessed as Gener-
al-Purpose Register P1 (01H). The port is written by specifying
P1 as an instruction's destination register. Writing to the port
causes data to be stored in the port's output register.
The port is read by specifying P1 as the source register of an in-
struction. When an output is read, data on the external pins is re-
turned. Under normal loading conditions, this is equivalent to
reading the output register. However, if Port 1 outputs are de-
fined as open-drain, the data returned is the value forced on the
output by the external system. This may not be the same as the
data in the output register. When Port 1 is defined as an input,
reading also returns data on the external pins. However, inputs
under handshake control return data latched into the input regis-
ter via the input strobe.
Using the Port 0-1 Mode Register, Port 1 is configured as an out-
put port by setting bits D
4
and D
3
to 0, or as an input port by set-
ting D
4
to 0 and D
3
to 1 (Figure 5-8).
5.3.3 Handshake Operations
When used as an I/O port, Port 1 can be placed under handshake
control by programming the Port 3 Mode register bits D
4
and D
3
both to 1. In this configuration, handshake control lines are
DAV
1
(P3
3
) and RDY1 (P3
4
) when Port 1 is an input port, or
RDY1 (P3
3
) and DAV1 (P3
4
) when Port 1 is an output port. See
Figures 5-8 and 5-10.
Handshake direction is determined by the configuration (input
and output) assigned to Port 1. For example, if Port 1 is an output
port then handshake is defined as output.
Figure 5-9. Port 1 I/O Operation
D4 D3
(F8, Write-Only)
Port 0-1 Mode Register
R248 P01M
01 = Byte Output
10 = AD
0
-AD
7
00 = Byte Output
P1
0
- P1
3
Mode

AS, DS, R/W,
11 = High Impedance AD
0
- AD
7
,
A
8
- A
11
, A
12
- A
15
Figure 5-10. Handshake Operation
D4 D3
(F7, Write-Only)
00 P33 = Input P34 = Output
01 P33 = Input P34 =
DM
Port 3 Mode Register
R247 P3M
10 P33 = Input P34 =
DM

11 P33 =
DAV1/
RDY1 P34 = RDY1/
DAV1
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-9
5.4 PORT 2
Port 2 is a general-purpose port. Figure 5-2 shows a block dia-
gram of Port 2. Each of its lines can be independently pro-
grammed as input or output via the Port 2 Mode Register (F6H)
as seen in Figure 5-11. A bit set to a 1 in P2M configures the cor-
responding bit in Port 2 as an input, while a bit set to 0 configures
an output line.
Figure 5-11. Port 2 I/O Mode Configuration
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
1 = Input
Port 2 Mode
0 = Output
Port 2 Mode Register (P2M)
Register F6H
Figure 5-12. Port 2 Configuration with Open-Drain Capability, Auto Latch, and Schmitt-Trigger
P21-P26 OE
PIN
P21-P26 OUT
P21-P26 IN
2.3V Hysteresis @ V
CC
= 5.0V
OPEN-DRAIN
1.5
R
500 K
Auto Latch
P21-P26
Z8 Microcontrollers
I/O Ports
ZiLOG
5-10
UM001601-0803
5.4 PORT 2
(Continued)
Figure 5-13. Port 2 Configuration with TTL Level Shifter
OEN
PIN
OUT
IN
TTL Level Shifter
Open-Drain
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-11
Figure 5-14. Port 2 Configuration with Open-Drain Capability, Auto Latch, Schmitt-Trigger and SPI
P27 OUT
PIN
SPI Active
P27 IN
0 SOI D0 Enable
OPEN-DRAIN
R
500 K
Auto Latch
P27
P20 OE
PIN
P20 OUT
P20 IN
OPEN-DRAIN
R
500 K
Auto Latch
P20
SPI EN
SPI DO
P27 OE
SPI
SPI DO
SPI
Standard
Standard
1 P27 OUT
*SPI must be enabled with D0
D2
SCON
or
SPI DI
Z8 Microcontrollers
I/O Ports
ZiLOG
5-12
UM001601-0803
5.4.2 Read/Write Operations
Port 2 is accessed as General-Purpose Register P2 (02H). Port 2
is written by specifying P2 as an instruction's destination regis-
ter. Writing to Port 2 causes data to be stored in the output reg-
ister of Port 2, and reflected externally on any bit configured as
an output.
Port 2 is read by specifying P2 as the source register of an in-
struction. When an output bit is read, data on the external
pin is returned. Under normal loading conditions, this is equiva-
lent to reading the output register. However, if a bit of Port 2 is
defined as an open-drain output, the data returned is the value
forced on the output pin by the external system. This may not be
the same as the data in the output register. Reading input bits of
Port 2 also returns data on the external pins. However, inputs un-
der handshake control return data latched into the input register
via the input strobe.
5.4.3 Handshake Operation
Port 2 can be placed under handshake control by programming
bit 6 in the Port 3 Mode Register (Figure 5-15). In this configu-
ration, Port 3 lines P31 and P36 are used as the handshake con-
trol lines DAV2 and RDY2 for input handshake, or RDY2 and
DAV2 for output handshake.
Handshake direction is determined by the configuration (input or
output) assigned to bit 7 of Port 2. Only those bits with the same
configuration as P27 will be under handshake control. Figure 5-
16 illustrates bit lines of Port 2 and the associated handshake
lines of Port 3.
Figure 5-15. Port 2 Handshake Configuration
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 3 Mode Register
Register F7H
1 P31 =
DAV2
/RDY2 P36 = RDY2/
DAV2
0 P31 = Input (T
IN
) P36 = Output (T
OUT
)
Port 2 Handshaking
Figure 5-16. Port 2 Handshaking
Handshake Controls
DAV2
and RDY2
(P3
1
and P3
6
)
P2
7
Port 2 (I/O)
P2
0
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-13
5.5 PORT 3
5.5.1 General Port I/O
Port 3 differs structurally from Port 0, 1, and 2. Port 3 lines are
fixed as four inputs (P33P30) and four outputs (P37P34) Port
3 does not have an input and output register for each bit. Instead,
all the input lines have one input register, and all the output lines
have an output register. Port 3 can be a CMOS- or TTL- compat-
ible I/O port. Under software control, the lines can be configured
as special control lines for handshake, comparator inputs, SPI
control, external memory status, or I/O lines for the on-board se-
rial and timer facilities. Figure 5-17 is a generic block diagram
of Port 3.
The inputs can be Schmitt-triggered, level-shifted, or single-trip
point buffered. In some cases, the Z8 may have auto latches
hardwired on certain Port 3 inputs and Low-EMI capabilities on
the outputs. Please refer to specific product specifications for ex-
act input/output buffer type features. Please refer to the section
on counter/timers, Stop-Mode Recovery, serial I/O, compara-
tors, and interrupts for more information on the relationships of
Port 3 to that feature.
Figure 5-17. Port 3 Block Diagram
Input
Buffer
Input
Register
Output
Buffer
Output
Register
Output
Register
Write
Port
Read
Port
4
4
4
4
4
4
4
4
Internal
Bus
From Timer,
Handshake Logic,
or Serial I/O
To Interrupt Timer,
Handshake Logic,
or Serial I/O
Port
Output
Lines
P3
4
- P3
7
Port
Input
Lines
P3
0
- P3
3
Read
Port
Input
Buffer
Output
Buffer
Output
Register
Output
Buffer
Data
Return
Z8 Microcontrollers
I/O Ports
ZiLOG
5-14
UM001601-0803
5.5 PORT 3
(Continued)
Figure 5-18. Port 3 Configuration with Comparator, Auto Latch, and Schmitt-Trigger
P31 (AN1)
R247 = P3M
+
-
IRQ2, T
IN
, P31 Data Latch
P30
+
-
1 = Analog
0 = Digital
D1
R
500 K
Auto Latch
Port 3
(I/O or Control)
P30 Data
Latch IRQ3
Z8
P34
P35
P37
P36
P30
P31
P32
P33
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
P32 (AN2)
P33 (REF)
From Stop-Mode
Recovery Source
DIG.
AN.
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-15
Figure 5-19. Port 3 Configuration with Comparator
PIN
P37
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
D0
P37 OUT
PCON
P32
REF (P33)
+
-
PIN
P34
P37 OUT
P32
REF (P33)
+
-
Z8 Microcontrollers
I/O Ports
ZiLOG
5-16
UM001601-0803
5.5 PORT 3
(Continued)
Figure 5-20. Port 3 Configuration with SPI and Comparator Outputs Using P34 and P35
SPI MSTR
PIN
P31
+
SPI EN
P34
SK IN
SPI MSTR
PIN
P35
SPI EN
REF
SS
0 P34, P35 Standard Output
1 P34, P35 Comparator Output
D0
P34 OUT
PCON
P31
REF
+
-
P34 OUT
-
SPI EN
SK OUT
MUX
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-17
5.5.2 Read/Write Operations
Port 3 is accessed as a General-Purpose Register P3 (03H). Port
3 is written by specifying P3 as an instruction's destination reg-
ister. However, Port 3 outputs cannot be written to if they are
used for special functions. When writing to Port 3, data is stored
in the output register.
Port 3 is read by specifying P3 as the source register of an in-
struction. When reading from Port 3, the data returned is both the
data on the input pins and in the output register.
5.5.3 Special Functions
Special functions for Port 3 are defined by programming the Port
3 Mode Register. By writing 0s in bit 6 through bit 1, lines
P37P30 are configured as input/output pairs (Figure 5-22). Ta-
ble 5-1 shows available functions for Port 3. The special func-
tions indicated in the figure are discussed in detail in their corre-
sponding sections in this manual.
Port 3 input lines P33P30 always function as interrupt requests
regardless of the configuration specified in the Port 3 Mode Reg-
ister.
Figure 5-21. Port 3 Configuration with TTL Level Shifter and Auto Latch
PIN
PIN
OUT
R
500 K
Auto Latch
IN
TTL Level Shifter
Port 3 Output Configuration
Port 3 Input Configuration
Z8 Microcontrollers
I/O Ports
ZiLOG
5-18
UM001601-0803
Figure 5-22. Port 3 Mode Register Configuration
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input P35 = Output
0 Port 2 Open-Drain
1 Port 2 Push-Pull
00 P33 = Input P34 = Output
01 P33 = Input P34 = /DM
Port 3 Mode Register
Register F7H
10 P33 = Input P34 = /DM
0 P31 = Input P36 = Output
0 P30 = Input P37 = Output
1 P30 = Serial In P37 = Serial Out
0 Party ON
1 Party OFF
Table 5-1. Port 3 Line Functions
Function
Line
Signal
Inputs
P30
Input
P31
Input
P32
Input
P33
Input
Outputs
P34
Output
P35
Output
P36
Output
P37
Output
Port 0 Handshake Input
P32
DAV0/RDY0
Port 1 Handshake Input
P33
DAV1/RDY1
Port 2 Handshake Input
P31
DAV2/RDY2
Port 0 Handshake Output
P35
RDY0/DAV0
Port 1 Handshake Output
P34
RDY1/DAV1
Port 2 Handshake Output
P36
RDY2/DAV2
Analog Comparator Input
P31
AN1
P32
AN2
P33
REF
Analog Comparator Output
P34
AN1-OUT
P35
AN2-OUT
P37
AN2-OUT
Interrupt Requests
P30
IRQ3
P31
IRQ2
P32
IRQ0
P33
IRQ1
Serial Input (UART)
P30
DI
Serial Output (UART)
P37
DO
SPI Slave Select
P35
SS
SPI Clock
P34
SK
Counter/Timer
P31
T
IN
P36
T
OUT
External Memory Status
P34
DM
Table 5-1. Port 3 Line Functions
Function
Line
Signal
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-19
5.6 PORT HANDSHAKE
When Ports 0, 1, and 2 are configured for handshake operation,
a pair of lines from Port 3 are used for handshake controls. The
handshake controls are interlocked to properly time asynchro-
nous data transfers between the Z8 and a peripheral. One con-
trol line (/DAV) functions as a strobe from the sender to indicate
to the receiver that data is available. The second control line
(RDY) acknowledges receipt of the sender's data, and indicates
when the receiver is ready to accept another data transfer.
In the input mode, data is latched into the Port's input register by
the first /DAV signal, and is protected from being overwritten if
additional pulses occur on the /DAV line. This overwrite protec-
tion is maintained until the port data is read. In the output mode,
data written to the port is not protected and can be overwritten
by the Z8 during the handshake sequence. To avoid losing data,
the software must not overwrite the port until the corresponding
interrupt request indicates that the external device has latched
the data.
The software can always read Port 3 output and input handshake
lines, but cannot write to the output handshake line.
The following is the recommended setup sequence when config-
uring a Port for handshake operation for the first time after a re-
set:
Load P01M or P2M to configure the port for input/output.
Load P3 to set the Output Handshake bit to a logic 1.
Load P3M to select the Handshake Mode for the port.
Once a data transfer begins, the configuration of the handshake
lines should not be changed until the handshake is completed.
Figures 5-23 and 5-24 show detailed operation for the handshake
sequence.
Figure 5-23. Z8 Input Handshake
Valid Data
(Input To Z8)
State 1.
2
1
3
4
5
/DAV
(Output From Z8)
RDY
(Input To Z8)
Data on Port
Port 3 output is High, indicating that the I/O device is ready to accept data.
State 2.
The I/O device puts data on the port and then activates the
DAV
input. This causes the data to be latched
.
State 3.
The Z8 forces the Ready (RDY) output Low, signaling to the I/O device that the data has been latched.
State 4.
The I/O device returns the
DAV
line High in response to RDY going Low.
State 5.
The Z8 RR software must respond to the interrupt request and read the contents of the port in order for the
into the port input register and generates an interrupt request.
handshake sequence to be completed. The RDY line goes High if and only if the port has been read and
DAV
is High. This returns the interface to its initial state.
Z8 Microcontrollers
I/O Ports
ZiLOG
5-20
UM001601-0803
5.6 PORT HANDSHAKE
(Continued)
Figure 5-24. Z8 Output Handshake
Valid Data
(Input To Z8)
State 1.
2
1
3
4
5
RDY
(Output From Z8)
DAV
(Output From Z8)
Data on Port
RDY input is High indicating that the I/O device is ready to accept data.
State 2.
The Z8 Writes to the port register to initiate a data transfer. Writing to the port outputs new data and
forces
DAV
Low if and only if RDY is High.
State 3.
The I/O device forces RDY Low after latching the data. RDY Low causes an interrupt request to be generated.
The Z8 can write new data responses to RDY going Low; however, the data is not output until State 5.
State 4.
The
DAV
output from the Z8 is driven High in response to RDY going Low.
State 5.
The
DAV
goes High, the I/O device is free to raise RDY High thus returning the interface to its initial state.
Z8 Microcontrollers
I/O Ports
ZiLOG
5-21
UM001601-0803
5.6 PORT HANDSHAKE
(Continued)
In applications requiring a strobed signal instead of the inter-
locked handshake, the Z8 MCU can satisfy this requirement as
follows:
In the Strobed Input mode, data can be latched in the Port input
register using the DAV input. The data transfer rate must
allow enough time for the software to read the Port before
strobing in the next character. The RDY output is ignored.
In the Strobed Output Mode, the RDY input should be tied to
the DAV output.
Figures 5-25 and 5-26 illustrate the strobed handshake connec-
tions.
Figure 5-25. Output Strobed Handshake on Port 2
P3
6
Z8
P2
0
- P2
7
P3
1
I/O
Device
DAV
RDY
Figure 5-26. Input Strobed Handshake on Port 2
Z8
P2
0
- P2
7
P3
1
I/O
Device
DAV
Z8 Microcontrollers
I/O Ports
ZiLOG
5-22
UM001601-0803
5.7 I/O PORT RESET CONDITIONS
5.7.1 Full Reset
After a hardware reset, Watch-Dog Timer (WDT) reset, or a
Power-On Reset (POR), Port Mode Registers P01M, P2M, and
P3M are set as shown in Figures 5-27 through 5-22. Port 2 is
configured for input operation on all bits and is set for open-
drain (Figure 5-29). If push-pull outputs are desired for Port 2
outputs, remember to configure them using P3M. Please note
that a WDT time-out from Stop-Mode Recovery does not do a
full reset. Certain registers that are not reset after Stop-Mode Re-
covery will not be reset.
For the condition of the Ports after Stop-Mode Recovery, please
refer to specific device product specifications. In some cases, the
Z8 has the P01M, P2M, and P3M control register set back to the
default condition after reset while others do not.
All special I/O functions of Port 3 are inactive, with P33P30 set
as inputs and P37P34 set as outputs (Figure 5-29).
Note: Because the types and amounts of I/O vary greatly among
the Z8 family devices, the user is advised to review the selected
device's product specifications for the register default state after
reset.
Figure 5-27. Port 0/1 Reset
0 1 0 0 1 1 0 1
(Write-Only)
01 = Input
1X = A
8
- A
11
Stack Selection
0 = External
P0
0
- P0
3
Mode
00 = Output
Port 0-1 Mode Register (P01M)
Register F8H
01 = Byte Output
1 = Internal
External Memory Timing
Normal = 0
Extended = 1
P0
4
- P0
7
Mode
Output = 00
Input = 01
A
12
- A
15
= 1X
10 = AD
0
- AD
7
00 = Byte Output
P
10
- P
17
Mode

A
8
- A
15
,
AS
,
DS
,
R
/W
11 = High Impedance AD
0
- AD
7,
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-23
Figure 5-28. Port 2 Reset
1 1 1 1 1 1 1 1
(Write-Only)
1 = Input
Port 2 Mode
0 = Output
Port 2 Mode Register (P2M)
Register F6H
Figure 5-29. Port 3 Mode Reset
0 0 0 0 0 0 0 0
(Write-Only)
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input P35 = Output
1 P32 = DAV0/RDY0 P35 = RDY0/DAV0
0 Port 2 Open-Drain
1 Port 2 Push-Pull
00 P33 = Input P34 = Output
01 P33 = Input P34 = DM
Port 3 Mode Register (P3M)
Register F7H
10 P33 = Input P34 = DM

11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
0 P31 = Input P36 = Output
1 P32 = DAV2/RDY2 P36 = RDY2/DAV2
0 P30 = Input P37 = Output
1 P30 = Serial In P37 = Serial Out
0 Parity OFF
1 Parity ON
Z8 Microcontrollers
I/O Ports
ZiLOG
5-24
UM001601-0803
5.8 ANALOG COMPARATORS
Select Z8 devices include two independent on-chip analog com-
parators. See the device product specification for feature avail-
ability and use. Port 3, Pins P31 and P32 each have a comparator
front end. The comparator reference voltage, pin P33, is com-
mon to both comparators. In Analog Mode, the P31 and P32 are
the positive inputs to the comparators and P33 is the reference
voltage supplied to both comparators. In Digital Mode, pin P33
can be used as a P33 register input or IRQ1 source. P34, P35, or
P37 may output the comparator outputs by software-program-
ming the PCON Register bit D0 to 1.
5.8.1 Comparator Description
Two on-board comparators can process analog signals on P31
and P32 with reference to the voltage on P33. The analog func-
tion is enabled by programming the Port 3 Mode Register (P3M
bit 1). For interrupt functions during analog mode, P31 and P32
can be programmable as rising, falling, or both edge triggered in-
terrupts (IRQ register bits 6 and bit 7).
Note: P33 cannot generate an external interrupt while in this
mode. P33 can only generate interrupts in the Digital Mode.
Note: Port 3 inputs must be in digital mode if Port 3 is a Stop-
Mode Recovery source. The analog comparator is disabled in
STOP mode.
P31 can be used as T
IN
in Analog or Digital Modes, but it must
be referenced to P33, when in Analog Mode.
Figure 5-30. Port 3 Input Analog Selection
D1
(Write-Only)
0 = Digital Mode P31, P32, P33
1 = Analog Mode P31, P32, P33
Port 3 Mode Register (P3M)
Register F7H
Figure 5-31. Port 3 Comparator Output Selection
D0
(Write-Only)
0 = P34, P35, or P37 Standard Outputs
1 = P34, P35, or P37 Comparator Outputs
Port Configuration Register (PCON)
Register 00H
ERF Bank F
Z8 Microcontrollers
I/O Ports
ZiLOG
5-25
UM001601-0803
5.8 ANALOG COMPARATORS
(Continued)
Figure 5-32. Port Configuration of Comparator Inputs on P31, P32, and P33
P31 (AN1)
R247 = P3M
+
-
IRQ2, T
IN
, P31 Data Latch
P30
+
-
1 = Analog
0 = Digital
D1
R
500 K
Auto Latch
Port 3
(I/O or Control)
P30 Data
Latch IRQ3
Z8
P34
P35
P37
P36
P30
P31
P32
P33
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
P32 (AN2)
P33 (REF)
From Stop-Mode
Recovery Source
DIG.
AN.
Z8 Microcontrollers
I/O Ports
ZiLOG
5-26
UM001601-0803
5.8.2 Comparator Programming
Example of enabling analog comparator mode.
Note: X = Any Binary Number
Example of enabling analog comparator output.
Figure 5-33. Port 3 Configuration
PIN
P37
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
D0
P37 OUT
PCON
P32
REF (P33)
+
-
PIN
P34
P34 OUT
P31
REF (P33)
+
-
LD P3M, #XXXX XX1XB
LD RP, #%0FH
;Sets register pointer to
;working register group 0
;and Expanded Register
;File Bank F.
LD R0, #XXXX
XXX1B
;Enables comparator
;outputs using PCON
;Register programming.
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-27
5.8.3 COMPARATOR OPERATION
After enabling the Analog Comparator mode, P33 becomes a
common reference input for both comparators. The P33 (Ref) is
hard wired to the reference inputs to both comparators and can-
not be separated. P31 and P32 are always connected to the posi-
tive inputs to the comparators. P31 is the positive input to com-
parator AN1 while P32 is the positive input to comparator AN2.
The outputs to comparators AN1 and AN2 are AN1-out and
AN2-out, respectively.
The comparator output reflects the relationship between the pos-
itive input to the reference input.
Example: If the voltage on AN1 is higher than the voltage on Ref
then AN1-out will be at a high state. If voltage on AN2 is lower
than the voltage on Ref then AN2-out will be at a Low state. In
this example, when the Port 3 register is read, Bits D1 = 1 and
D2 = 0. If the comparator outputs are enabled to come out on P34
and P37, then P34 = 1 and P37 = 0. Please note that the previous
data stored in P34 and P37 is not disturbed. Once the comparator
outputs are de-selected the stored values in the P34 and P37 reg-
ister bits will be reflected on these pins again.
5.8.4 Interrupts
In the example from Section 5.8.3, P32 (AN2) will generate an
interrupt based on the result of the comparison being low and the
Interrupt Request Register (IRQ FAH) having bits D7=0 and
D6=0. If IRQ D7=1 and D6=0 then both P31 and P32 would
generate interrupts.
5.8.5 Comparator Definitions
5.8.5.1 V
ICR
The usable voltage range for both positive inputs and the refer-
ence input is called the common mode voltage range (V
ICR
). The
comparator is not guaranteed to work if the inputs are outside of
the V
ICR
range.
5.8.5.2 V
OFFSET
The absolute value of the voltage between the positive input and
the reference input required to make the comparator output volt-
age switch is the input offset voltage (V
OFFSET
). If AN1 is 3.000V
and Ref is 3.001V when the comparator output switches states
then the Voffset = 1mV.
5.8.5.3 I
IO
For CMOS voltage comparator inputs, the input offset current
(I
IO
) is the leakage current of the CMOS input gate.
5.8.6 RUN Mode
P33 is not available as an interrupt input during Analog Mode.
P31 and P32 are valid interrupt inputs in conjunction with P33
(Ref) when in the Analog Mode.
P31 can still be used as T
IN
when the analog mode is selected. If
comparator outputs are desired to be outputted on the Port 3 out-
puts, please refer to specific products specification for priority of
mixing when other special features are sharing those same Port
3 pins.
5.8.7 HALT Mode
The analog comparators are functional during HALT Mode if
the Analog Mode has been enabled. P31 and P32, in conjunction
with P33 (Ref) will be able to generate interrupts. Only P33 can-
not generate an interrupt since the P33 input goes directly to the
Ref input of the comparators and is disconnected from the inter-
rupt sensing circuits.
5.8.8 STOP Mode
The analog comparators are disabled during STOP Mode so it
does not use any current at that time. If P31, P32, or P33 are used
as a source for Stop-Mode Recovery, the Port 3 Digital Mode
must be selected by setting bit D1=0 in the Port 3 Mode Register.
Otherwise in STOP Mode, the P31, P32, and P33 cannot be
sensed. If the Analog Mode was selected when entering STOP
Mode, it will still be enabled after a valid SMR triggered reset.
Z8 Microcontrollers
I/O Ports
ZiLOG
5-28
UM001601-0803
5.9 OPEN-DRAIN CONFIGURATION
All Z8s can configure Port 2 to provide open-drain outputs by
programming the Port 3 Mode Register (P3M) bit D0=0.
Other Z8s that have a Port Configuration Register (PCON) that
can configure Port 0 and Port 1 to provide open-drain outputs.
The PCON Register is located in Expanded Register File (ERF)
Bank F, Register 00H. See Figure 5-35.
Port 1 Open-Drain (D1). Port 1 can be configured as open-drain
by resetting this bit (D1=0) or configured as push-pull active by
setting this bit (D1=1). The default value is 1.
Port 0 Open Drain (D2). Port 0 can be configured as open-drain
by resetting this bit (D2=0) or configured as push-pull active by
setting this bit (D2=1). The default value is 1.
5.10 LOW EMI EMISSION
Some Z8s can be programmed to operate in a Low EMI Emis-
sion Mode using the Port configuration register (PCON). The
PCON register allows the oscillator and all I/O ports to be pro-
grammed in the Low-EMI Mode independently. Other Z8s may
offer a ROM Mask or OTP programming option to configure the
Z8 Ports and oscillator globally to a Low-EMI mode (where the
XTAL frequency is set equal to the internal system clock fre-
quency.
Use of the Low EMI feature results in:
The output pre-drivers slew rate reduced to 10 ns (typical).
Low EMI output drivers have resistance of 200 Ohms
(typical).
Low EMI Oscillator.
All output drivers are approximately 25 percent of the
standard drive.
Internal SCLK/TCLK = XTAL operation limited to a
maximum of 4 MHz - 250 ns cycle time, when Low EMI
Oscillator is selected and system clock (SCLK=XTAL, SMR
Reg. Bit D1=1).
Figure 5-34. Port 2 Configuration
Figure 5-35. Port Configuration Register (PCON) (Write-
Only)
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
0= Pull-Ups Active
Port 2 Configuration
1= Pull-Ups Open-Drain
Port 3 Mode Register
Register F7H
D7 D6 D5 D4 D3 D2 D1 D0
PCON (FH) 00H
0 Port 1 Open Drain
1 Port 1 Push-pull Active *
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Comparator Output Port 3
Low EMI Oscillator
0 Port 0 Open Drain
1 Port 0 Push-pull Active *
0 Port 0 Low EMI
1 Port 0 Standard *
0 Port 1 Low EMI
1 Port 1 Standard *
0 Port 2 Low EMI
1 Port 2 Standard *
0 Low EMI
1 Standard *
0 Port 3 Low EMI
1 Port 3 Standard *
* Default Setting After RESET
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-29
For Z8s having the PCON register feature, the following bits
control the Low EMI options:
Low EMI Port 0 (D3). Port 0 can be configured as a Low
EMI Port by resetting this bit (D3=0) or configured as a
Standard Port by setting this bit (D3=1). The default value is 1.
Low EMI Port 1 (D4). Port 1 can be configured as a Low
EMI Port by resetting this bit (D4=0) or configured as a
Standard Port by setting this bit (D4=1). The default value is 1.
Low EMI Port 2 (D5). Port 2 can be configured as a Low
EMI Port by resetting this bit (D5=0) or configured as a
Standard Port by setting this bit (D5=1). The default value is 1.
Low EMI Port 3 (D6). Port 3 can be configured as a Low
EMI Port by resetting this bit (D6=0) or configured as a
Standard Port by setting this bit (D6=1). The default value is 1.
Low EMI OSC (D7). This bit of the PCON Register controls
the Low EMI oscillator. A 1 in this location configures the
oscillator with standard drive, while a 0 configures the
oscillator with low noise drive. The Low-EMI mode will
reduce the drive of the oscillator (OSC). The default value is
1. XTAL/2 mode is not effected by this bit.
Note: The maximum external clock frequency is 4 MHz when
running in the Low EMI oscillator mode.
Please refer to the selected device product specification for
availability of the Low EMI feature and programming options.
5.11 INPUT PROTECTION
All CMOS ROM Z8s have I/O pins with diode input protection.
There is a diode from the I/O pad to V
CC
and to V
SS
. See Figure
5-36.
On CMOS OTP EPROM Z8s, the Port 3 inputs P31, P32, P33
and the XTAL 1 pin have only the input protection diode from
pad to V
SS
. See Figure 5-37.
The high-side input protection diodes were removed on these
pins to allow the application of +12.5V during the various OTP
programming modes.
For better noise immunity in applications that are exposed to
system EMI, a clamping diode to V
CC
from these pins may be re-
quired to prevent entering the OTP programming mode or to pre-
vent high voltage from damaging these pins.
Figure 5-36. Diode Input Protection
PIN
V
CC
V
SS
Figure 5-37. OTP Diode Input Protection
PIN
V
SS
Z8 Microcontrollers
I/O Ports
ZiLOG
5-30
UM001601-0803
5.12 Z8 CMOS AUTO LATCHES
I/O port bits that are configurable as inputs are protected against
open circuit conditions using Auto Latches. An Auto Latch is a
circuit which, in the event of an open circuit condition, latches
the input at a valid CMOS level. This inhibits the tendency of the
input transistors to self-bias in the forward active region, thus
drawing excessive supply current. A simplified schematic of the
CMOS Z8 I/O circuit is shown in Figure 5-38.
The operation of the Auto Latch circuit is straight-forward. As-
sume the input pad is latched at +5V (logic 1). The inverter G1
inverts the bit, turning the P-channel FET ON and the N-channel
FET OFF. The output of the circuit is effectively shorted to V
DD
,
returning +5V to the input. If the pad is then disconnected from
the +5V source, the Auto Latch will hold the input at the previ-
ous state. If the device is powered up with the input floating, the
state of the Auto Latch will be at either supply, but which state
is unpredictable.
There are four operating conditions which will activate the Auto
Latches. The first, which occurs when the input pin is physically
disconnected from any source, is the most obvious. The second
occurs when the input is connected to the output of a device with
tri-state capability.
The Auto Latch will also activate when the input voltage at the
pin is not within 200 microvolts or so of either supply rail. In this
case, the circuit will draw current, which is not significant com-
pared to the Icc operating current of the device, but will increase
I
CC2
STOP Mode current of the device dramatically.
The fourth condition occurs when the I/O bit is configured as an
output. Referring to the output section of Figure 5-38, there are
two ways of tri-stating the port pin. The first is by configuring
the port as an input, which disables the OE signal turning both
transistors off. The second can be achieved in output mode by
writing a "1" to the output port, then activating the open drain
mode. Both transistors are again off, and the port bit is in a high
impedance state. The Auto Latches then pull the input section to-
ward V
DD
.
Figure 5-38. Simplified CMOS Z8 I/O Circuit
Open-Drain
PIN
V
DD
OE
Data Out
Data In
Auto Latch
G1
N
P
V
DD
N
P
Z8 Microcontrollers
ZiLOG
I/O Ports
UM001601-0803
5-31
Auto Latch Model:
The Auto Latch's equivalent circuit is shown in Figure 5-39.
When the input is high, the circuit consists of a resistance Rp
from V
DD
(the P-channel transistor in its ON state) and a much
greater resistance Rh to G
ND
. Current Iao flows from V
DD
to the
output. When the input is low, the circuit may be modeled as a
resistance Rp from G
ND
(the N-channel transistor in the ON
state) and a much greater resistance Rh to V
DD
. Current Iao now
flows from the input to ground. The Auto Latch is characterized
with respect to Iao, so the equivalent resistance Rp is calculated
according to R
P
= (V
DD
-VIN)/I
AO
. The worst case equivalent re-
sistance Rp (min) may be calculated at the worst case input volt-
age, V
I
= V
IH
(min).
Design Considerations:
For circuits in which the Auto Latch is active, consideration
should be given to the loading constraints of the Auto Latches.
For example, with weak values of V
IN
, close to Vih (min) or Vil
(max), pullup or pull-down resistances must be calculated using
Ref = R/Rp. For best case STOP mode operation, the inputs
should be within 200 mV of the supply rails.
In output mode, if a port bit is forced into a tri-state condition,
the Auto Latches will force the pad to V
DD
. If there is an external
pulldown resistor on the pin, the voltage at the pin may not
switch to GND due to the Auto Latch. As shown in Figure 5-40,
the equivalent resistance of the Auto Latch and the external pull-
down form a voltage divider, and if the external resistor is large,
the voltage developed across it will exceed Vil(max). For worst
case:
V
IL
(max > V
DD
[Rext/(Rext+Rp)]
Rext(max) = [(Vil(max)/V
DD
)Rp]/[1-(Vil(max)/V
DD
)]
For V
DD
= 5.0V and Iao = 5 uA we have Vih(max) =0.8V:
R
EXT
(max) = (0.16/1M)/(10.16) = 190 K ohms.
Rp increases rapidly with V
DD
, so increased V
DD
will relax the
requirement on Rext.
In summary, the CMOS Z8 Auto Latch inhibits excessive cur-
rent drain in Z8 devices by latching an open input to either V
DD
or GND. The effect of the Auto Latch on the I/O characteristics
of the device may be modeled by a current Iao and a resistor Rp,
whose value is V
DD
/Iao.
Figure 5-39. Auto Latch Equivalent Circuit
V
DD
Data in
PIN
Logic 1
A0
PIN
V
DD
R
P
R
H
R
H
R
P
Data in
Logic 0
A0
Figure 5-40. Effect of Pulldown Resistors on Auto Latches
V
LO
V
IH
(min.)
R
P
R
EXT
Z8 Microcontrollers
I/O Ports
ZiLOG
5-32
UM001601-0803
UM001601-0803
6-1
U
SER
'
S
M
ANUAL
C
HAPTER
6
C
OUNTER
/T
IMERS
6.1 INTRODUCTION
The Z8 MCU
provides up to two 8-bit counter/timers, T0 and
T1, each driven by its own 6-bit prescaler, PRE0 and PRE1 (Fig-
ure 6-1). Both counter/timers are independent of the processor
instruction sequence, that relieves software from time-critical
operations such as interval timing or event counting. Some
MCUs offer clock scaling using the SMR register. See the device
product specification for clock available options. The following
description is typical.
Each counter/timer operates in either Single-Pass or Continuous
mode. At the end-of-count, counting either stops or the initial
value is reloaded and counting continues. Under software con-
trol, new values are loaded immediately or when the end-of-
count is reached. Software also controls the counting mode, how
a counter/timer is started or stopped, and its use of I/O lines. Both
the counter and prescaler registers can be altered while the
counter/timer is running.
Figure 6-1. Counter/Timer Block Diagram
2
OSC
D1 (SMR)
16
D0 (SMR)
Clock
4
Logic
Internal
Clock
External Clock
Internal Clock
Gated Clock
Triggered Clock
T
IN
P31
4
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Read
Write
Write
Read
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
2
Internal Data Bus
Internal Data Bus
T
OUT
IRQ
4
P36
IRQ
5
Z8 Microcontrollers
Counter/Timers
ZiLOG
6-2
UM001601-0803
Counter/timers 0 and 1 are driven by a timer clock generated by
dividing the internal clock by four. The divide-by-four stage, the
6-bit prescaler, and the 8-bit counter/timer form a synchronous
16-bit divide chain. Counter/timer 1 can also be driven by a ex-
ternal input (T
IN
) using P31. Port 3 line P36 can serve as a timer
output (T
OUT
) through which T0, T1, or the internal clock can be
output. The timer output will toggle at the end-of-count.
The counter/timer, prescaler, and associated mode registers are
mapped into the register file as shown in Figure 6-2. This allows
the software to treat the counter/timers as general-purpose regis-
ters, and eliminates the need for special instructions.
6.2 PRESCALERS AND COUNTER/TIMERS
The prescalers, PRE0 (F5H) and PRE1 (F3H), each consist of an
8-bit register and a 6-bit down-counter as shown in Figure 6-1.
The prescaler registers are write-only registers. Reading the
prescalers returns the value FFH. Figures 6-3 and 6-4 show the
prescaler registers.
The six most significant bits (D2-D7) of PRE0 or PRE1 hold the
prescalers count modulo, a value from 1 to 64 decimal. The pres-
caler registers also contain control bits that specify T0 and T1
counting modes. These bits also indicate whether the clock
source for T
1
is internal or external. These control bits will be
discussed in detail throughout this chapter.
The counter/timer registers, T0 (F4H) and T1 (F2H), each con-
sist of an 8-bit down-counter, a write-only register that holds the
initial count value, and a read-only register that holds the current
count value (Figure 6-1). The initial value can range from 1 to
256 decimal (01H,02H,..,00H). Figure 6-5 illustrates the
counter/timer registers.
Figure 6-2. Counter/Timer Register Map
HEX Identifiers
T0 Prescaler
F7
Timer/Counter0
Port 3 Mode
T1 Prescaler
Time/Counter1
Timer Mode
F5
F4
F3
F2
F1
DEC
247
245
244
243
242
241
Figure 6-3. Prescaler 0 Register
Figure 6-4. Prescaler 1 Register
Figure 6-5. Counter / Timer 0 and 1 Registers
D7 D6 D5 D4 D3 D2 D1 D0
(%F5; Write-Only)
1 = T
0
Modulo-n
Count Mode
0 = T
0
Single Pass
Prescaler 0 Register
R245 PRE0
01-00 HEX)
Prescaler Modulo
(Range: 1-64 Decimal
Reserved (Must be 0)
U U U U U U 0 0
(%F3; Write-Only)
1 = T
1
Modulo-n
Count Mode
0 = T
1
Single Pass
Prescaler 1 Register
R243 PRE1
01-00 HEX)
Prescaler Modulo
(Range: 1-64 Decimal
Clock Source
0 = T
1
External (T
IN
)
1 = T
1
Internal
D7 D6 D5 D4 D3 D2 D1 D0
(%F4; Write/Read Only)
current value when read
Initial value when written
(Range 1-256 decimal, 01-00 HEX)
Counter/Timer 0 Register
R244 T0
(%F2; Write/Read Only)
Counter/Timer 1 Register
R242 T1
Z8 Microcontrollers
ZiLOG
Counter/Timers
UM001601-0803
6-3
6.3 COUNTER/TIMER OPERATION
Under software control, counter/timers are started and stopped
via the Timer Mode Register (TMR,F1H) bits D
0
-D
3
(Figure 6-
6). Each counter/timer is associated with a Load bit and an En-
able Count bit.
6.3.1 Load and Enable Count Bits
Setting the Load bit (D
0
for T0 and D
2
for T1) transfers the initial
value in the prescaler and the counter/timer registers into their
respective down-counters. The next internal clock resets bits D
0
and D
2
to 0, readying the Load bit for the next load operation.
New values may be loaded into the down-counters at any time.
If the counter/timer is running, it continues to do so and starts the
count over with the new value. Therefore, the Load bit actually
functions as a software re-trigger.
The counter timers remain at rest as long as the Enable Count
bits are 0. To enable counting, the Enable Count bit (D
1
for T0
and D
3
for T1) must be set to 1. Counting actually starts when
the Enable Count bit is written by an instruction. The first decre-
ment occurs four internal clock periods after the Enable Count
bit has been set. If T1 is configured to use an external clock, the
first decrement begins on the next clock period. The Load and
Enable Count bits can be set at the same time. For example, us-
ing the instruction:
OR TMR,#03H
sets both D0 and D1 of the TMR. This loads the initial values of
PRE0 and T0 into their respective counters and starts the count
after the M2T2 machine state after the operand is fetched (Figure
6-7).
Figure 6-6. Timer Mode Register
D3 D2 D1 D0
(% F1; Read/Write)
0 = Disable T
0
Count
0 = No Function
1 = Load T
0
Timer Mode Register
R241 TMR
1 = Enable T
0
Count
0 = No Function
1 = Load T
1
0 = Disable T
1
Count
1 = Enable T
1
Count
Figure 6-7. Starting The Count
D0
(% F5; Write-Only)
Count Mode
Prescaler 0 Register
R245 PRE0
(% F3; Write-Only)
Prescaler 1 Register
R243 PRE1
0 = T
1
Single Pass
1 = T
1
Modulo-n
Figure 6-8. Counting Modes
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
TMR is Written, Counter/Timer
First Decrement Occurs
Four Clock Periods Later
is Loaded
#03H is Fetched
M3 M1 M2 Mn
Z8 Microcontrollers
Counter/Timers
ZiLOG
6-4
UM001601-0803
6.3.2 Prescaler Operations
During counting, the programmed clock source drives the 6-bit
Prescaler Counter. The counter is counted down from the value
specified by bits of the corresponding Prescaler Register, PRE0
(bit 7 to bit 2) or PRE1 (bit 7 to bit 2). (Figures 6-3, 6-4). When
the Prescaler Counter reaches its end-of-count, the initial value
is reloaded and counting continues. The prescaler never actually
reaches 0. For example, if the prescaler is set to divide-by-three,
the count sequence is:
Each time the prescaler reaches its end of count a carry is gener-
ated, that allows the Counter/Timer to decrement by one on the
next timer clock input. When the Counter/Timer and the prescal-
er both reach the end-of-count, an interrupt request is generated
(IRQ4 for T0, IRQ5 for T1). Depending on the counting mode
selected, the Counter/Timer will either come to rest with its val-
ue at 00H (Single-Pass Mode) or the initial value will be auto-
matically reloaded and counting will continue (Continuous
Mode). The counting modes are controlled by bit 0 of PRE0 and
bit 0 of PRE1. (Figure 6-8). A 0, written to this bit configures the
counter for Single-pass counting mode, while a 1 written to this
bit configures the counter for Continuous mode.
The Counter/Timer can be stopped at any time by setting the En-
able Count bit to 0, and restarted by setting it back to 1. The
Counter/Timer will continue its count value at the time it was
stopped. The current value in the Counter/Timer can be read at
any time without affecting the counting operation.
Note: The prescaler registers are write-only and cannot be read.
New initial values can be written to the prescaler or the
Counter/Timer registers at any time. These values will be trans-
ferred to their respective down counters on the next load opera-
tion. If the Counter/Timer mode is continuous, the next load oc-
curs on the timer clock following an end-of-count. New initial
values should be written before the desired load operation, since
the prescalers always effectively operate in Continuous count
mode.
The time interval (i) until end-of-count, is given by the equation:
The internal clock frequency defaults to the external clock
source (XTAL, ceramic resonator, and others) divided by 2.
Some Z8 microcontrollers allow this divisor to be changed via
the Stop-Mode Recovery register. See the product data sheet for
available clock divisor options.
Note that t is equal to eight divided-by-XTAL frequency of the
external clock source for T1 (external clock mode only).
p = the prescaler value (1 63) for T
0
and T
1
.
The minimum prescaler count of 1 is achieved by loading
000001xx. The maximum prescaler count of 63 is achieved by
loading 111111xx.
v = the Counter/Timer value (1-256)
Minimum duration is achieved by loading 01H (1 prescaler out-
put count), maximum duration is achieved by loading 00H (256
prescaler outputs counts).
The prescaler and counter/timer are true divide-by-n counters.
3213213213...
i = t X p X v
in which:
t = four times the internal clock period.
Z8 Microcontrollers
ZiLOG
Counter/Timers
UM001601-0803
6-5
6.4 T
OUT
MODES
The Timer Mode Register TMR (F1H) (Figure 6-9), is used in
conjunction with the Port 3 Mode Register P3M (F7H) (Figure
6-10) to configure P36 for T
OUT
operation for T0 and T1. In or-
der for T
OUT
to function, P36 must be defined as an output line
by setting P3M bit 5 to 0. Output is controlled by one of the
counter/timers (T0 or T1) or the internal clock.
Figure 6-9. Timer Mode Register (T
OUT
Operation)
D7 D6 D3 D0
(Read/Write)
0 = No Function
1 = Load T
0
Timer Mode Register (TMR)
Register F1HR
T
OUT
Modes:
0 = Disable T
1
Count
1 = Enable T
1
Count
T
OUT
OFF = 00
T
0
OUT = 01
T
1
OUT = 10
Internal Clock OUT = 11
Figure 6-10. Port 3 Mode Register (T
OUT
Operation)
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 3 Mode Register (P3M)
Register F7H
0 P31 = Input (T
IN
) P36 = Output (T
OUT
)
1 P31 = DAV2/RDY2 P36 = RDY2/DAV2
Z8 Microcontrollers
Counter/Timers
ZiLOG
6-6
UM001601-0803
6.4 T
OUT
MODES
(Continued)
The counter/timer to be output is selected by TMR bit 7 and bit
6. T0 is selected to drive the T
OUT
line by setting bit 7 to 0 and
bit 6 to 1. Likewise, T1 is selected by setting bit 7 and bit 6 to 1
and 0, respectively. The counter/timer T
OUT
mode is turned off
by setting TMR bit and bit 6 both to 0, freeing P36 to be a data
output line.
T
OUT
is initialized to a logic 1 whenever the TMR Load bit (bit
0 for T0 or bit 1 for T2) is set to 1. The T
OUT
configuration timer
load, and Timer Enable Count bits for the counter/timer driving
the T
OUT
pin can be set at the same time. For example, using the
instruction:
OR TMR,#43H
Configures T0 to drive the T
OUT
pin (P36).
Sets the P36 T
OUT
pin to a logic 1 level.
Loads the initial PRE0 and T0 levels into their respective
counters and starts the counter after the M2T2 machine state
after the operand is fetched.
At end-of-count, the interrupt request line (IRQ4 or IRQ5),
clocks a toggle flip-flop. The output of this flip-flop drives the
T
OUT
line, P36. In all cases, when the selected counter/timer
reaches its end-of-count, T
OUT
toggles to its opposite state (Fig-
ure 6-11). If, for example, the counter/timer is in Continuous
Counting Mode, Tout will have a 50 percent duty cycle output.
This duty cycle can easily be controlled by varying the initial
values after each end-of-count.
The internal clock can be selected as output instead of T0 or T1
by setting TMR bit 7 and bit 6 both to 1. The internal clock
(XTAL frequency/2) is then directly output on P36 (Figure 6-
12).
While programmed as T
OUT
, P36 cannot be modified by a write
to port register P3. However, the Z8
software can examine the
P36 current output by reading the port register.
Figure 6-11. T0 and T1 Output Through T
OUT
2
P3
6
T
OUT
TMR
D
7
- D
6
= 01
IRQ
4
(T0 End-of-Count)
IRQ
5
(T1 End-of-Count)
TMR
D
7
- D
6
= 10
Figure 6-12. Internal Clock Output Through T
OUT
OSC
2
P3
6
T
OUT
Internal
TMR D
6
Clock
TMR D
7
Z8 Microcontrollers
ZiLOG
Counter/Timers
UM001601-0803
6-7
6.5 T
IN
MODES
The Timer Mode Register TMR (F1H) (Figure 6-13) is used in
conjunction with the Prescaler Register PRE1 (F3H) (Figure 6-
14) to configure P31 as T
IN
. T
IN
is used in conjunction with T1
in one of four modes:
External Clock Input
Gated Internal Clock
Triggered Internal Clock
Retriggerable Internal Clock
Note: The T
IN
mode is restricted for use with timer 1 only. To
enable the T
IN
mode selected (via TMR bits 4- 5), bit 1 of PRE1
must be set to 0.
The counter/timer clock source must be configured for external
by setting the PRE1 Register bit 2 to 1. The Timer Mode Regis-
ter bit 5 and bit 4 can then be used to select the desired T
IN
oper-
ation.
For T1 to start counting as a result of a T
IN
input, the Enable
Count bit (bit 3 in TMR) must be set to 1. When using T
IN
as an
external clock or a gate input, the initial values must be loaded
into the down counters by setting the Load bit (bit 2 in TMR) to
a 1 before counting begins. In the descriptions of T
IN
that follow,
it is assumed the programmer has performed these operations.
Initial values are automatically loaded in Trigger and Retrigger
modes so software loading is unnecessary.
Figure 6-13. Timer Mode Register (T
IN
Operation)
D5 D4
(Read/Write)
Timer Mode Register (TMR)
Register F1H
(Retriggerable)

(Non-retriggerable)
Trigger Input = 10
T
IN
= Modes:
External Clock Input = 00
Gate Input = 01
Trigger Input = 11
Figure 6-14. Prescaler 1 Register (T
IN
Operation)
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
1 = T
1
Internal Disable T
IN
Mode
Clock Source
0 = T
1
External Enable T
IN
Mode
Prescaler 1 Register (PRE1)
Register F3H
Z8 Microcontrollers
Counter/Timers
ZiLOG
6-8
UM001601-0803
It is suggested that P31 be configured as an input line by setting
P3M Register bit 5 to 0, although T
IN
is still functional if P31 is
configured as a handshake input.
Each High-to-Low transition on T
IN
generates an interrupt re-
quest IRQ2, regardless of the selected T
IN
mode or
the enabled/disabled state of T1. IRQ2 must therefore be masked
or enabled according to the needs of the application.
6.5.1 External Clock Input Mode
The T
IN
External Clock Input Mode (TMR bit 5 and bit 4 both
set to 0) supports counting of external events, where an event is
considered to be a High-to-Low transition on T
IN
(Figure 6-15).
Note: See the product data sheet for the minimum allowed T
IN
external clock input period (T
P
T
IN
).
Figure 6-15. External Clock Input Mode
D
P3
1
Internal
IRQ
2
TMR
T
IN
Clock
D
PRE1
T1
IRQ
5
D
5
- D
4
= 00
Clock
Z8 Microcontrollers
ZiLOG
Counter/Timers
UM001601-0803
6-9
6.5.2 Gated Internal Clock Mode
The T
IN
Gated Internal Clock Mode (TMR bit 5 and bit 4 set to
0 and 1 respectively) measures the duration of an external event.
In this mode, the T1 prescaler is driven by the internal timer
clock, gated by a High level on T
IN
(Figure 6-16). T1 counts
while T
IN
is High and stops counting while
T
IN
is Low. Interrupt request IRQ2 is generated on the High-to-
Low transition of T
IN
signalling the end of the gate input. Inter-
rupt request IRQ5 is generated if T1 reaches its end-of-count.
Figure 6-16. Gated Clock Input Mode
OSC
2
4
D
D
PRE1
P3
1
T1
IRQ
2
T
IN
IRQ
5
Gate
Internal
TMR
D
5 -
D
4
= 01
Clock
Z8 Microcontrollers
Counter/Timers
ZiLOG
6-10
UM001601-0803
6.5.3 Triggered Input Mode
The T
IN
Triggered Input Mode (TMR bits 5 and 4 are set to 1 and
0, respectively) causes T1 to start counting as the result of an ex-
ternal event (Figure 6-17). T1 is then loaded and clocked by the
internal timer clock following the first High-to-Low transition
on the T
IN
input. Subsequent T
IN
transitions do not affect T1. In
the Single-Pass Mode, the Enable bit is reset whenever T1 reach-
es its end-of-count. Further T
IN
transitions will have no effect on
T1 until software sets the Enable Count bit again. In Continuous
mode, once T1 is triggered counting continues until software re-
sets the Enable Count bit. Interrupt request IRQ5 is generated
when T1 reaches its end-of-count.
Figure 6-17. Triggered Clock Mode
OSC
2
4
D
D
PRE1
TMR
P3
1
T1
IRQ
2
T
IN
IRQ
5
Trigger
D
5
- D
4
= 11
Internal
TMR
D
5
= 1
Clock
Edge
Trigger
Z8 Microcontrollers
ZiLOG
Counter/Timers
UM001601-0803
6-11
6.5.4 Retriggerable Input Mode
The T
IN
Retriggerable Input Mode (TMR bits 5 and 4 are set to
1) causes T1 to load and start counting on every occurrence of a
High-to-Low transition on T
IN
(Figure 6-17). Interrupt request
IRQ5 will be generated if the programmed time interval (deter-
mined by T1 prescaler and counter/timer register initial values)
has elapsed since the last High-to-Low transition on T
IN
. In Sin-
gle-Pass Mode, the end-of-count resets the Enable Count bit.
Subsequent T
IN
transitions will not cause T1 to load and start
counting until software sets the Enable Count bit again. In Con-
tinuous Mode, counting continues once T1 is triggered until soft-
ware resets the Enable Count bit. When enabled, each High-to-
Low T
IN
transition causes T1 to reload and restart counting. In-
terrupt request IRQ5 is generated on every end-of-count.
6.6 CASCADING COUNTER/TIMERS
For some applications, it may be necessary to measure a time in-
terval greater than a single counter/timer can measure. In this
case, T
IN
and T
OUT
can be used to cascade T0 and T1 as a single
unit (Figure 6-18). T0 should be configured to operate in Contin-
uous mode and to drive T
OUT
. T
IN
should be configured as an ex-
ternal clock input to T1 and wired back to T
OUT
. On every other
T0 end-of-count, T
OUT
undergoes a High-to-Low transition that
causes T1 to count.
T1 can operate in either Single-Pass or Continuous mode. When
the T1 end-of-count is reached, interrupt request IRQ5 is gener-
ated. Interrupt requests IRQ2 (T
IN
High-to-Low transitions) and
IRQ4 (T0 end-of-count) are also generated but are most likely of
no importance in this configuration and should be disabled.
Figure 6-18. Cascaded Counter / Timers
OSC
2
4
PRE0
T0
2
PRE1
IRQ
2
P3
1
P3
6
T1
IRQ
4
T
OUT
T
IN
IRQ
5
Z8 Microcontrollers
Counter/Timers
ZiLOG
6-12
UM001601-0803
6.7 RESET CONDITIONS
After a hardware reset, the counter/timers are disabled and the
contents of the counter/timer and prescaler registers are unde-
fined. However, the counting modes are configured for Single-
Pass and the T1 clock source is set for external.
T
IN
is set for External Clock mode, and the T
OUT
mode is off.
Figures 6-19 through 6-22 show the binary reset values of the
Prescaler, Counter/Timer, and Timer Mode registers.
Figure 6-19. Counter / Timer Reset
Figure 6-20. Prescaler 1 Register Reset
U U U U U U U U
(%F4; Write/Read Only)
current value when read
Initial value when written
(Range 1-256 decimal, 01-00 HEX)
Counter/Timer 0 Register
R244 T0
(%F2; Write/Read Only)
Counter/Timer 1 Register
R242 T1
U U U U U U 0 0
(%F3; Write-Only)
1 = T
1
Modulo-n
Count Mode
0 = T
1
Single Pass
Prescaler 1 Register
R243 PRE1
01-00 HEX)
Prescaler Modulo
(Range: 1-64 Decimal
Clock Source
0 = T
1
External (T
IN
)
1 = T
1
Internal
Figure 6-21. Prescaler 0 Reset
Figure 6-22. Timer Mode Register Reset
U U U U U U U 0
(%F5; Write-Only)
1 = T
0
Modulo-n
Count Mode
0 = T
0
Single Pass
Prescaler 0 Register
R245 PRE0
01-00 HEX)
Prescaler Modulo
(Range: 1-64 Decimal
Reserved (Must be 0)
0 0 0 0 0 0 0 0
(% F1; Read/Write)
0 = Disable T
0
Count
0 = No Function
1 = Load T
0
Timer Mode Register
R241 TMR
1 = Enable T
0
Count
(Retriggerable)
T
OUT
Modes:

(Non-retriggerable)
Trigger Input = 10
T
IN
= Modes:
External Clock Input = 00
Gate Input = 01
0 = No Function
1 = Load T
1
0 = Disable T
1
Count
1 = Enable T
1
Count
T
OUT
OFF = 00
T
0
OUT = 01
T
1
OUT = 10
Internal Clock OUT = 11
Trigger Input = 11
UM001601-0803
7-1
U
SER
'
S
M
ANUAL
C
HAPTER
7
I
NTERRUPTS
7.1 INTRODUCTION
The Z8 MCU
allows 6 different interrupts from a variety of
sources; up to four external inputs, the on-chip Counter/Tim-
er(s), software, and serial I/O peripherals. These interrupts can
be masked and their priorities set by using the Interrupt Mask
and the Interrupt Priority Registers. All six interrupts can be glo-
bally disabled by resetting the master Interrupt Enable, bit 7 in
the Interrupt Mask Register, with a Disable Interrupt (DI) in-
struction. Interrupts are globally enabled by setting bit 7 with an
Enable Interrupt (EI) instruction.
There are three interrupt control registers: the Interrupt Request
Register (IRQ), the Interrupt Mask register (IMR), and the Inter-
rupt Priority Register (IPR). Figure 7-1 shows addresses and
identifiers for the interrupt control registers. Figure 7-2 is a block
diagram showing the Interrupt Mask and Interrupt Priority logic.
The Z8 MCU family supports both vectored and polled interrupt
handling. Details on vectored and polled interrupts can be found
later in this chapter.
Note: See the selected Z8 MCU's product specification for the
exact interrupt sources supported.
Figure 7-1. Interrupt Control Registers
Register
HEX
Interrupt Mask
Interrupt Request
Interrupt Priority
Identifier
FBH
FAH
F9H
IMR
IRQ
IPR
Figure 7-2. Interrupt Block Diagram
IRQ
IRQ
0
- IRQ
5
Vector Select
Interrupt
Request
IMR
IPR
Priority Logic
6
Global
Interrupt
Enable
6
Z8 Microcontrollers
Interrupts
ZiLOG
7-2
UM001601-0803
7.2 INTERRUPT SOURCES
Table 7-1 presents the interrupt types, sources, and vectors available in the Z8 family of processors.
7.2.1 External Interrupt Sources
External sources involve interrupt request lines IRQ0-IRQ3.
IRQ0, IRQ1, and IRQ2 can be generated by a transition on the
corresponding Port 3 pin (P32, P33, and P31 correspond to
IRQ0, IRQ1, and IRQ2, respectively).
Figure 7-3 is a block diagram for interrupt sources IRQ0, IRQ1,
and IRQ2.
Note: The interrupt sources and trigger conditions are device
dependent. See the device product specification to determine
available sources (internal and external), triggering edge
options, and exact programming details.
Table 7-1. Interrupt Types, Sources, and Vectors *
Name
Sources
Vector Location
Comments
IRQ
0
DAV
0
, IRQ
0
, Comparator
0,1
External (P3
2
), Edge Triggered; Internal
IRQ
1
DAV
1
, IRQ
1
2,3
External (P3
3
), Edge Triggered; Internal
IRQ
2
DAV
2
, IRQ
2
, TIN, Comparator
4,5
External (P3
1
), Edge Triggered; Internal
IRQ
3
6,7
External (P3
0
) or (P3
2
), Edge Triggered;
Internal
Serial In
6,7
Internal
T
0
8,9
Internal
Serial Out
8,9
Internal
IRQ
5
T
1
10,11
Internal
Figure 7-3. Interrupt Sources IRQ0-IRQ2 Block Diagram
P3
n
IRQ
m
System Clock
Multiple Input
n = 2, 3, 1
and Signal
Q
S
R
Conditioning
Circuitry
m = 0,1,2
(Internal)
Q
D
Q
D
Z8 Microcontrollers
ZiLOG
Interrupts
UM001601-0803
7-3
When the Port 3 pin (P31, P32, or P33) transitions, the first flip-
flop is set. The next two flip-flops synchronize the request to the
internal clock and delay it by two internal clock periods. The
output of the last flip-flop (IRQ0, IRQ1, or IRQ2) goes to the
corresponding Interrupt Request Register.
IRQ3 can be generated from an external source only if Serial In
is not enabled. Otherwise, its source is internal. The external re-
quest is generated by a Low edge signal on P30 as shown in Fig-
ure 7-4. Again, the external request is synchronized and delayed
before reaching IRQ3. Some Z8 products replace P30 with P32
as the external source for IRQ3. In this case, IRQ3 interrupt gen-
eration follows the logic as illustrated in Figure 7-3.
Note: Although interrupts are edge triggered, minimum
interrupt request Low and High times must be observed for
proper operation. See the device product specification for exact
timing requirements on external interrupt requests (T
W
IL,
T
W
IH).
7.2.2 Internal Interrupt Sources
Internal sources involve interrupt requests IRQ0, IRQ2, IRQ3,
IRQ4, and IRQ5. Internal sources are ORed with the external
sources, so either an internal or external source can trigger the
interrupt. Internal interrupt sources and trigger conditions are
device dependent.
See the device product specification to determine available
sources, triggering edge options, and exact programming details.
For more details on the internal interrupt sources, refer to the
chapters describing the Counter/Timer, I/O ports, and Serial I/O.
Figure 7-4. Interrupt Source IRQ3 Block Diagram
Q
PIN
D
Serial Receiver
P3M
6
IRQ
3
Clock
IRQ
3
IRQ
3
External Source
(IRQ
3
Serial In)
Internal Source
D
Q
Z8 Microcontrollers
Interrupts
ZiLOG
7-4
UM001601-0803
7.3 INTERRUPT REQUEST REGISTER LOGIC AND TIMING
Figure 7-5 shows the logic diagram for the Interrupt Request
(IRQ) Register. The leading edge of the request will set the first
flip-flop, that will remain set until interrupt requests are sam-
pled.
Requests are sampled internally during the last clock cycle be-
fore an opcode fetch (Figure 7-6). External requests are sampled
two internal clocks earlier, due to the synchronizing flip-flops
shown in Figures 7-3 and 7-4.
At sample time the request is transferred to the second flip-flop
in Figure 7-5, that drives the interrupt mask and priority logic.
When an interrupt cycle occurs, this flip-flop will be reset only
for the highest priority level that is enabled.
The user has direct access to the second flip-flop by reading and
writing the IRQ Register. IRQ is read by specifying it as the
source register of an instruction and written by specifying it as
the destination register.
Figure 7-5. IRQ Register Logic
Q
S
From
To Mask
IRQ
0
- IRQ
5
R
Q
R
Priority
Logic
and
Priority
Logic
Sample
Clock
Figure 7-6. Interrupt Request Timing
T1 T2 T3 T1 T2 T3 T1 T2 T3
External Interrupt
Interrupt Request
Sampled Internally
Request Sampled
Mn M1 M2
Z8 Microcontrollers
ZiLOG
Interrupts
UM001601-0803
7-5
7.4 INTERRUPT INITIALIZATION
After reset, all interrupts are disabled and must be initialized be-
fore vectored or polled interrupt processing can begin. The Inter-
rupt Priority Register (IPR), Interrupt Mask Register (IMR), and
Interrupt Request Register (IRQ) must be initialized, in that or-
der, to start the interrupt process.
7.4.1 Interrupt Priority Register (IPR) Initializa-
tion
IPR (Figure 7-7) is a write-only register that sets priorities for the
vectored interrupts in order to resolve simultaneous interrupt re-
quests. (There are 48 sequence possibilities for interrupts.) The
six interrupt levels IRQ0-IRQ5 are divided into three groups of
two interrupt requests each. One group contains IRQ3 and IRQ5.
The second group contains IRQ0 and IRQ2, while the third
group contains IRQ1 and IRQ4.
Priorities can be set both within and between groups as shown in
Tables 7-2 and 7-3. Bits 1, 2, and 5 define the priority of the in-
dividual members within the three groups. Bits 0, 3, and 4 are en-
coded to define six priority orders between the three groups. Bits
6 and 7 are reserved.
Figure 7-7. Interrupt Priority Register
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Interrupt Priority Register (IPR)
Register F9H
Interrupt Group Priority
Bits Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
0 = IRQ1 > IRQ4
1 = IRQ4 > IRQ1
Group C (IRQ1 and IRQ4 Priority)
Reserved (Must be 0)
0 = IRQ2 > IRQ0
1 = IRQ0 > IRQ2
Group B (IRQ0 and IRQ2 Priority)
0 = IRQ5 > IRQ3
1 = IRQ3 > IRQ5
Group A (IRQ3 and IRQ5 Priority)
Table 7-2. Interrupt Priority
Priority
Group
Bit
Value
Highest
Lowest
C
Bit 1
0
IRQ1
IRQ4
1
IRQ4
IRQ1
B
Bit 2
0
IRQ2
IRQ0
1
IRQ0
IRQ2
A
Bit 5
0
IRQ5
IRQ3
1
IRQ3
IRQ5
Table 7-3. Interrupt Group Priority
Bit Pattern
Group Priority
Bit 4
Bit 3
Bit 0
High
Medium
Low
0
0
0
Not Used
0
0
1
C
A
B
0
1
0
A
B
C
0
1
1
A
C
B
1
0
0
B
C
A
1
0
1
C
B
A
1
1
0
B
A
C
1
1
1
Not Used
Z8 Microcontrollers
Interrupts
ZiLOG
7-6
UM001601-0803
7.4 INTERRUPT INITIALIZATION
(Continued)
7.4.2 Interrupt Mask Register (IMR) Initialization
IMR individually or globally enables or disables the six interrupt
requests (Figure 7-8). When bit 0 to bit 5 are set to 1, the corre-
sponding interrupt requests are enabled. Bit 7 is the master en-
able and must be set before any of the individual interrupt re-
quests can be recognized. Resetting bit 7 globally disables all the
interrupt requests. Bit 7 is set and reset by the EI and DI instruc-
tions. It is automatically reset during an interrupt service routine
and set following the execution of an Interrupt Return (IRET) in-
struction.
Note: Bit 7 must be reset by the DI instruction before the
contents of the Interrupt Mask Register or the Interrupt Priority
Register are changed except:
Immediately after a hardware reset.
Immediately after executing an interrupt service routine and
before IMR bit 7 has been set by any instruction.
Note: The RAM Protect option is selected at ROM mask
submission time or at EPROM program time. If not selected or
not an available option, this bit is reserved and must be 0.
Figure 7-8. Interrupt Mask Register
D7 D6 D5 D4 D3 D2 D1 D0
(Read/Write)
Interrupt Request Register (IMR)
Register FBH
0 = Disables IRQ0
1 = Enables IRQ0
0 = Disables IRQ1
1 = Enables IRQ1
0 = Disables IRQ2
1 = Enables IRQ2
0 = Disables IRQ3
1 = Enables IRQ3
0 = Disables IRQ4
1 = Enables IRQ4
0 = Disables IRQ5
1 = Enables IRQ5
0 = Disables RAM Protect
1 = Enables RAM Protect
0 = Disables Interrupt
1 = Enables Interrupt
Z8 Microcontrollers
ZiLOG
Interrupts
UM001601-0803
7-7
7.4.3 Interrupt Request (IRQ) Register Initialization
IRQ (Figure 7-9) is a read/write register that stores the interrupt
requests for both vectored and polled interrupts. When an inter-
rupt is made on any of the six, the corresponding bit position in
the register is set to 1. Bit 0 to bit 5 are assigned to interrupt re-
quests IRQ0 to IRQ5, respectively.
Whenever Power-On Reset (POR) is executed, the IRQ resister
is reset to 00H and disabled. Before the IRQ register will accept
requests, it must be enabled by executing an ENABLE INTER-
RUPTS (EI) instruction.
Note: Setting the Global Interrupt Enable bit in the Interrupt
Mask Register (IMR, bit 7) will not enable the IRQ. Execution
of the EI instruction is required (Figure 7-10).
For polled processing, IRQ must still be initialized by an EI in-
struction.
To properly initialize the IRQ register, the following code is pro-
vided:
Note: IRQ is always cleared to 00Hex and is read only until the
1st EI instruction which enables the IRQ to be read/write.
CLR
IMR
//make sure disabled vectored interrupts
EI
//enable IRQ register otherwise read only.
//not needed if interrupts were previously
enabled.
DI
//disable interrupt heading.
Figure 7-9. Interrupt Request Register
D7 D6 D5 D4 D3 D2 D1 D0
(Read/Write)
Reserved /Int Edge Select
Interrupt Request Register (IRQ)
Register FAH
0 = IRQ0 RESET
1 = IRQ0 SET
0 = IRQ1 RESET
1 = IRQ1 SET
0 = IRQ2 RESET
1 = IRQ2 SET
0 = IRQ3 RESET
1 = IRQ3 SET
0 = IRQ4 RESET
1 = IRQ4 SET
0 = IRQ5 RESET
1 = IRQ5 SET
Z8 Microcontrollers
Interrupts
ZiLOG
7-8
UM001601-0803
7.4 INTERRUPT INITIALIZATION
(Continued)
IMR is cleared before the IRQ enabling sequence to insure no
unexpected interrupts occur when EI is executed. This code se-
quence should be executed prior to programming the application
required values for IPR and IMR.
Note: IRQ bits 6 and 7 are device dependent. When reserved,
the bits are not used and will return a 0 when read. When used as
the Interrupt Edge select bits, the configuration options are as
show in Table 7-4.
The proper sequence for programming the interrupt edge select
bits is (assumes IPR and IMR have been previously initialized):
Table 7-4. IRQ Register Configuration
IRQ
Interrupt Edge
D7
D6
P31
P32
0
0
F
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
DI
;Inhibit all interrupts
until input edges are
configured
OR
IRQ,#XX 000000B
;Configure interrupt
do not disturb
edges as needed -
IRQ 0-5.
EI
;Re-enable interrupts.
Figure 7-10. IRQ Reset Functional Logic Diagram
S
Interrupt Request Register
(IRQ, FAH)
RESET
El Instruction
POR
R
Z8 Microcontrollers
ZiLOG
Interrupts
UM001601-0803
7-9
7.5 IRQ SOFTWARE INTERRUPT GENERATION
IRQ can be used to generate software interrupts by specifying
IRQ as the destination of any instruction referencing the Z8
Standard Register File. These Software Interrupts (SWI) are
controlled in the same manner as hardware generated requests
(in other words, the IPR and the IMR control the priority and en-
abling of each SWI level).
To generate a SWI, the desired request bit in the IRQ is set as fol-
lows:
where the immediate data, NUMBER, has a 1 in the bit position
corresponding to the level of the SWI desired. For example, if an
SWI is desired on IRQ5, NUMBER would have a 1 in bit 5:
With this instruction, if the interrupt system is globally enabled,
IRQ5 is enabled, and there are no higher priority pending re-
quests, control is transferred to the service routine pointed to by
the IRQ5 vector.
7.6 VECTORED PROCESSING
Each Z8 interrupt level has its own vector. When an interrupt oc-
curs, control passes to the service routine pointed to by the inter-
rupt's vector location in program memory. The sequence of
events for vectored interrupts is as follows:
PUSH PC Low Byte on Stack
PUSH PC High Byte on Stack
PUSH FLAGS on Stack
Fetch High Byte of Vector
Fetch Low Byte of Vector
Branch to Service Routine specified by Vector
Figures 7-11 and 7-12 show the vectored interrupt operation.
ORIRQ,
#NUMBER
OR
IRQ, #00100000B
Figure 7-11. Effects of an Interrupt on the STACK
SP
Top of Stack
PC LOW Byte
PC HIGH Byte
FLAGS
SP and Stack after an interrupt
SP
SP and Stack before an interrupt
Z8 Microcontrollers
Interrupts
ZiLOG
7-10
UM001601-0803
7.6 VECTORED PROCESSING
(Continued)
Figure 7-12. Interrupt Vectoring
PC HIGH Byte
FLAGS
Vector Selected
000CH
Program Memory
Interrupt
Service
Routine
By Priority Logic
Interrupt
Vector Table
0000H
XXFFH
Z8 Microcontrollers
ZiLOG
Interrupts
UM001601-0803
7-11
7.6.1 Vectored Interrupt Cycle Timing
The interrupt acknowledge cycle time is 24 internal clock cycles
and is shown in Figure 7-13. In addition, two internal clock cy-
cles are required for the synchronizing flip-flops. The maximum
interrupt recognition time is equal to the number of clock cycles
required for the longest executing instruction present in the user
program (assumes worst case condition of interrupt sampling,
Figure 7-6, just prior to the interrupt occurrence). To calculate
the worst case interrupt latency (maximum time required from
interrupt generation to fetch of the first instruction of the inter-
rupt service routine), sum these components:
Worst Case Interrupt Latency
24 INT CLK (interrupt acknowl-
edge time) + # T
P
C of longest instruction present in the user's ap-
plication program + 2T
P
C (internal synchronization time).
Figure 7-13. Z8 Interrupt Acknowledge Timing
PC
For Stack External Only
PC+1
PC
PCL
SP-1
SP-2
PCH
SP-3 FLAGS
VECT
VECT+1
Even Vector Address
Odd Vector Address
Op Code (Discarded)
VECTH
VECTL
First Instruction Of Interrupt Service Routine
For Stack External Only
A0-A7 IN
Internal Clock
/AS
/DS
A0-A7 OUT
M3
M1
M2
M1
M2
Stack Push
Fetch
Vector High
Fetch
Vector Low
Stack Push
Stack Push
R/W
Z8 Microcontrollers
Interrupts
ZiLOG
7-12
UM001601-0803
7.6.2 Nesting of Vectored Interrupts
Nesting of vectored interrupts allows higher priority requests to
interrupt a lower priority request. To initiate vectored interrupt
nesting, do the following during the interrupt service routine:
Push the old IMR on the stack.
Load IMR with a new mask to disable lower priority
interrupts.
Execute EI instruction.
Proceed with interrupt processing.
After processing is complete, execute DI instruction.
Restore the IMR to its original value by returning the previous
mask from the stack.
Execute IRET.
Depending on the application, some simplification of the above
procedure may be possible.
7.7 POLLED PROCESSING
Polled interrupt processing is supported by masking off the IRQ
to be polled. This is accomplished by clearing the corresponding
bits in the IMR.
To enable any interrupt, first the interrupt mechanism must be
engaged with an EI instruction. If only polled interrupts are to
be serviced, execute:
EI ;Enable interrupt mechanism
DI ;Disable vectored interrupts.
To initiate polled processing, check the bits of interest in the IRQ
using the Test Under Mask (TM) instruction. If the bit is set, call
or branch to the service routine. The service routine services the
request, resets its Request Bit in the IRQ, and branches or returns
back to the main program. An example of a polling routine is as
follows:
In this example, if IRQ2 is being polled, MASKA will be
00000100B and MASKB will be 11111011B.
7.8 RESET CONDITIONS
Upon reset, all bits in IPR are undefined.
In IMR, bit 7 is 0 and bits 0-6 are undefined. The IRQ register is
reset and held in that state until an enable interrupt (EI) instruc-
tion is executed.
TM IRQ, #MASKA
;Test for request
JR Z, NEXT
;If no request go to NEXT
CALL SERVICE
;If request is there, then
;service it
NEXT:
.
.
.
SERVICE:
;Process Request
.
.
.
AND IRQ, #MASKB
;Clear Request Bit
RET
;Return to next
UM001601-0803
8-1
U
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S
M
ANUAL
C
HAPTER
8
P
OWER
-D
OWN
M
ODES
8.1 INTRODUCTION
In addition to the standard RUN mode, the Z8 MCU
supports
two Power-Down modes to minimize device current consump-
tion. The two modes supported are HALT and STOP.
8.2 HALT MODE OPERATION
The HALT mode suspends instruction execution and turns off
the internal CPU clock. The on-chip oscillator circuit remains ac-
tive so the internal clock continues to run and is applied to the
Counter/Timer(s) and interrupt logic.
To enter the HALT mode, it is necessary to first flush the instruc-
tion pipeline to avoid suspending execution in mid-instruction.
To do this, the application program must execute a NOP instruc-
tion (opcode = FFH) immediately before the HALT instruction
(opcode 7FH), that is,
The HALT mode is exited by interrupts, either externally or in-
ternally generated. Upon completion of the interrupt service rou-
tine, the user program continues from the instruction after
HALT.
The HALT mode may also be exited via a POR/RESET activa-
tion or a Watch-Dog Timer (WDT) timeout. (See the product
data sheet for WDT availability). In this case, program execution
will restart at the reset restart address 000CH.
To further reduce power consumption in the HALT mode, some
Z8 family devices allow dynamic internal clock scaling. Clock
scaling may be accomplished on the fly by reprogramming bit 0
and/or bit1 of the STOP-Mode Recovery register (SMR). See
Figure 8-1.
Note: Internal clock scaling directly effects Counter/Timer
operation -- adjustment of the prescaler and downcounter values
may be required. To determine the actual HALT mode current
(I
CC1
) value for the various optional modes available, see the
related Z8
device's product specification.
FF
NOP
;clear the instruction pipeline
7F
HALT
;enter HALT mode
Z8 Microcontrollers
Power-Down Modes
ZiLOG
8-2
UM001601-0803
8.3 STOP MODE OPERATION
The STOP mode provides the lowest possible device standby
current. This instruction turns off the on-chip oscillator and in-
ternal system clock.
To enter the STOP mode, it is necessary to first flush the instruc-
tion pipeline to avoid suspending execution in mid-instruction.
To do this, the application program must execute a NOP instruc-
tion (opcode=FFH) immediately before the STOP instruction
(opcode=6FH), that is,
The STOP mode is exited by any one of the following resets:
Power-On Reset activation, WDT time out (if available), or a
STOP-Mode Recovery source. Upon reset generation, the pro-
cessor will always restart the application program at address
000CH.
POR/RESET activation is present on all Z8 devices and is imple-
mented as a reset pin and/or an on-chip power on reset circuit.
Some Z8 devices allow for the on-chip WDT to run in the STOP
mode. If so activated, the WDT timeout will generate a reset
some fixed time period after entering the STOP mode.
Note: STOP-Mode Recovery by the WDT will increase the
STOP mode standby current (I
CC2
). This is due to the WDT
clock and divider circuitry that is now enabled and running to
support this recovery mode. See the product data sheet for actual
I
CC2
values.
All Z8 devices provide some form of dedicated STOP-Mode Re-
covery (SMR) circuitry. Two SMR methods are implemented --
a single fixed input pin or a flexible, programmable set of inputs.
The selected Z8 device product specification should be reviewed
to determine the SMR options available for use.
Note: For devices that support SPI, the slave mode compare
feature also serves as a SMR source.
In the simple case, a low level applied to input pin P27 will trig-
ger a SMR. To use this mode, pin P27 (I/O Port 2, bit 7) must be
configured as an input before the STOP mode is entered. The
low level on P27 must meet a minimum pulse width T
WSM
. (See
the product data sheet) to trigger the device reset mode). Some
Z8 devices provide multiple SMR input sources. The desired
SMR source is selected via the SMR Register.
Note: Use of specialized SMR modes (P2.7 input or SMR
register based) or the WDT timeout (only when in the STOP
mode) provide a unique reset operation. Some control registers
are initialized differently for a SMR/WDT triggered POR than a
standard reset operation. See the product specification (register
file map) for exact details.
To determine the actual STOP mode current (I
CC2
) value for the
optional SMR modes available, see the selected Z8 device's
product data sheet.
Note: The STOP mode current (I
CC2
) will be minimized when:
V
CC
is at the low end of the devices operating range.
WDT is off in the STOP mode.
Output current sourcing is minimized.
All inputs (digital and analog) are at the low or high rail
voltages.
FF
NOP
;clear the instruction pipeline
6F
STOP
;enter STOP mode
Z8 Microcontrollers
ZiLOG
Power-Down Modes
UM001601-0803
8-3
8.4 STOP-MODE RECOVERY REGISTER
This register selects the clock divide value and determines the
mode of STOP-Mode Recovery (Figure 8-1). All bits are Write-
Only, except bit 7, that is Read-Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP recovery and reset by a
power-on cycle. Bit 6 controls whether a low level or a high level
is required from the recovery source. Bit 5 controls the reset de-
lay after recovery. Bits 2, 3, and 4, of the SMR register, specify
the source of the STOP-Mode Recovery signal. Bits 0 and 1 con-
trol internal clock divider circuitry. The SMR is located in Bank
F of the Expanded Register File at address 0BH.
Note: The SMR register is available in select Z8 MCU products. Refer to the device product specification to determine SMR options
available.
SCLK/TCLK Divide-by-16 Select (DO). This bit of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The purpose
of this control is to selectively reduce device power consumption
during normal processor execution (SCLK control) and/or
HALT mode (where TCLK sources counter/timers and interrupt
logic).
External Clock Divide-by-Two (D1). This bit can eliminate the
oscillator divide-by-two circuitry. When this bit is 0, the System
Clock (SCLK) and Timer Clock (TCLK) are equal to the exter-
nal clock frequency divided by two. The SCLK/TCLK is equal
to the external clock frequency when this bit is set (D1=1). Using
this bit together with D7 of PCON helps further lower EMI (D7
(PCON) =0, D1 (SMR) =1). The default setting is zero.
Figure 8-1. STOP-Mode Recovery Register
(Write-Only Except Bit D7, Which Is Read-Only)
D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B
STOP-Mode Recovery Source
000 POR Only and/or External Reset
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
0 OFF **
1 ON
SCLK/TCLK Divide-by-16
0 OFF
1 ON*
Stop Delay
0 POR*
1 Stop Recovery
Stop Flag (Read Only)
0 SCLK/TCLK = XTAL/2*
External Clock Divide by 2
0 Low*
1 High
Stop Recovery Level
1 SCLK/TCLK = XTAL
* Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
Z8 Microcontrollers
Power-Down Modes
ZiLOG
8-4
UM001601-0803
8.4 STOP-MODE RECOVERY REGISTER
(Continued)
STOP-Mode Recovery Source (D2, D3, and D4). These three
bits of the SMR specify the wake-up source of the STOP recov-
ery and (Table 8-1 and Figures 8-2).
STOP-Mode Recovery Delay Select (D5). This bit, if High, en-
ables the T
POR
/RESET delay after Stop-Mode Recovery. The
default configuration of this bit is 1. If the "fast" wake up is se-
lected, the Stop-Mode Recovery source is kept active for at least
5 TpC.
STOP-Mode Recovery Edge Select (D6). A 1 in this bit posi-
tion indicates that a high level on any one of the recovery sources
wakes the Z8 from STOP mode. A 0 indicates low-level recov-
ery. The default is 0 on POR (Figure 8-2).
Cold or Warm Start (D7). This bit is set by the device upon en-
tering STOP mode. A 0 in this bit (cold) indicates that the device
reset by POR/WDT RESET. A 1 in this bit (warm) indicates that
the device awakens by a SMR source.
Note: If P31, P32, or P33 are to be used for a SMR source, the digital mode of operation must be selected prior to entering the STOP
Mode.
Table 8-1. STOP-Mode Recovery Source
SMR: 432
Operation
D4
D3
D2 Description of Action
0
0
0
POR and/or external reset recovery
0
0
1
P30 transition
0
1
0
P31 transition (not in Analog Mode)
0
1
1
P32 transition (not in Analog Mode)
1
0
0
P33 transition (not in Analog Mode)
1
0
1
P27 transition
1
1
0
Logical NOR of P20 through P23
1
1
1
Logical NOR of P20 through P27
Figure 8-2. STOP-Mode Recovery Source
SMR D4 D3 D2
0 0 0
SMR D4 D3 D2
0 0 1
0 1 0
0 1 1
SMR D4 D3 D2
1 0 0
SMR D4 D3 D2
1 0 1
SMR D4 D3 D2
1 1 0
SMR D4 D3 D2
1 1 0
V
DD
P20
P23
P20
P27
P30
P33
P27
P31
P32
MUX
To POR
RESET
To P33 Data
Latch and IRQ
1
Stop Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
UM001601-0803
9-1
U
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ANUAL
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9
S
ERIAL
I/O
9.1 UART INTRODUCTION
Select Z8 MCU
microcontrollers contain an on-board full-du-
plex Universal Asynchronous Receiver/Transmitter (UART) for
data communications. The UART consists of a Serial I/O Regis-
ter (SIO) located at address F0H, and its associated control logic
(Figure 9-1). The SIO is actually two registers, the receiver buff-
er and the transmitter buffer, which are used in conjunction with
Counter/Timer T0 and Port 3 I/O lines P30 (input) and P37 (out-
put). Counter/Timer T0 provides the clock input for control of
the data rates.
Figure 9-1. UART Block Diagram
Stop
Bit Detect
Transmitter
Shift Register
6
Parity
Gan
Serial
Out
Char
Detect
Receiver
Buffer
Receiver
Shift Register
Serial
In
Start
Bit Detect
Clock
Control
Parity
Check
Shift
Clock
Shift
Clock
16
Transfer
Stop
Start
Write FOH
RESET
Read FOH
Mark
Serial I/O Clock (From T0)
IRQ
4
Internal Data Bus
IRQ
3
P3
7
P3
0
Z8 Microcontrollers
Serial I/O
ZiLOG
9-2
UM001601-0803
Configuration of the UART is controlled by the Port 3 Mode
Register (P3M) located at address F7H. The Z8 always transmits
eight bits between the start and stop bits (eight Data Bits or seven
Data Bits and one Parity Bit). Odd parity generation and detec-
tion is supported.
The SIO Register and its associated Mode Control Registers are
mapped into the Standard Z8 Register File as shown in Table 9-
1. The organization allows the software to access the UART as
general-purpose registers, eliminating the need for special in-
structions.
9.2 UART BIT-RATE GENERATION
When Port 3 Mode Register bit 6 is set to 1, the UART is enabled
and T0 automatically becomes the bit rate generator (Figure 9-
2). The end-of-count signal of T0 no longer generates Interrupt
Request IRQ4. Instead, the signal is used as the input to the di-
vide-by-16 counters (one each for the receiver and the transmit-
ter) that clock the data stream.
The divide chain that generates the bit rate is shown in Figure 9-
3. The bit rate is given by the following equation:
Bit Rate = XTAL Frequency/(2 x 4 x p x t x 16)
where p and t are the initial values in Prescaler0 and
Counter/Timer0, respectively. The final divide-by-16 is required
since T0 runs at 16 times the bit rate in order to synchronize on
the incoming data.
To configure the Z8 for a specific bit rate, appropriate values as
determined by the above equation must be loaded into registers
PRE0
(F5H) and T0 (F4H). PRE0 also controls the counting mode for
T0 and should therefore be set to the Continuous Mode (D0 = 1).
Table 9-1. UART Register Map
Register
Hex
Name
Identifier
Address
Port 3 Mode
P3M
F7
T0 Prescaler
PRE0
F5
Timer/Counter0
T0
F4
Timer Mode
TMR
F1
UART
SIO
F0
Figure 9-2. Port 3 Mode Register (P3M) and Bit-Rate Generation
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 3 Mode Register (P3M)
Register F7H
0 P30 Input and P37 = Output
1 P30 Serial In and P37 = Serial Out
Figure 9-3. Bit Rate Divide Chain
P
t
16
Bit Rate
4
2
Clock
PRE0
T0
f
XTAL
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-3
For example, given an input clock frequency (XTAL) of
11.9808 MHz and a selected bit rate of 1200 bits per second, the
equation is satisfied by p = 39 and t = 2. Counter/Timer T0
should be set to 02H. With T0 in Continuous Mode, the value of
PRE0 becomes 9DH (Figure 9-4).
Table 9-2 lists several commonly used bit rates and the values of
XTAL, p, and t required to derive them. This list is presented for
convenience and is not intended to be exhaustive.
Table 9-2. Bit Rates
Bit
7,3728
7,9872
9,8304
11,0592
11,6736
11,9808
12,2880
Rate
p
t
p
t
p
t
p
t
p
t
p
t
p
t
19200
3
1
4
1
5
1
9600
3
2
4
2
9
1
5
2
4800
3
4
13
1
4
4
9
2
19
1
5
4
2400
3
8
13
2
4
8
9
4
19
2
39
1
5
8
1200
3
16
13
4
4
16
9
8
19
4
39
2
5
16
600
3
32
13
8
4
32
9
16
19
8
39
4
5
32
300
3
64
13
16
4
64
9
32
19
16
39
8
5
64
150
3
128
13
32
4
128
9
64
19
32
39
16
5
128
110
3
175
3
189
4
175
5
157
4
207
17
50
8
109
Figure 9-4. Prescaler 0 Register (PRE0) Bit-Rate Generation
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Prescalar 0 Register (PRE0)
Register F5H
Count Mode
0 = T
0
Single Pass
(Range: 1-64 decimal, 01H-00H)
(Range: 1-64)
1 = T
0
Modulo-n
Z8 Microcontrollers
Serial I/O
ZiLOG
9-4
UM001601-0803
The bit rate generator is started by setting the Timer Mode Reg-
ister (TMR) (F1H) bit 1 and bit 0 both to 1 (Figure 9-5). This
transfers the contents of the Prescaler 0 Register and
Counter/Timer0 Register to their corresponding down counters.
In addition, counting is enabled so that UART operations begin.
9.3 UART RECEIVER OPERATION
The receiver consists of a receiver buffer (SIO Register [F0H]),
a serial-in, parallel-out shift register, parity checking, and data
synchronizing logic. The receiver block diagram is shown as
part of Figure 9-1.
9.3.1 Receiver Shift Register
After a hardware reset or after a character has been received, the
Receiver Shift Register is initialized to all 1s and the shift clock
is stopped. Serial data, input through Port 3 bit 0, is synchronized
to the internal clock by two D-type flip-flops before being input
to the Shift Register and the start bit detection circuitry.
The start bit detection circuitry monitors the incoming data
stream, looking for a start bit (a High-to-Low input transition).
When a start bit is detected, the shift clock logic is enabled. The
T0 input is divided-by-16 and, when the count equals eight, the
divider outputs a shift clock. This clock shifts the start bit into
the Receiver Shift Register at the center of the bit time. Before
the shift actually occurs, the input is rechecked to ensure that the
start bit is valid. If the detected start bit is false, the receiver is
reset and the process of looking for a start bit is repeated. If the
start bit is valid, the data is shifted into the Shift Register every
sixteen counts until a full character is assembled (Figure 9-6).
Figure 9-5. Timer Mode Register (TMR) Bit Rate Generation
D7 D6 D5 D4 D3 D2 D1 D0
(Read/Write)
0 = No Function
1 = Load T
0
Timer Mode Register (TMR)
Register F1H
0 = Disable T
0
Count
1 = Enable T
0
Count
Figure 9-6. Receiver Timing
Shift register Contents
(R)
Shift
RCVR
Start Bit Transition Detected
Eight T0 Counts Later Shifting Starts
Stop Bit
One or More
Transferred to Receive Buffer
and IRQ3 is Generated
RCVR
Data
Clock
IRQ3
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-5
After a full character has been assembled in the receiver's buffer,
SIO Register (F0H), Interrupt Request IRQ3 is generated. The
shift clock is stopped and the Shift Register reset to all 1s. The
start bit detection circuitry begins monitoring the data input for
the next start bit. This cycle allows the receiver to synchronize
on the center of the bit time for each incoming character.
9.3.2 Overwrites
Although the receiver is single buffered, it is not protected from
being overwritten, so the software must read the SIO Register
(F0H) within one character time after the interrupt request
(IRQ3). The Z8 does not have a flag to indicate this overrun con-
dition. If polling is used, the IRQ3 bit in the Interrupt Request
Register must be reset by software.
9.3.3 Framing Errors
Framing error detection is not supported by the receiver hard-
ware, but by responding to the interrupt request within one char-
acter bit time, the software can test for a stop bit on P30. Port 3
bits are always readable, which facilitates break detection. For
example, if a null character is received, testing P30 results in a 0
being read.
9.3.4 Parity
The data format supported by the receiver must have a start bit,
eight data bits, and at least one stop bit. If parity is on, bit 7 of
the data received will be replaced by a Parity Error Flag. A parity
error sets bit 7 to 1, otherwise, bit D7 is set to 0. Figure 9-7 shows
these data formats.
The Z8
hardware supports odd parity only, that is enabled by
setting the Port 3 Mode Register bit 7 to 1 (Figure 9-8). If even
parity is required, the Parity Mode should be disabled (P3M bit
7 set to 0), and software must calculate the received data's parity.
Figure 9-7. Receiver Data Formats
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Eight Data Bits
Start Bit
Start Bit
Seven Data Bits
One Stop Bit
SP P D6 D5 D4 D3 D2 D1 D0 ST
Parity Error Flag
One Stop Bit
Received Data
(No Parity)
Received Data
(With Parity)
Figure 9-8. Port 3 Mode Register (P3M) Parity
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
0 = Parity OFF
1 = Parity ON
Port 3 Mode Register (P3M)
Register F7H
Z8 Microcontrollers
Serial I/O
ZiLOG
9-6
UM001601-0803
9.4 TRANSMITTER OPERATION
The transmitter consists of a transmitter buffer (SIO Register
[F0H]), a parity generator, and associated control logic. The
transmitter block diagram is shown as part of Figure 9-1.
After a hardware reset or after a character has been transmitted,
the transmitter is forced to a marking state (output always High)
until a character is loaded into the transmitter buffer, SIO Regis-
ter (F0H). The transmitter is loaded by specifying the SIO Reg-
ister as the destination register of any instruction.
T0's output drives a divide-by-16 counter that in turn generates
a shift clock every 16 counts. This counter is reset when the
transmitter buffer is written by an instruction. This reset syn-
chronizes the shift clock to the software. The transmitter then
outputs one bit per shift clock, through Port 3 bit 7, until a start
bit, the character written to the buffer, and two stop bits have
been transmitted. After the second stop bit has been transmitted,
the output is again forced to a marking state. Interrupt request
IRQ4 is generated at this time to notify the processor that the
transmitter is ready to accept another character.
9.4.1 Overwrites
The user is not protected from overwriting the transmitter, so it
is up to the software to respond to IRQ4 appropriately. If polling
is used, the IRQ4 bit in the Interrupt Request Register must be
reset.
9.4.2 Parity
The data format supported by the transmitter has a start bit, eight
data bits, and at least two stop bits. If parity is on, bit 7 of the data
transmitted will be replaced by an odd parity bit. Figure 9-9
shows the transmitter data formats.
Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If
even parity is required, the parity mode should be disabled (P3M
bit 7 reset to 0), and software must modify the data to include
even parity.
Since the transmitter can be overwritten, the user is able to gen-
erate a break signal. This is done by writing null characters to the
transmitter buffer (SIO Register [F0H]) at a rate that does not al-
low the stop bits to be output. Each time the SIO Register is load-
ed, the divide-by-16 counter is resynchronized and a new start
bit is output followed by data.
Figure 9-9. Transmitter Data Formats
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Eight Data Bits
Start Bit
Start Bit
Seven Data Bits
Two Stop Bit
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Odd Parity
Two Stop Bit
Transmitted Data
(No Parity)
Transmitted Data
(With Parity)
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-7
9.5 UART RESET CONDITIONS
After a hardware reset, the SIO Register contents are undefined,
and Serial Mode and parity are disabled. Figures 9-10 and 9-11
show the binary reset values of the SIO Register and its associ-
ated mode register P3M.
Figure 9-10. SIO Register Reset
U U U U U U U U
(Read/Write)
Serial Data (D
0
= LSB)
Serial I/O Register (SIO)
Register RF0H
Figure 9-11. P3M Register Reset
0 0 0 0 0 0 0 0
(Write-Only)
0 P32 = Input P35 = Output
1 P32 = DAV0/RDY0 P35 = RDY0/DAV0
0 Port 2 Pull-Ups Open-Drain
1 Port 2 Pull-Ups Active
00 P33 = Input P34 = Output
01 P33 = Input P34 = DM
Port 3 Mode Register (P3M)
Register F7H
10 P33 = Input P34 = DM

11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
0 P31 = Input (T
IN
) P36 = Output (T
OUT
)
1 P32 =
DAV2
/RDY2 P36 = RDY2/DAV2
0 P30 = Input P37 = Output
1 P30 = Serial In P37 = Serial Out
0 Parity ON
1 Parity OFF
Z8 Microcontrollers
Serial I/O
ZiLOG
9-8
UM001601-0803
9.6 SERIAL PERIPHERAL INTERFACE (SPI)
Select Z8 microcontrollers incorporate a serial peripheral inter-
face (SPI) for communication with other microcontrollers and
peripherals. The SPI includes features such as Stop-Mode Re-
covery, Master/Slave selection, and Compare mode. Table 9-3
contains the pin configuration for the SPI feature when it is en-
abled. The SPI consists of four registers: SPI Control Register
(SCON), SPI Compare Register (SCOMP), SPI Receive/Buffer
Register (RxBUF), and SPI Shift Register. SCON is located in
bank (C) of the Expanded Register File at address 02.
The SPI Control Register (SCON) (Figure 9-12), is a read/write
register that controls Master/Slave selection, interrupts, clock
source and phase selection, and error flag. Bit 0 enables/disables
the SPI with the default being SPI disabled. A 1 in this location
will enable the SPI, and a 0 will disable the SPI. Bits 1 and 2 of
the SCON register in Master Mode select the clock rate. The user
may choose whether internal clock is divide-by-2, 4, 8, or 16. In
Slave Mode, Bit 1 of this register flags the user if an overrun of
the RxBUF Register has occurred. The RxCharOverrun flag is
only reset by writing a 0 to this bit. In slave mode, bit 2 of the
Control Register disables the data-out I/O function. If a 1 is writ-
ten to this bit, the data-out pin is released to its original port con-
figuration. If a 0 is written to this bit, the SPI shifts out one bit
for each bit received. Bit 3 of the SCON Register enables the
compare feature of the SPI, with the default being disabled.
When the compare feature is enabled, a comparison of the value
in the SCOMP Register is made with the value in the RxBUF
Register. Bit 4 signals that a receive character is available in the
RxBUF Register.
If the associated IRQ3 is enabled, an interrupt is generated. Bit
5 controls the clock phase of the SPI. A 1 in bit 5 allows for re-
ceiving data on the clock's falling edge and transmitting data on
the clock's rising edge. A 0 allows receiving data on the clock's
rising edge and transmitting on the clock's falling edge. The SPI
clock source is defined in bit 6. A 1 uses Timer0 output for the
SPI clock, and a 0 uses TCLK for clocking the SPI. Finally, bit
7 determines whether the SPI is used as a Master or a Slave. A 1
puts the SPI into Master mode and a 0 puts the SPI into Slave
mode.
Table 9-3. SPI Pin Configuration
Name
Function
Pin Location
DI
Data-In
P20
DO
Data-Out
P27
SS
Slave Select
P35
SK
SPI Clock
P34
Figure 9-12. SPI Control Register (SCON)
D7 D6 D5 D4 D3 D2 D1 D0
SCON (C) 02
CLK Divide (M)
00 TCLK/2
01 TCLK/4
10 TCLK/8
11 TCLK/16
DO SPI Port Enable (S)
0 SPI DO Port Enable
1 Do Port to I/O
0 Disable *
1 Enable
SPI Enable
0 Enable
1 Disable *
Compare Enable
0 Trans/Fall
1 Trans/Rise
Clock Phase
0 Reset
RxCharOverrun (S)
0 Reset
1 Char. Avail
RxCharAvail
1 Overrun
(M) Used with Bit D7 equal to 1
* Default setting after Reset
0 TCLK
1 Timer 0 Output
CLK Source
0 Slave
1 Master
Master Slave
(S) Used with Bit D7 equal to 0
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-9
9.7 SPI OPERATION
The SPI is used in one of two modes: either as system slave, or
as system master. Several of the possible system configurations
are shown in Figure 9-13. In the slave mode, data transfer starts
when the slave select (SS) pin goes active. Data is transferred
into the slave's SPI Shift Register through the DI pin, which has
the same address as the RxBUF Register. After a byte of data has
been received by the SPI Shift Register, a Receive Character
Available (RCA/IRQ3) flag and interrupt is generated. The next
byte of data will be received at this time. The RxBUF Register
must be cleared, or a Receive Character Overrun (RxCharOver-
run) flag will be set in the SCON Register, and the data in the
RxBUF Register will be overwritten. When the communication
between the master and slave is complete, the SS goes inac-
tive.When the SPI is activated as a slave, it operates in all system
modes: STOP, HALT, and RUN.
Unless disconnected, for every bit that is transferred into the
slave through the DI pin, a bit is transferred out through the D0
pin on the opposite clock edge. During slave operation, the SPI
clock pin (SK) is an input. In master mode, the CPU must first
activate a SS through one of its I/O ports. Next, data is trans-
ferred through the master's D0 pin one bit per master clock cy-
cle. Loading data into the shift register initiates the transfer. In
master mode, the master's clock will drive the slave's clock. At
the conclusion of a transfer, a Receive Character Available
(RCA/IRQ3) flag and interrupt is generated. Before data is trans-
ferred via the D0 pin, the SPI Enable bit in the SCON Register
must be enabled.
9.8 SPI COMPARE
When the SPI Compare Enable bit, D3 of the SCON Register is
set to 1, the SPI Compare feature is enabled. The compare fea-
ture is only valid for slave mode. A compare transaction begins
when the (SS) line goes active. Data is received as if it were a
normal transaction, but there is no data transmitted to avoid bus
contention with other slave devices. When the compare byte is
received, IRQ3 is not generated. Instead, the data is compared
with the contents of the SCOMP Register. If the data does not
match, DO remains inactive and the slave ignores all data until
the (SS) signal is reset. If the data received matches the data in
the SCOMP register, then a SMR signal is generated. DO is ac-
tivated if it is not tri-stated by D2 in the SCON Register, and data
is received the same as any other SPI slave transaction.
Slaves' not comparing remain in their current mode, whereas
slaves' comparing wake from a STOP mode by means of an
SMR
9.9 SPI CLOCK
The SPI clock maybe driven by three sources: Timer0, a division
of the internal system clock, or the external master when in slave
mode. Bit D6 of the SCON Register controls what source drives
the SPI clock. A 0 in bit D6 of the SCON Register determines
the division of the internal system clock if this is used as the SPI
clock source. Divide by 2, 4, 8, or 16 is chosen as the scaler.
Z8 Microcontrollers
Serial I/O
ZiLOG
9-10
UM001601-0803
Figure 9-13. SPI System Configuration
ss sk do di
Slave
Multiple slaves may have the same address
ss1
ss4
do
ss2
ss3
sk
di
Master
Three Wire Compare Setup
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss
sk
do
di
Master
ss sk do di
Slave
Setup For Compare
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss
sk
do
di
Master
Up to 256 slaves per SS line
(1) (2) (255) (256)
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
Standard Parallel Setup
ss sk do di
Slave
Standard Serial Setup
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss
sk
do
di
Master
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-11
9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN
When a complete data stream is received, an interrupt is gener-
ated and the RxCharAvail bit in the SCON Register is set. Bit 4
in the SCON Register is for enabling or disabling the RxCharA-
vail interrupt. The RxCharAvail bit is available for interrupt
polling purposes and is reset when the RxBUF Register is read.
RxCharAvail is generated in both master and slave modes.
While in slave mode, if the RxBUF is not read before the next
data stream is received and loaded into the RxBUF Register, Re-
ceive Character Overrun (RxCharOverrun) occurs. Since there is
no need for clock control in slave mode, bit D1 in the SPI Con-
trol Register is used to log any RxCharOverrun (Figure 9-14 and
Figure 9-15).
No
Parameter
Min
Units
1
DI to SK Setup
10
ns
2
SK to D0 Valid
15
ns
3
SS to SK Setup
.5 Tsk
ns
4
SS to D0 Valid
15
ns
5
SK to DI Hold Time
10
ns
Figure 9-14. SPI Timing
TSK
SS
SK
D0
DI
1
2
3
4
5
Z8 Microcontrollers
Serial I/O
ZiLOG
9-12
UM001601-0803
9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN
(Continued)
Figure 9-15. SPI Logic
SPI Compare Register (SCOMP)
SS
D0
DI
SK
Port
TCLK
SMR
Bit Control
SPI Control
SPI Receive Buffer (RxBUF)
SPI Shift Register
/Interrupt
Control
IRQ
3
SCLK + n
SPI
Clock
Control
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-13
Figure 9-16. SPI Data In/Out Configuration
P27 OUT
PIN
SPI Active
P27 IN
0 SOI D0 Enable
OPEN-DRAIN
Auto Latch
P27
P20 OE
PIN
P20 IN
OPEN-DRAIN
R
500 K
Auto Latch
P20
SPI EN
SPI DO
P27 OE
SPI
SPI DO
SPI
Standard
Standard
1 P27 OUT
*SPI must be enabled with D0
D2
SCON
or
SPI DI
R
500 K
Z8 Microcontrollers
Serial I/O
ZiLOG
9-14
UM001601-0803
9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN
(Continued)
Figure 9-17. SPI Clock / SPI Slave Select Output Configuration
SPI MSTR
PIN
P31
+
SPI EN
P34
SK IN
SPI MSTR
PIN
P35
SPI EN
REF
SS
0 P34, P35 Standard Output
1 P34, P35 Comparator Output
D0
P35 OUT
PCON
P32
REF
+
-
P34 OUT
-
SPI EN
SK OUT
MUX
Z8 Microcontrollers
ZiLOG
Serial I/O
UM001601-0803
9-15
Z8 Microcontrollers
Serial I/O
ZiLOG
9-16
UM001601-0803
UM001601-0803
10-1
U
SER
'
S
M
ANUAL
C
HAPTER
10
E
XTERNAL
I
NTERFACE
10.1 INTRODUCTION
The Z8
can be a microcontroller with 20 pins for external mem-
ory interfacing. The external memory interface on the Z8 is gen-
erally for either RAM or ROM. This is only available for devices
featuring Port 0, Port 1, R/W, DM, AS, and DS. Please refer to
specific product specifications for availability of these features.
The Z8 has a multiplexed external memory interface. In the mul-
tiplexed mode, eight pins from Port 1 form an Address/Data Bus
(AD7-AD0), eight pins from Port 0 form a High Address Bus
(A15-A8). Three additional pins provide the Address Strobe,
Data Strobe, and the Read/Write Signal. Figure 10-1 shows the
Z8 external interface pins.
Figure 10-1. Z8 External Interface Pins
External
Z8 MCU
Program/Data
64 Kbytes
Each
(Port 1) AD7 - AD0
(Port 0) AD15 - AD8
/AS
/DS
R//W
/DM
Z8 Microcontrollers
External Interface
ZiLOG
10-2
UM001601-0803
10.2 PIN DESCRIPTIONS
The following sections briefly describe the pins associated with
the Z8 MCU
external memory interface.
10.2.1 /AS
Address Strobe (output, active Low). Address Strobe is pulsed
Low once at the beginning of each machine cycle. The rising
edge of AS indicates the address, Read/Write (R/W), and Data
Memory (DM) signals are valid for program or data memory
transfers. In some cases, the Z8 address strobe is pulsed low re-
gardless of accessing external or internal memory. Please refer
to specific product specifications for AS operation.
10.2.2
DS
Data Strobe (Output, Active Low). Data Strobe provides the
timing for data movement to or from the Address/Data bus for
each external memory transfer. During a Write Cycle, data out is
valid at the leading edge of the DS. During a Read Cycle, data in
must be valid prior to the trailing edge of the DS.
10.2.3 R/W
Read/Write (Output). Read/Write determines the direction of
data transfer for memory transactions. R/W is Low when writing
to program or data memory, and High for all other transactions.
10.2.4 DM
Data Memory (Output). Data Memory provides a signal to sep-
arate External Program Memory from External Data Memory. It
is a programmable function on pin P34. Data memory is active
low for External Data Memory accesses and high for External
Program Memory accesses.
10.2.5 P07 - P00
High Address Lines A15 -A8 (Outputs can be CMOS- or TTL-
compatible. Please refer to product specifications for actual
type). A15-A8 provide the High Address lines for the memory
interface. Port 0 - 1 mode register must have bits D7 = 1 and D1
= 1 to configure Port 0 as A15 - A8 (Figure 10-2).
10.2.6 P17 - P10
Address/Data Lines AD7 - AD0 (inputs/outputs, TTL-compati-
ble). AD7-AD0 is a multiplexed Address/Data memory inter-
face. The lower eight Address lines (A7-A0) are multiplexed
with Data lines (D7-D0). Port 0 - 1 mode register must have bits
D4 = 1 and D3 = 0 to configure Port 1 as AD7 - AD0 (Figure 10-
2).
10.2.7 /RESET
Reset (input, active Low). RESET initializes the Z8. When
RESET is deactivated, program execution begins from program
location 000CH. If held Low, RESET acts as a register file
protect during power-down and power-up sequences. To avoid
asynchronous and noisy reset problems, the Z8 is equipped with
a reset filter of four external clocks (4T
P
C). If the external
RESET signal is less than 4T
P
C in duration, no reset will occur.
On the fifth clock after the RESET is detected, an internal reset
signal is latched and held for an internal register count of 18 or
more external clocks, or for the duration of the external RESET,
whichever is longer. Please refer to specific product
specifications for length of reset delay time.
10.2.8 XTAL1, XTAL2.
Crystal1, Crystal2 (Oscillator input and output). These pins con-
nect a parallel-resonant crystal, ceramic resonator, LC, RC net-
work, or external single-phase clock to the on-chip oscillator in-
put. Please refer to the device product specifications for
information on availability of RC oscillator features.
Z8 Microcontrollers
ZiLOG
External Interface
UM001601-0803
10-3
10.3 EXTERNAL ADDRESSING CONFIGURATION
The minimum bus configuration uses Port 1 as a multiplexed ad-
dress/data port (AD7 - AD0), allowing access to 256 bytes of ex-
ternal memory. In this configuration, the eight low-order bits
(A0 - A7) are multiplexed with the data (D7 - D0).
Port 0 can be programmed to provide either four additional ad-
dress lines (A11- A8), which increases the addressable memory
to 4K bytes, or eight additional address lines (A15 - A8), which
increases the addressable external memory up to 64K bytes. It is
required to add a NOP after configuring Port 0 / Port 1 for exter-
nal addressing before jumping to external memory execution.
Figure 10-2. External Address Configuration
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
01 = Input
1X = A
8
- A
11
P0
0
- P0
7
Mode
00 = Output
Port 0-1 Mode Register (P01M)
Register F8H (P01M)
01 = Byte Output
P0
4
- P0
7
Mode
00 = Output
01 = Input
1X = A
12
- A
15
10 = AD
0
-AD
7
00 = Byte Output
P
10
- P
17
Mode

A
8
- A
15
,
AS
,
DS
,
R/
W
11 = High Impedance AD
0
- AD
7
,
Z8 Microcontrollers
External Interface
ZiLOG
10-4
UM001601-0803
10.4 EXTERNAL STACKS
The Z8 architecture supports stack operations in either the Z8
Standard Register File or External Data Memory. A stack's lo-
cation is determined by bit 2 in the Port 0-1 Mode Register
(F8H). If bit 2 is set to 0, the stack is in External Data Memory.
(Figure 10-3).
The instruction used to change the stack selection bit should not
be immediately followed by the instructions RET or IRET, be-
cause this will cause indeterminate program flow. After a RE-
SET, the internal stack is selected.
Please note that if Port 0 is configured as A15 - A8 and the stack
is selected as internal, any stack operation will cause the contents
in register FEH to be displayed on Port 0.
10.5 DATA MEMORY
The two Z8 external memory spaces, data and program, are ad-
dressed as two separate spaces of up to 64 Kbytes each. External
Program Memory and External Data Memory are logically se-
lected by the Data Memory select output (DM). DM is made
available on Port 3, bit 4 (P34) by setting bit 4 and bit 3 in the
Port 3 Mode Register (F7H) to 10 or 01 (Figure 10-4). DM is ac-
tive Low during the execution of the LDE, LDEI instructions,
and High for the execution of program instructions. DM is also
active Low during the execution of CALL, POP, PUSH, RET
and IRET instructions if the stack resides in External Data Mem-
ory. After a RESET, DM is not selected.
Figure 10-3. Z8 Stack Selection
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 0-1 Register
Register F8H (P01M)
Z8 Stack Selection
0 = External
1 = Internal
Figure 10-4. Port 3 Data Memory Operation
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Bits Configuration
00 P33 = Input P34 = Output
01 P33 = Input P34 = /DM
Port 3 Mode Register
Register F7H (P3M)
10 P33 = Input P34 = /DM

11 P33 = /DAV1/RDY1 P34 = RDY1//DAV1
Z8 Microcontrollers
ZiLOG
External Interface
UM001601-0803
10-5
10.6 BUS OPERATION
Typical data transfers between the Z8 MCU and External Mem-
ory are illustrated in Figures 10-5 and 10-6. Machine cycles can
vary from six to 12 clock periods depending on the operation be-
ing performed. The notations used to describe the basic timing
periods of the Z8 are machine cycles (Mn), timing states (Tn),
and clock periods. All timing references are made with respect
to the output signals AS and DS. The clock is shown for clarity
only and does not have a specific timing relationship with other
signals.
Figure 10-5. External Instruction Fetch or Memory Read Cycle
Machine Cycle
T1
T2*
T3
Clock
A15-A8
AD7-AD0
/AS
/DS
R/W
/DM
Read Cycle
A8-A15
A7-A0
D7-D0 IN
*Port inputs are strobed during T2, which is two internal systems clocks
before the execution cycle of the current instruction.
Z8 Microcontrollers
External Interface
ZiLOG
10-6
UM001601-0803
10.6 BUS OPERATION
(Continued)
10.6.1 Address Strobe (
AS
)
All transactions start with AS driven Low and then raised High
by the Z8 MCU. The rising edge of AS indicates that R/W, DM
(if used), and the address outputs are valid. The address outputs
(AD7-AD0), remain valid only during MnT1 and typically need
to be latched using AS. Address outputs (A15-A8) remain stable
throughout the machine cycle, regardless of the addressing
mode.
10.6.2 Data Strobe (/DS)
The Z8 uses DS to time the actual data transfer. For Write oper-
ations (R/W = Low), a Low on DS indicates that valid data is on
the AD7-AD0 lines. For Read operations (R/W = High), the bus
is placed in a high-impedance state before driving DS Low, so
the addressed device can put its data on the bus. The Z8 samples
this data prior to raising DS High.
Figure 10-6. External Memory Write Cycle
Machine Cycle
T1
T2
T3
Clock
A15-A8
AD7-AD0
/AS
/DS
R/W
/DM
Write Cycle
A8-A15
A7-A0
D7-D0 OUT
Z8 Microcontrollers
ZiLOG
External Interface
UM001601-0803
10-7
10.7 EXTENDED BUS TIMING
Some products can accommodate slow memory access time by
automatically inserting an additional software controlled state
time (Tx). This stretches the DS timing by two clock periods.
Figures 10-7 and 10-8 illustrate extended external memory Read
and Write cycles.
Figure 10-7. Extended External Instruction Fetch or Memory Read Cycle
Machine Cycle
T2*
TX
T3
Clock
A15-A8
AD7-AD0
/AS
/DS
R/W
/DM
Read Cycle
A15-A8
A7-A0
D7-D0 IN
T1
*Port inputs are strobed during T2, which is two internal system clocks
before the execution of the current instruction.
Z8 Microcontrollers
External Interface
ZiLOG
10-8
UM001601-0803
Timing is extended by setting bit D5 in the Port 0-1 Mode Reg-
ister (F8H) to 1 (Figure 10-9). After a RESET, this bit is set to 0.
Figure 10-8. Extended External Memory Write Cycle
Machine Cycle
T2
TX
T3
Clock
A15-A8
AD7-AD0
AS
DS
R/W
DM
Write Cycle
A15-A8
A7-A0
D7-D0 OUT
T1
Figure 10-9. Extended Bus Timing
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 0-1 Register
Register F8H (P01M)
External Memory Timing
0 = Normal
1 = Extended
Z8 Microcontrollers
ZiLOG
External Interface
UM001601-0803
10-9
10.8 INSTRUCTION TIMING
The High throughput of the Z8 is due, in part, to the use of an
instruction pipeline, in which the instruction fetch and execution
cycles are overlapped. During the execution of the current in-
struction, the opcode of the next instruction is fetched. Instruc-
tion pipelining is illustrated in Figure 10-10.
Figures 10-10 and 10-11 show typical instruction cycle timing
for instructions fetched from memory. For those instructions that
require execution time longer than that of the overlapped fetch,
or reference program or data memory as part of their execution,
the pipe must be flushed.
Figures 10-10 and 10-11 assume the XTAL/2 clock mode is
selected.
Figure 10-10. Instruction Cycle Timing (One-Byte Instructions)
T1
T2
T3
T3
T1
/DS
/AS
R/W
T1
T2
T2
Fetch 1st Byte
T3
M1
M2
M3
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
Fetch 1st Byte Of Next Instruction
* Port inputs are strobed during T2, which is two internal system clocks
before the execution cycle of the current installation
Clock
Z8 Microcontrollers
External Interface
ZiLOG
10-10
UM001601-0803
10.9 Z8 RESET CONDITIONS
After a hardware reset, extended timing is set to accommodate
slow memory access during the configuration routine, DM is in-
active, the stack resides in the register file. Port 0, 1, and 2 are
reset to input mode. Port 2 is set to Open-Drain Mode.
Figure 10-11. Instruction Cycle Timing (2- and 3-Byte Instructions)
T1
T2
T3
T3
T1
DS
AS
R/W
T1
T2
T2
Fetch 1st Byte
T3
M1
M2
M3
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
Fetch 2nd Byte
Fetch 3rd Byte
Fetch 1st Byte (1- or 2-Byte Instruction)
(3-Byte Instruction)
A15-A8
A7-A0
A7-A0
Clock
*Port inputs are strobed during T2, which is two internal system clocks before
the execution cycle of the current instruction.
UM001601-0803
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11
A
DDRESSING
M
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11.1 INTRODUCTION
11.1.1 Z8 Addressing Modes
The Z8 microcontroller provides six addressing modes:
Register (R)
Indirect Register (IR)
Indexed (X)
Direct (D)
Relative (RA)
Immediate (IM)
With the exception of immediate data and condition codes, all
operands are expressed as register file, Program Memory, or
Data Memory addresses. Registers are accessed using 8-bit ad-
dresses in the range of 00H-FFH. The Program Memory or Data
Memory is accessed using 16-bit addresses (register pairs) in the
range of 0000H-FFFFH.
Working Registers are accessed using 4-bit addresses in the
range of 0-15 (0H-FH). The address of the register being access-
ed is formed by the combination of the upper four bits in the Reg-
ister Pointer (R253) and the 4-bit working register address sup-
plied by the instruction.
Registers can be used in pairs to designate 16-bit values or mem-
ory addresses. A Register Pair must be specified as an even-num-
bered address in the range of 0, 2,...., 14 for Working Registers,
or 4, 6,....238 for actual registers.
In the following definitions of Z8 Addressing Modes, the use
of'register' can also imply register pair, working register, or
working register pair, depending on the context.
Note: See the product data sheet for exact program, data, and
register memory types and address ranges available.
Z8 Microcontrollers
Addressing Modes
ZiLOG
11-2
UM001601-0803
11.2 Z8 REGISTER ADDRESSING (R)
In 8-bit Register Addressing mode, the operand value is equiva-
lent to the contents of the specified register or register pair.
In the Register Addressing (Figure 11-1), the destination and/or
source address specified corresponds to the actual register in the
register file.
In 4-bit Register Addressing (Figure 11-2), the destination
and/or source addresses point to the Working Register within the
current Working Register Group. This 4-bit address is combined
with the upper four bits of the Register Pointer to form the actual
8-bit address of the affected register.
Figure 11-1. 8-Bit Register Addressing
OpCode
One Operand
Register File
Operand
Program Memory
Points to
dst
8-Bit Register
One Register
in the
Register
File
Instruction
(Example)
File Address
Figure 11-2. 4-Bit Register Addressing
Op Code
Two Operand
Register File
Operand
Program Memory
Points to
src
4-Bit Working
One Register
in the
Register
File
Instruction
(Example)
Registers
Operand
RP
dst
Points to
Origin of
Working
Register
Group
Z8 Microcontrollers
ZiLOG
Addressing Modes
UM001601-0803
11-3
11.3 Z8 INDIRECT REGISTER ADDRESSING (IR)
In the Indirect Register Addressing Mode, the contents of the
specified register are equivalent to the address of the operand
(Figures 11-3 and 11-4).
Depending upon the instruction selected, the specified register
contents points to a Register, Program Memory, or an External
Data Memory location.
When accessing program memory or External Data Memory,
register pairs or Working Register pairs are used to hold the 16-
bit addresses.
Figure 11-3. 4-Bit Register Addressing
Op Code
One Operand
Register File
Operand
Program Memory
Points to one
8-Bit Register
Value Used in
Address of Operand
Instruction
(Example)
File Address
Address
dst
Points to
Register of
Operand
Register in
Register File
Instruction
Execution
Used By Instruction
Z8 Microcontrollers
Addressing Modes
ZiLOG
11-4
UM001601-0803
11.3 Z8 INDIRECT REGISTER ADDRESSING (IR) (Continued)
Figure 11-4. Indirect Register Addressing to Program or Data Memory
Op Code
Instruction Example
Program or
Register File
Program Memory
Points to
src
4-Bit Working
Points to Origin
Registers Address
Register
dst
RP
Operand
Pair LSB
Register
Pair MSB
Data Memory
Working
Register
Pair (Even
Address)
of Working
Register Group
16-Bit Address
Points to Program
or Data Memory
References Either
Program Memory or
Data Memory
Value Used in
Instruction
Z8 Microcontrollers
ZiLOG
Addressing Modes
UM001601-0803
11-5
11.4 Z8 INDEXED ADDRESSING (X)
The Indexed Addressing Mode is used only by the Load (LD) in-
struction. An indexed address consists of a register address off-
set by the contents of a designated Working Register (the Index).
This offset is added to the register address to obtain the address
of the operand. Figure 11-5 illustrates this addressing conven-
tion.
Figure 11-5. Indexed Register Addressing
Op Code
Register File
Program Memory
Points to
src
Two Operand
Points to Origin
Instruction
dst/
RP
Operand
Offset
Working
Register
Offset
Address
of Working
Register Group
Value Used in
Instruction
Address
X
Z8 Microcontrollers
Addressing Modes
ZiLOG
11-6
UM001601-0803
11.5 Z8 DIRECT ADDRESSING (DA)
The Direct Addressing mode, as shown in Figure 11-6, specifies
the address of the next instruction to be executed. Only the Con-
ditional Jump (JP) and Call (CALL) instructions use this ad-
dressing mode.
Figure 11-6. Direct Addressing
Op Code
Upper Addr. Byte
Lower Addr. Byte
Program Memory
Program Memory
Address Used
Z8 Microcontrollers
ZiLOG
Addressing Modes
UM001601-0803
11-7
11.6 Z8 RELATIVE ADDRESSING (RA)
In the Relative Addressing mode, illustrated in Figure 11-7, the
instruction specifies a two's-complement signed displacement in
the range of 128 to +127. This is added to the contents of the
PC to obtain the address of the next instruction to be executed.
The PC (prior to the add) consists of the address of the instruc-
tion following the Jump Relative (JR) or Decrement and Jump if
Non-Zero (DJNZ) instruction. JR and DJNZ are the only instruc-
tions which use this addressing mode.
Figure 11-7. Relative Addressing
OpCode
Displacement
Next OpCode
Current
JR or DJNZ
Program Memory
Program Memory
Address Used
PC Value
Z8 Microcontrollers
Addressing Modes
ZiLOG
11-8
UM001601-0803
11.7 Z8 IMMEDIATE DATA ADDRESSING (IM)
Immediate data is considered an "addressing mode" for the pur-
poses of this discussion. It is the only addressing mode that does
not indicate a register or memory address as the source operand.
The operand value used by the instruction is the value supplied
in the operand field itself. Because an immediate operand is part
of the instruction, it is always located in the Program Memory
address space (Figure 11-8).
Figure 11-8. Immediate Data Addressing
OpCode
Immediate Data
Program Memory
The Operand value
is in the instruction
UM001601-0803
12-1
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12
I
NSTRUCTION
S
ET
12.1 Z8 FUNCTIONAL SUMMARY
Z8
instructions can be divided functionally into the following
eight groups:
Load
Bit Manipulation
Arithmetic
Block Transfer
Logical
Rotate and Shift
Program Control
CPU Control
The following summary shows the instructions belonging to
each group and the number of operands required for each. The
source operand is src, the destination operand is dst, and a con-
dition code is cc.
Table 12-1. Load Instructions
Mnemonic
Operands
Instruction
CLR
dst
Clear
LD
dst, src
Load
LDC
dst, src
Load Constant
LDE
dst, src
Load External
POP
dst
Pop
PUSH
src
Push
Table 12-2. Arithmetic Instructions
Mnemonic
Operands
Instruction
ADC
dst, src
Add with Carry
ADD
dst, src
Add
CP
dst, src
Compare
DA
dst
Decimal Adjust
DEC
dst
Decrement
DECW
dst
Decrement Word
INC
dst
Increment
INCW
dst
Increment Word
SBC
dst, src
Subtract with Carry
SUB
dst, src
Subtract
Table 12-3. Logical Instructions
Mnemonic
Operands
Instruction
AND
dst, src
Logical AND
COM
dst
Complement
OR
dst, src
Logical OR
XOR
dst, src
Logical Exclusive OR
Table 12-4. Program Control Instructions
Mnemonic
Operands
Instruction
CALL
dst
Call Procedure
DJNZ
dst, src
Decrement and Jump
Non-Zero
IRET
Interrupt Return
JP
cc, dst
Jump
JR
cc, dst
Jump Relative
RET
Return
Z8 Microcontrollers
Instruction Set
ZiLOG
12-2
UM001601-0803
12.2 PROCESSOR FLAGS
The Flag Register (FCH) informs the user of the current status of
the Z8. The flags and their bit positions in the Flag Register are
shown in Figure 12-1.
The Z8 Flag Register contains six bits of status information
which are set or cleared by CPU operations. Four of the bits (C,
V, Z and S) can be tested for use with conditional Jump instruc-
tions. Two flags (H and D) cannot be tested and are used for
BCD arithmetic. The two remaining bits in the Flag Register (F1
and F2) are available to the user, but they must be set or cleared
by instructions and are not usable with conditional Jumps.
As with bits in the other control registers, the Flag Register bits
can be set or reset by instructions; however, only those instruc-
tions that do not affect the flags as an outcome of the execution
should be used (Load Immediate).
Note: The Watch-Dog Timer (WDT) instruction effects the
Flags accordingly: Z=1, S=0, V=0.
Table 12-5. Bit Manipulation Instructions
Mnemonic
Operands
Instruction
TCM
dst, src
Test Complement
Under Mask
TM
dst, src
Test Under Mask
AND
dst, src
Bit Clear
OR
dst, src
Bit Set
XOR
dst, src
Bit Complement
Table 12-6. Block Transfer Instructions
Mnemonic
Operands
Instruction
LDCI
dst, src
Load Constant
Auto Increment
LDEI
dst, src
Load External
Auto Increment
Table 12-7. Rotate and Shift Instructions
Mnemonic
Operands
Instruction
RL
dst
Rotate Left
RLC
dst
Rotate Left Through Carry
RR
dst
Rotate Right
RRC
dst
Rotate Right Through Carry
SRA
dst
Shift Right Arithmetic
SWAP
dst
Swap Nibbles
Table 12-8. CPU Control Instructions
Mnemonic
Operands
Instruction
CCF
Complement Carry Flag
DI
Disable Interrupts
EI
Enable Interrupts
HALT
Halt
NOP
No Operation
RCF
Reset Carry Flag
SCF
Set Carry Flag
SRP
src
Set Register Pointer
STOP
Stop
WDH
WDT Enable During HALT
WDT
WDT Enable or Refresh
Z8 Microcontrollers
ZiLOG
Instruction Set
UM001601-0803
12-3
Figure 12-1. Z8 Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
Flag Register (Read/Write)
Half Carry Flag (H)
User Flag (F1)
User Flag (F2)

Register FCH (Flags)
Overflow Flag (V)
Carry Flag (C)
Decimal Adjust Flag (D)
Zero Flag (Z)
Sign Flag (S)
Z8 Microcontrollers
Instruction Set
ZiLOG
12-4
UM001601-0803
12.2.1 Carry Flag (C)
The Carry Flag is set to 1 whenever the result of an arithmetic
operation generates a carry or a borrow the high order bit 7. Oth-
erwise, the Carry Flag is cleared to 0.
Following Rotate and Shift instructions, the Carry Flag contains
the last value shifted out of the specified register.
An instruction can set, reset, or complement the Carry Flag.
IRET may change the value of the Carry Flag when the Flag
Register, saved in the Stack, is restored.
12.2.2 Zero Flag (Z)
For arithmetic and logical operations, the Zero Flag is set to 1 if
the result is zero. Otherwise, the Zero Flag is cleared to 0.
If the result of testing bits in a register is 00H, the Zero Flag is
set to 1. Otherwise the Zero Flag is cleared to 0.
If the result of a Rotate or Shift operation is 00H, the Zero Flag
is set to 1. Otherwise, the Zero Flag is cleared to 0.
IRET changes the value of the Zero Flag when the Flag Register
saved in the Stack is restored. The WDT Instruction sets the Zero
Flag to a 1.
12.2.3 Sign Flag (S)
The Sign Flag stores the value of the most significant bit of a re-
sult following an arithmetic, logical, Rotate, or Shift operation.
When performing arithmetic operations on signed numbers, bi-
nary two's-complement notation is used to represent and process
information. A positive number is identified by a 0 in the most
significant bit position (bit 7); therefore, the Sign Flag is also 0.
A negative number is identified by a 1 in the most significant bit
position (bit 7); therefore, the Sign Flag is also 1.
IRET changes the value of the Sign Flag when the Flag Register
saved in the Stack is restored.
12.2.4 Overflow Flag (V)
For signed arithmetic, Rotate, and Shift operations, the Over-
flow Flag is set to 1 when the result is greater than the maximum
possible number (>127) or less than the minimum possible num-
ber (<128) that can be represented in two's-complement form.
The Overflow Flag is set to 0 if no overflow occurs.
Following logical operations the Overflow Flag is set to 0.
IRET changes the value of the Overflow Flag when the Flag
Register saved in the Stack is restored.
12.2.5 Decimal Adjust Flag (D)
The Decimal Adjust Flag is used for BCD arithmetic. Since the
algorithm for correcting BCD operations is different for addition
and subtraction, this flag specifies what type of instruction was
last executed so that the subsequent Decimal Adjust (DA) oper-
ation can function properly. Normally, the Decimal Adjust Flag
cannot be used as a test condition.
After a subtraction, the Decimal Adjust Flag is set to 1. Follow-
ing an addition it is cleared to 0.
IRET changes the value of the Decimal Adjust Flag when the
Flag Register saved in the Stack is restored.
12.2.6 Half Carry Flag (H)
The Half Carry Flag is set to 1 whenever an addition generates a
carry bit 3 (Overflow) or a subtraction generates a borrow bit 3.
The Half Carry Flag is used by the Decimal Adjust (DA) instruc-
tion to convert the binary result of a previous addition or subtrac-
tion into the correct decimal (BCD) result. As in the case of the
Decimal Adjust Flag, the user does not normally access this flag.
IRET changes the value of the Half Carry Flag when the Flag
Register saved in the Stack is restored.
Z8 Microcontrollers
ZiLOG
Instruction Set
UM001601-0803
12-5
12.3 CONDITION CODES
The C, Z, S, and V Flags control the operation of the `Condition-
al' Jump instructions. Sixteen frequently useful functions of the
flag settings are encoded in a 4-bit field called the condition code
(cc), which forms bits 4-7 of the conditional instructions.
Condition codes and flag settings are summarized in Tables 12-
9, 12-10, and 12-11. Notation for the flags and how they are af-
fected are as follows:
Table 12-9. Z8 Flag Definitions
Flag
Description
C
Carry Flag
Z
Zero Flag
S
Sign Flag
V
Overflow Flag
D
Decimal Adjust Flag
H
Half Carry Flag
Table 12-10. Flag Settings Definitions
Symbol
Definition
0
Cleared to 0
1
Set to 1
*
Set or cleared according to operation
Unaffected
X
Undefined
Table 12-11. Condition Codes
Binary
HEX
Mnemonic
Definition
Flag Settings
0000
0
F
Always False
1000
8
(blank)
Always True
0111
7
C
Carry
C = 1
1111
F
NC
No Carry
C = 0
0110
6
Z
Zero
Z = 1
1110
E
NZ
Non-Zero
Z = 0
1101
D
PL
Plus
S = 0
0101
5
Ml
Minus
S = 1
0100
4
OV
Overflow
V = 1
1100
C
NOV
No Overflow
V = 0
0110
6
EQ
Equal
Z = 1
1110
E
NE
Not Equal
Z = 0
1001
9
GE
Greater Than or Equal
(S XOR V) = 0
0001
1
LT
Less Than
(S XOR V) = 1
1010
A
GT
Greater Than
(Z OR (S XOR V)) = 0
0010
2
LE
Less Than or Equal
(Z OR (S XOR V)) = 1
1111
F
UGE
Unsigned Greater Than or Equal
C = 0
0111
7
ULT
Unsigned Less Than
C = 1
1011
B
UGT
Unsigned Greater Than
(C = 0 AND Z = 0) = 1
0011
3
ULE
Unsigned Less Than or Equal
(C OR Z) = 1
Z8 Microcontrollers
Instruction Set
ZiLOG
12-6
UM001601-0803
12.4 NOTATION AND BINARY ENCODING
In the detailed instruction descriptions that make up the rest of
this chapter, operands and status flags are represented by a nota-
tional shorthand. Operands, condition codes, address modes, and
their notations are as follows (Table 12-12):
Table 12-12. Notational Shorthand
Notation
Address Mode
Operand
Range *
cc
Condition Code
See condition codes
r
Working Register
Rn
n = 0 15
R
Register
Reg
Reg. represents a number in the range of 00H to FFH
or
Working Register
Rn
n = 0 15
RR
Register Pair
Reg
Reg. represents an even number in the range of 00H to FEH
or
Working Register Pair
RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14
Ir
Indirect Working Register
@Rn
n = 0 15
IR
Indirect Register
@Reg
Reg. represents a number in the range of 00H to FFH
or
Indirect Working Register
@Rn
n = 0 15
Irr
Indirect Working Register Pair
@RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14
IRR
Indirect Register Pair
@Reg
Reg. represents an even number in the range 00H to FFH
or
Working Register Pair
@RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14
X
Indexed
Reg (Rn)
Reg. represents a number in the range of 00H to FFH and n = 0 15
DA
Direct Address
Addrs
Addrs. represents a number in the range of 00H to FFH
RA
Relative Address
Addrs
Addrs. represents a number in the range of +127 to 128 which is an
offset relative to the address of the next instruction
IM
Immediate
#Data
Data is a number between 00H to FFH
*See the device product specification to determine the exact register file range available. The register file size varies by the device type.
Z8 Microcontrollers
ZiLOG
Instruction Set
UM001601-0803
12-7
Additional symbols used are:
Assignment of a value is indicated by the symbol "". For exam-
ple,
dst dst + src
indicates the source data is added to the destination data and the
result is stored in the destination location.
The notation 'addr(n)' is used to refer to bit'n' of a given location.
For example,
dst (7)
refers to bit 7 of the destination operand.
12.4.1 Assembly Language Syntax
For proper instruction execution, Z8 assembly language syntax
requires `dst, src' be specified, in that order. The following in-
struction descriptions show the format of the object code pro-
duced by the assembler. This binary format should be followed
by users who prefer manual program coding or who intend to im-
plement their own assembler.
Example: If the contents of registers 43H and 08H are added and
the result is stored in 43H, the assembly syntax and resulting ob-
ject code is:
In general, whenever an instruction format requires an 8-bit reg-
ister address, that address can specify any register location in the
range 0 - 255 or a Working Register R0 - R15. If, in the above
example, register 08H is a Working Register, the assembly syn-
tax and resulting object code would be:
Note: See the device product specification to determine the
exact register file range available. The register file size varies by
device type
Table 12-13. Additional Symbols
Symbol
Definition
dst
Destination Operand
src
Source Operand
@
Indirect Address Prefix
SP
Stack Pointer
PC
Program Counter
FLAGS
Flag Register (FCH)
RP
Register Pointer (FDH)
IMR
Interrupt Mask Register (FBH)
#
Immediate Operand Prefix
%
Hexadecimal Number Prefix
H
Hexadecimal Number Suffix
B
Binary Number Suffix
OPC
Opcode
ASM:
ADD
43H,
08H
(ADD dst, src)
OBJ:
04
08
43
(OPC src, dst)
ASM:
ADD
43H,
08H
(ADD dst, src)
OBJ:
04
08
43
(OPC src, dst)
Z8 Microcontrollers
Instruction Set
ZiLOG
12-8
UM001601-0803
12.5 Z8 INSTRUCTION SUMMARY
Instruction
and Operation
Address
Mode
Op Code
Byte (Hex)
Flags Affected
dst
src
C Z S V D H
ADC dst, src
dst
dst + src
+C
1[ ]
0
ADD dst, src
dst
dst + src
0[ ]
0
AND dst, src
dst
dst AND
src
5[ ]
0
CALL dst
DA
D6
SP
SP 2
IRR
D4
and PC
dst
or @ SP
PC
CCF
EF
C
NOT C
CLR dst
R
B0
dst
0
IR
B1
COM dst
R
60
0
dst
NOT dst
IR
61
CP dst, src
A[ ]
dst
- src
DA dst
R
40
X
dst
DA dst
IR
41
DEC dst
R
00
dst
dst 1
IR
01
DECW dst
R R
80
dst
dst 1
IR
81
DI dst
8 F
IMR(7)
0
DJNZr, dst
RA
rA
r
r 1
r=0-F
if r
0
PC
PC + dst
Range:+127,
-128
EI
9 F
IMR(7)
1
HALT
7 F
INC dst
dst
dst + 1
r
rE
r=0-F
R
20
IR
21
INCW dst
RR
A0
dst
dst + 1
IR
A1
Instruction
and Operation
Address
Mode
Op Code
Byte (Hex)
Flags Affected
dst
src
C Z S V D H
IRET
B F
FLAGS
@SP;
SP
SP + 1
PC
@SP;
SP
SP + 2;
and IMR(7) 1
JP cc, dst
DA
cD
if cc is true,
c = 0 F
then PC
dst
IRR
30
JR cc, dst
RA
cB
if cc is true,
c = 0 F
PC
PC + dst
Range: +127,
128
LD dst, src
r
Im
r C
dst
src
r
R
r 8
R
r
r 9
r = 0 F
r
X
C 7
X
r
D 7
r
Ir
E 3
Ir
r
F 3
R
R
E 4
R
IR
E 5
R
IM
E 6
IR
IM
E 7
IR
R
F 5
LDC dst, src
r
Irr
C 2
dst
src
lrr
r
D 2
LDCI dst, src
Ir
Irr
C 3
dst
src
lrr
Ir
D 3
r
r + 1 or
rr
rr + 1
LDE dst, src
r
Irr
82
dst
src
lrr
r
92
LDEI dst, src
Ir
Irr
83
dst
src and
lrr
Ir
93
r
r + 1 or
rr
rr + 1
NOP
FF
OR dst, src
4[ ]
0
dst
dst OR src
Z8 Microcontrollers
ZiLOG
Instruction Set
UM001601-0803
12-9
Instruction
Address
Mode
Op Code
Byte
Flags Affected
and Operation dst
src
(Hex)
C Z S V D H
POP dst
R
50
dst
@SP
IR
51
and SP
SP + 1
PUSH src
R
70
SP
SP 1
IR
71
and @SP
src
RCF
C F
0
C
0
RET
A F
PC
@SP;
SP
SP + 2
RL dst
R
IR
90
91
RLC dst
R
IR
10
11
RR dst
R
IR
E 0
E 1
RRC dst
R
C 0
IR
C 1
SBC dst, src
3[ ]
1
dst
dst src
C
SCF
D F
1
C
1
SRA dst
R
D 0
0
IR
D 1
SRP dst
Im
31
RP
src
STOP
6 F
SUB dst, src
2[ ]
1
dst
dst src
SWAP dst
R
IR
F0
F1
X
X
Instruction
Address
Mode
Opcode
Byte
Flags Affected
and Operation dst
src
(Hex)
C Z S V D H
C
7
0
C
7
0
C
7
0
C
7
0
C
7
0
7
4 3
0
TCM dst, src
6[ ]
0
(NOT dst) AND
src
TM dst, src
7[ ]
0
dst AND src
WDH
4 F
X X X
WDT
5 F
X X X
XOR dst, src
7[ ]
0
dst AND src
XOR src
Note: These instructions have an identical set of addressing modes,
which are encoded for brevity. The first opcode nibble is found in the
instruction set table above. The second nibble is expressed symbolically
by a `[ ]' in this table, and its value is found in the following table to
the left of the applicable addressing mode pair. For example, the opcode
of an ADC instruction using the addressing modes r (destination) and Ir
(source) is 13.
Address
Mode
Lower
dst
src
Op Code Nibble
r
r
[2]
r
Ir
[3]
R
R
[4]
R
IR
[5]
R
IM
[6]
IR
IM
[7]
Z8 Microcontrollers
Instruction Set
ZiLOG
12-10
UM001601-0803
12.5.1 Op Code Map
10.5
CP
R , R1
6.5
DEC
R1
6.5
DEC
IR1
6.5
ADD
r1, r2
6.5
ADD
r1, Ir2
10.5
ADD
R2, R1
10.5
ADD
IR2, R1
10.5
ADD
R1, IM
10.5
ADD
IR1, IM
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Lower Nibble (Hex)
Bytes per Instruction
2
3
2
3
1
6.5
RLC
R1
6.5
RLC
IR1
6.5
ADC
r1, r2
6.5
ADC
r1, Ir2
10.5
ADC
R2, R1
10.5
ADC
IR2, R1
10.5
ADC
R1, IM
10.5
ADC
IR1, IM
6.5
INC
R1
6.5
INC
IR1
6.5
SUB
r1, r2
6.5
SUB
r1, Ir2
10.5
SUB
R2, R1
10.5
SUB
IR2, R1
10.5
SUB
R1, IM
10.5
SUB
IR1, IM
10.5
DECW
RR1
10.5
DECW
IR1
6.5
RL
R1
6.5
RL
IR1
10.5
INCW
RR1
10.5
INCW
IR1
6.5
CP
r1, r2
6.5
CP
r1, Ir2
10.5
CP
R2, R1
10.5
CP
IR2, R1
10.5
CP
R1, IM
10.5
CP
IR1, IM
6.5
CLR
R1
6.5
CLR
IR1
6.5
XOR
r1, r2
6.5
XOR
r1, Ir2
10.5
XOR
R2, R1
10.5
XOR
IR2, R1
10.5
XOR
R1, IM
10.5
XOR
IR1, IM
6.5
RRC
R1
6.5
RRC
IR1
12.0
LDC
r1, Irr2
18.0
LDCI
Ir1, Irr2
10.5
LD
r1,x,R2
6.5
SRA
R1
6.5
SRA
IR1
20.0
CALL*
IRR1
20.0
CALL
DA
10.5
LD
r2,x,R1
6.5
RR
R1
6.5
RR
IR1
6.5
LD
r1, IR2
10.5
LD
R2, R1
10.5
LD
IR2, R1
10.5
LD
R1, IM
10.5
LD
IR1, IM
8.5
SWAP
R1
8.5
SWAP
IR1
6.5
LD
Ir1, r2
10.5
LD
R2, IR1
6.5
LD
r1, R2
6.5
LD
r2, R1
12/10.5
DJNZ
r1, RA
12/10.0
JR
cc, RA
6.5
LD
r1, IM
12.10.0
JP
cc, DA
6.5
INC
r1
6.0
STOP
7.0
HALT
6.1
DI
6.1
EI
14.0
RET
16.0
IRET
6.5
RCF
6.5
SCF
6.5
CCF
6.0
NOP
2
4
A
Lower
Op Code
Nibble
Pipeline
Cycles
Mnemonic
Second
Operand
Fetch
Cycles
Upper
Op Code
Nibble
First
Operand
Legend:
R = 8-Bit Addr ess
r = 4-Bit Addr ess
R1 or r1 = Dst Addr ess
R2 or r2 = Sr c Addr ess
Sequence:
Opcode, First Operand,
Second Operand
Note: Blank areas ar e r eserved.
*2-byte instruction appears as
a 3-byte instruction
8.0
JP
IRR1
6.1
SRP
IM
6.5
SBC
r1, r2
6.5
SBC
r1, Ir2
10.5
SBC
R2, R1
10.5
SBC
IR2, R1
10.5
SBC
R1, IM
10.5
SBC
IR1, IM
8.5
DA
R1
8.5
DA
IR1
6.5
OR
r1, r2
6.5
OR
r1, Ir2
10.5
OR
R2, R1
10.5
OR
IR2, R1
10.5
OR
R1, IM
10.5
OR
IR1, IM
10.5
POP
R1
10.5
POP
IR1
6.5
AND
r1, r2
6.5
AND
r1, Ir2
10.5
AND
R2, R1
10.5
AND
IR2, R1
10.5
AND
R1, IM
10.5
AND
IR1, IM
6.5
COM
R1
6.5
COM
IR1
6.5
TCM
r1, r2
6.5
TCM
r1, Ir2
10.5
TCM
R2, R1
10.5
TCM
IR2, R1
10.5
TCM
R1, IM
10.5
TCM
IR1, IM
10/12.1
PUSH
R2
12/14.1
PUSH
IR2
6.5
TM
r1, r2
6.5
TM
r1, Ir2
10.5
TM
R2, R1
10.5
TM
IR2, R1
10.5
TM
R1, IM
10.5
TM
IR1, IM
6.0
WDT
6.0
WDH
Upper Nibbl
e
(Hex)
12.0
LDC
lrr1, r2
18.0
LDCI
lrr1, Ir2
12.0
LDE
r1, lrr2
18.0
LDEI
lr1, lrr2
12.0
LDE
r2, lrr1
18.0
LDEI
lr2, lrr1
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-11
12.6 INSTRUCTION DESCRIPTION AND FORMATS
ADC
ADD WITH CARRY
ADC
Add With Carry
ADC dst, src
Instruction Format:
Operation:
dst <-- dst + src + C
The source operand, along with the setting of the Carry (C) Flag, is added to the destination operand. Two's
complement addition is performed. The sum is stored in the destination operand. The contents of the source operand
are not affected. In multiple precision arithmetic, this instruction permits the carry from the addition of low order
operands to be carried into the addition of high order operands.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R3 contains 16H, the C Flag is set to 1, and Working Register R11 contains 20H, the statement:
ADC R3, R11
Op Code: 12 3B
leaves the value 37H in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
Flags:
C:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D:
Always cleared.
H:
Set if there is a carry from the most significant bit of the low order four bits of the result;
cleared otherwise.
dst
src
OPC
OPC
OPC
src
dst
dst
src
6
Cycles
OPC
(Hex)
Address
dst
Mode
src
12
r
r
6
13
r
Ir
10
14
R
R
10
15
R
IR
10
16
R
IM
10
17
IR
IM
E
src
E
dst
or
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-12
UM001601-0803
ADC
ADD WITH CARRY
Example:
If Working Register R16 contains 16H, the C Flag is not set, Working Register R10 contains 20H, and Register 20H
contains 11H, the statement:
ADC R16, @R10
Op Code: 13 FA
leaves the value 27H in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared.
Example
If Register 34H contains 2EH, the C Flag is set, and Register 12H contains 1BH, the statement:
ADC 34H, 12H
Op Code: 14 12 34
leaves the value 4AH in Register 34H. The H Flag is set, and the C, Z, S, V, and D Flags are cleared.
Example:
If Register 4BH contains 82H, the C Flag is set, Working Register R3 contains 10H, and Register 10H contains
01H, the statement:
ADC 4BH, @R3
Op Code: 15 E3 4B
leaves the value 84H in Register 4BH. The S Flag is set, and the C, Z, V, D, and H Flags are cleared.
Example:
If Register 6CH contains 2AH, and the C Flag is not set, the statement:
ADC 6CH, #03H
Op Code: 16 6C 03
leaves the value 2DH in Register 6CH. The C, Z, S, V, D, and H Flags are all cleared.
Example:
If Register D4H contains 5FH, Register 5FH contains 4CH, and the C Flag is set, the statement:
ADC @D4H, #02H
Op Code: 17 D4 02
leaves the value 4FH in Register 5FH. The C, Z, S, V, D, and H Flags are all cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-13
ADD
ADD
ADD
Add
ADD dst, src
Instruction Format:
Operation:
dst <-- dst + src
The source operand is added to the destination operand. Two's complement addition is performed. The sum is
stored in the destination operand. The contents of the source operand are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the
OpCode.
Example:
If Working Register R3 contains 16H and Working Register R11 contains 20H, the statement:
ADD R3, R11
OpCode: 02 3B
leaves the value 36H in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
Flags:
C:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if an arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the
opposite sign; cleared otherwise.
D:
Always cleared.
H:
Set if there is a carry from the most significant bit of the low order four bits of the result; cleared
otherwise.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-14
UM001601-0803
ADD
ADD
Example:
If Working Register R16 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11H, the
statement:
ADD R16, @R10
Op Code: 03 FA
leaves the value 27H in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared.
Example:
If Register 34H contains 2EH and Register 12H contains 1BH, the statement:
ADD 34H, 12H
Op Code: 04 12 34
leaves the value 49H in Register 34H. The H Flag is set, and the C, Z, S, V, and D Flags are cleared.
Example
If Register 4BH contains 82H, Working Register R3 contains 10H, and Register 10H contains 01H, the statement:
ADD 3EH, @R3
Op Code: 05 E3 4B
leaves the value 83H in Register 4BH. The S Flag is set, and the C, Z, V, D, and H Flags are cleared.
Example:
If Register 6CH contains 2AH, the statement:
ADD 6CH, #03H
Op Code: 06 6C 03
leaves the value 2DH in Register 6CH. The C, Z, S, V, D, and H Flags are all cleared.
Example:
If Register D4H contains 5FH and Register 5FH contains 4CH, the statement:
ADD @D4H, #02H
Op Code: 07 D4 02
leaves the value 4EH in Register 5FH. The C, Z, S, V, D, and H Flags are all cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-15
AND
Logical AND
AND
Logical AND
AND dst, src
Instruction Format:
Operation:
dst <-- dst AND src
The source operand is logically ANDed with the destination operand. The AND operation results in a 1 being stored
whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored. The result is stored in the
destination operand. The contents of the source bit are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R1 contains 34H (00111000B) and Working Register R14 contains 4DH (10001101), the
statement:
AND R1, R14
Op Code: 52 1E
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise
S:
Set if the result of bit 7 is set; cleared otherwise
V:
Always reset to 0
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-16
UM001601-0803
AND
Logical AND
Example:
If Working Register R4 contains F9H (11111001B), Working Register R13 contains 7BH, and Register 7BH
contains 6AH (01101010B), the statement:
AND R4, @R13
Op Code: 53 4D
leaves the value 68H (01101000B) in Working Register R4. The Z, V, and S Flags are cleared.
Example:
If Register 3AH contains the value F5H (11110101B) and Register 42H contains the value 0AH (00001010), the
statement:
AND 3AH, 42H
Op Code: 54 42 3A
leaves the value 00H (00000000B) in Register 3AH. The Z Flag is set, and the V and S Flags are cleared.
Example:
If Working Register R5 contains F0H (11110000B), Register 45H contains 3AH, and Register 3AH contains 7FH
(01111111B), the statement:
AND R5, @45H
Op Code: 55 45 E5
leaves the value 70H (01110000B) in Working Register R5. The Z, V, and S Flags are cleared.
Example:
If Register 7AH contains the value F7H (11110111B), the statement:
AND 7AH, #F0H
Op Code: 56 7A F0
leaves the value F0H (11110000B) in Register 7AH. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Working Register R3 contains the value 3EH and Register 3EH contains the value ECH (11101100B), the
statement:
AND @R3, #05H
Op Code: 57 E3 05
leaves the value 04H (00000100B) in Register 3EH. The Z, V, and S Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-17
CALL
CALL PROCEDURE
CALL
Call Procedure
CALL dst
Instruction Format:
Operation:
SP <-- SP - 2
@SP <-- PC
PC <-- dst
The Stack pointer is decremented by two, the current contents of the Program Counter (PC) (address of the first
instruction following the CALL instruction) are pushed onto the top of the Stack, and the specified destination
address is then loaded into the PC. The PC now points to the first instruction of the procedure.
At the end of the procedure a RET (return) instruction can be used to return to the original program flow. RET will
pop the top of the Stack and replace the original value into the PC.
Note:
Address mode IRR can be used to specify a 4-bit Working Register Pair. In this format, the destination Working
Register Pair operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register Pair RR12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-18
UM001601-0803
CALL
Call Procedure
Example:
If the contents of the PC are 1A47H and the contents of the SP (Registers FEH and FFH) are 3002H, the statement:
CALL 3521H
Op Code: D6 35 21
causes the SP to be decremented to 3000H, 1A4AH (the address following the CALL instruction) to be stored in
external data memory 3000 and 3001H, and the PC to be loaded with 3521H. The PC now points to the address of
the first statement in the procedure to be executed.
Example:
If the contents of the PC are 1A47H, the contents of the SP (Register FFH) are 72H, the contents of Register A4H
are 34H, and the contents of Register Pair 34H are 3521H, the statement:
CALL @A4H
Op Code: D4 A4
causes the SP to be decremented to 70H, 1A4AH (the address following the CALL instruction) to be stored in R70H
and 71H, and the PC to be loaded with 3521H. The PC now points to the address of the first statement in the
procedure to be executed.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-19
CCF
COMPLEMENT CARRY FLAG
CCF
Complement Carry Flag
CCF
Instruction Format:
Operation:
C <-- NOT C
The C Flag is complemented. If C = 1, then it is changed to C = 0; or, if C = 0, then it is changed to C = 1.
Example:
If the C Flag contains a 0, the statement:
CCF
Op Code: EF
will change the C Flag from C = 0 to C = 1.
Flags:
C:
Complemented
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-20
UM001601-0803
CLR
CLEAR
CLR
CLEAR
CLR dst
Instruction Format:
Operation:
dst <-- 0
The destination operand is cleared to 00H.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If Working Register R6 contains AFH, the statement:
CLR R6
Op Code: B0 E6
will leave the value 00H in Working Register R6.
If Register A5H contains the value 23H, and Register 23H contains the value FCH, the statement:
CLR @A5H
Op Code: B1 A5
will leave the value 00H in Register 23H.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-21
COM
COMPLEMENT
COM
Complement
COM dst
Instruction Format:
Operation:
dst <-- NOT dst
The contents of the destination operand are complemented (one's complement). All 1 bits are changed to 0, and all
0 bits are changed to 1.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If Register 08H contains 24H (00100100B), the statement:
COM 08H
Op Code: 60 08
leaves the value DBH (11011011) in Register 08H. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Register 08H contains 24H, and Register 24H contains FFH (11111111B), the statement:
COM @08H
Op Code: 61 08
leaves the value 00H (00000000B) in Register 24H. The Z Flag is set, and the V and S Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if result bit 7 is set; cleared otherwise.
V:
Always reset to 0.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-22
UM001601-0803
CP
COMPARE
CP
Compare
CP dst, src
Instruction Format:
Operation:
dst - src
The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set
accordingly. The contents of both operands are unaffected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R3 contains 16H and Working Register R11 contains 20H, the statement:
CP R3, R11
Op Code: A2 3B
sets the C and S Flags, and the Z and V Flags are cleared.
Flags:
C:
Cleared if there is a carry from the most significant bit of the result. Set otherwise indicating a borrow.
Z:
Set if the result is zero; cleared otherwise.
S:
Set if result bit 7 is set (negative); cleared otherwise.
V:
Set if arithmetic overflow occurs; cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-23
CP
COMPARE
Example:
If Working Register R15 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11H, the
statement:
CP R16, @R10
Op Code: A3 FA
clears the C, Z, S, and V Flags.
Example:
If Register 34H contains 2EH and Register 12H contains 1BH, the statement:
CP 34H,12H
Op Code: A4 12 34
clears the C, Z, S, and V Flags.
Example:
If Register 4BH contains 82H, Working Register R3 contains 10H, and Register 10H contains 01H, the statement:
CP 4BH, @R3
Op Code: A5 E3 4B
sets the S Flag, and clears the C, Z, and V Flags.
Example:
If Register 6CH contains 2AH, the statement:
CP 6CH, #2AH
Op Code: A6 6C 2A
sets the Z Flag, and the C, S, and V Flags are all cleared.
Example:
If Register D4H contains FCH, and Register FCH contains 8FH, the statement:
CP @D4H, 7FH
Op Code: A7 D4 FF
sets the V Flag, and the C, Z, and S Flags are all cleared.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-24
UM001601-0803
DA
DECIMAL ADJUST
DA
Decimal Adjust
DA dst
Instruction Format:
Operation:
dst <-- DA dst
The destination operand is adjusted to form two 4-bit BCD digits following a binary addition or subtraction
operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the following table
indicates the operation performed.
If the destination operand is not the result of a valid addition or subtraction of BCD digits, the operation is
undefined.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Carry
Bits 7-4
H Flag
Bits 3-0
Number
Carry
Instruction
Before
Value
Before
Value
Added To
After
DA
(HEX)
DA
(HEX)
Byte
DA
0
0-9
0
0-9
00
0
0
0-8
0
A-F
06
0
0
0-9
1
0-3
06
0
ADD
0
A-F
0
0-9
60
1
ADC
0
9-F
0
A-F
66
1
0
A-F
1
0-3
66
1
1
0-2
0
0-9
60
1
1
0-2
0
A-F
66
1
1
0-3
1
0-3
66
1
0
0-9
0
0-9
00
0
SUB
0
0-8
1
6-F
FA
0
SBC
1
7-F
0
0-9
A0
1
1
6-F
1
6-F
9A
1
Flags:
C:
Set if there is a carry from the most significant bit; cleared otherwise (see table above).
Z:
Set if the result is zero; cleared otherwise.
S:
Set if result bit 7 is set (negative); cleared otherwise.
D
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-25
Example:
If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however,
when the binary representations are added in the destination location using standard binary arithmetic.
If the result of the addition is stored in Register 5FH, the statement:
DA 5FH
Op Code: 40 5F
adjusts this result so the correct BCD representation is obtained.
Register 5F now contains the value 42H. The C, Z, and S Flags are cleared, and V is undefined.
Example:
If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however,
when the binary representations are added in the destination location using standard binary arithmetic.
Register 45F contains the value 5FH, and the result of the addition is stored in Register 5FH, the statement:
DA @45H
Op Code: 40 45
adjusts this result so the correct BCD representation is obtained.
Register 5F now contains the value 42H. The C, Z, and S Flags are cleared, and V is undefined.
0001 0101 = 15H
+0010 0111 = 27H
0011 1100 = 3CH
0011 1100 = 3CH
0000 0110 = 06H
0100 0010 = 42H
0001 0101 = 15H
+ 0010 0111 = 27H
0011 1100 = 3CH
0011 1100 = 3CH
0000 0110 = 06H
0100 0010 = 42H
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-26
UM001601-0803
DEC
DECREMENT
DEC
Decrement
DEC dst
Instruction Format:
Operation:
dst <-- dst - 1
The contents of the destination operand are decremented by one.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If Working Register R10 contains 2A%, the statement:
DEC R10
Op Code: 00 EA
leaves the value 29H in Working Register R10. The Z, V, and S Flags are cleared.
Example:
If Register B3H contains CBH, and Register CBH contains 01H, the statement:
DEC @B3H
Op Code: 01 B3
leaves the value 00H in Register CBH. The Z Flag is set, and the V and S Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise
S:
Set if the result of bit 7 is set (negative); cleared otherwise
V:
Set if arithmetic overflow occurs; cleared otherwise
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-27
DECW
DECREMENT WORD
DECW
Decrement Word
DECW dst
Instruction Format:
Operation:
dst <-- dst - 1
The contents of the destination (which must be an even address) operand are decremented by one. The destination
operand can be a Register Pair or a Working Register Pair.
Note:
Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this format, the destination
Working Register Pair operand is specified by adding 1110B (EH) to the high nibble of the operand. For example,
if Working Register Pair R12 (CH) is the destination operand, then ECH will be used as the destination operand in
the Op Code.
Example:
If Register Pair 30H and 31H contain the value 0AF2H, the statement:
DECW 30H
Op Code: 80 30
leaves the value 0AF1H in Register Pair 30H and 31H. The Z, V, and S Flags are cleared.
Example:
If Working Register R0 contains 30H and Register Pairs 30H and 31H contain the value FAF3H, the statement:
DECW @R0
Op Code: 81 E0
leaves the value FAF2H in Register Pair 30H and 31H. The S Flag is set, and the Z and V Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise
S:
Set if the result of bit 7 is set (negative); cleared otherwise
V:
Set if arithmetic overflow occurs; cleared otherwise
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-28
UM001601-0803
DI
DISABLE INTERRUPTS
DI
Disable Interrupts
Dl
Instruction Format:
Operation:
IMR (7) <-- 0
Bit 7 of Control Register FBH (the Interrupt Mask Register) is reset to 0. All interrupts are disabled, although they
remain "potentially" enabled. (For instance, the Global Interrupt Enable is cleared, but not the individual interrupt
level enables.)
Example:
If Control Register FBH contains 8AH (10001010) (interrupts IRQ1 and IRQ3 are enabled), the statement:
DI
Op Code: 8F
sets Control Register FBH to 0AH (00001010B) and disables these interrupts.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-29
DJNZ
DECREMENT AND JUMP IF NON-ZERO
DJNZ
Decrement and Jump if Non-zero
DJNZ r, dst
Instruction Format:
Operation:
r <-- r - 1;
If r <> 0, PC <-- PC + dst
The specified Working Register being used as a counter is decremented. If the contents of the specified Working
Register are not zero after decrementing, then the relative address is added to the Program Counter (PC) and control
passes to the statement whose address is now in the PC. The range of the relative address is +127 to 128. The
original value of the PC is the address of the instruction byte following the DJNZ statement. When the specified
Working Register counter reaches zero, control falls through to the statement following the DJNZ instruction.
Note:
The Working Register being used as a counter must be one of the Registers from 04H to EFH. Use of one of the
I/O ports, control or peripheral registers will have undefined results.
Example:
DJNZ is typically used to control a "loop" of instructions. In this example, 12 bytes are moved from one buffer area
in the register file to another. The steps involved are:
Load 12 into the counter (Working Register R6).
Set up the loop to perform the moves.
End the loop with DJNZ.
The assembly listing required for this routine is as follows:
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
LD R6, 12
;Load Counter
LOOP
:
LD R9, @R6
;Move one byte to
LD @R6, R9
;new location
DJNZ R6, LOOP
;Decrement and Loop until
counter = 0
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-30
UM001601-0803
EI
ENABLE INTERRUPTS
EI
Enable Interrupts
EI
Instruction Format:
Operation:
IMR (7) <-- 0
Bit 7 of Control Register FBH (the Interrupt Mask Register) is set to 1. This allows potentially enabled interrupts
to become enabled.
Example:
If Control Register FBH contains 0AH (00001010) (interrupts IRQ1 and IRQ3 are selected), the statement:
EI
Op Code: 9F
sets Control Register FBH to 8AH (10001010B) and enables IRQ1 and IRQ3.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-31
HALT
HALT
HALT
Halt
HALT
Instruction Format:
Operation:
The HALT instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and the
external interrupts IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally
or internally generated.
Note:
In order to enter HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in
mid-instruction. The user must execute a NOP immediately before the execution of the HALT instruction.
Example:
Assuming the Z8 is in normal operation, the statements:
NOP
HALT
Op Codes: FF 7F
place the Z8 into HALT mode.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-32
UM001601-0803
INC
INCREMENT
Inc
Increment
Instruction Format:
Operation:
dst <-- dst + 1
The contents of the destination operand are incremented by one.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If Working Register R10 contains 2AH, the statement:
INC R10
Op Code: AE
leaves the value 2BH in Working Register R10. The Z, V, and S Flags are cleared.
Example:
If Register B3H contains CBH, the statement:
INC B3H
Op Code: 20 B3
leaves the value CCH in Register CBH. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Register B3H contains CBH and Register BCH contains FFH, the statement:
INC @B3H
Op Code: 21 B3
leaves the value 00H in Register CBH. The Z Flag is set, and the V and S Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result of bit 7 is set (negative); cleared otherwise.
V:
Set if arithmetic overflow occurs; cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-33
INCW
INCREMENT WORD
INCW
Increment Word
INCW dst
Instruction Format:
Operation:
dst <-- dst - 1
The contents of the destination (which must be an even address) operand is decremented by one. The destination
operand can be a Register Pair or a Working Register Pair.
Note:
Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this format, the destination
Working Register Pair operand is specified by adding 1110B (EH) to the high nibble of the operand. For example,
if Working Register Pair R12 (CH) is the destination operand, then ECH will be used as the destination operand in
the Op Code
Example:
If Register Pairs 30H and 31H contain the value 0AF2H, the statement:
INCW 30H
Op Code: A0 30
leaves the value 0AF3H in Register Pair 30H and 31H. The Z, V, and S Flags are cleared.
Example:
If Working Register R0 contains 30H, and Register Pairs 30H and 31H contain the value FAF3H, the statement:
INCW @R0
Op Code: A1 E0
leaves the value FAF4H in Register Pair 30H and 31H. The S Flag is set, and the Z and V Flags are cleared.
OPC
dst
Cycles
OPC
Address Mode
(Hex)
dst
10
10
10
A0
A1
A0
RR
IR
R
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result of bit 7 is set (negative); cleared otherwise.
V:
Set if arithmetic overflow occurs; cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-34
UM001601-0803
IRET
INTERRUPT RETURN
IRET
Interrupt RETURN
IRET
Instruction Format:
Operation:
FLAGS <-- @SP
SP <-- SP + 1
PC <-- @SP
SP <-- SP + 2
IMR (7) <-- 1
This instruction is issued at the end of an interrupt service routine. It restores the Flag Register (Control Register
FCH) and the PC. It also re-enables any interrupts that are potentially enabled.
Example:
If Stack Pointer Low Register FFH currently contains the value 45H, Register 45H contains the value 00H, Register
46H contains 6FH, and Register 47 Contains E4H, the statement:
IRET
Op Code: BF
restores the FLAG Register FCH with the value 00H, restores the PC with the value 6FE4H, re-enables the
interrupts, and sets the Stack Pointer Low to 48H. The next instruction to be executed will be at location 6FE4H.
Flags:
C:
Restored to original setting before the interrupt occurred.
Z:
Restored to original setting before the interrupt occurred.
S:
Restored to original setting before the interrupt occurred.
V:
Restored to original setting before the interrupt occurred.
D:
Restored to original setting before the interrupt occurred.
H:
Restored to original setting before the interrupt occurred.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-35
JP
JUMP
JP
JUMP
JP cc, dst
Instruction Format:
Operation:
If cc (condition code) is true, then PC <-- dst
A conditional jump transfers Program Control to the destination address if the condition specified by cc (condition
code) is true. Otherwise, the instruction following the JP instruction is executed. See Section 12.3 for a list of
condition codes.
The unconditional jump simply replaces the contents of the Program Counter with the contents of the register pair
specified by the destination operand. Program Control then passes to the instruction addressed by the PC.
Note:
Address mode IRR can be used to specify a 4-bit Working Register. In this format, the destination Working Register
operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working Register
R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If the Carry Flag is set, the statement:
JP C, 1520H
Op Code: 7D 15 20
replaces the contents of the Program Counter with 1520H and transfers program control to that location. If the Carry
Flag had not been set, control would have fallen through to the statement following the JP instruction.
Example:
If Working Register Pair RR2 contains the value 3F45H, the statement:
JP @RR2
Op Code: 30 E2
replaces the contents of the PC with the value 3F45H and transfers program control to that location.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-36
UM001601-0803
JR
JUMP RELATIVE
JR
Jump Relative
JR cc, dst
Instruction Format:
Operation:
If cc is true, PC <-- PC + dst
If the condition specified by the "cc" is true, the relative address is added to the PC and control passes to the
instruction located at the address specified by the PC (See Section 12.3 for a list of condition codes). Otherwise, the
instruction following the JR instruction is executed. The range of the relative address is +127 to 128, and the
original value of the PC is taken to be the address of the first instruction byte following the JR instruction.
Example:
If the result of the last arithmetic operation executed is negative, the next four statements (which occupy a total of
seven bytes) are skipped with the statement:
JR Ml, #9
Op Code: 5B 09
If the result was not negative, execution would have continued with the instruction following the JR instruction.
Example:
A short form of a jump 45 is:
JR #45
Op Code: 8B D3
The condition code is "blank" in this case, and is assumed to be "always true."
dst
Cycles
OPC
Address Mode
(Hex)
dst
12 if jump taken
10 if jump not taken
ccB
cc = 0 to F
RA
cc
OPC
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-37
LD
LOAD
LD
Load
LD dst, src
Instruction Format:
Operation:
dst <-- src
The contents of the source operand are loaded into the destination operand. The contents of the source operand are
not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-38
UM001601-0803
LD
LOAD
Example:
The statement:
LD R15, #34H
Op Code: FC 34
loads the value 34H into Working Register R15.
Example:
If Register 34H contains the value FCH, the statement:
LD R14, 34H
Op Code: F8 34
loads the value FCH into Working Register R15. The contents of Register 34H are not affected.
Example:
If Working Register R14 contains the value 45H, the statement:
LD 34H, R14
Op Code: E9 34
loads the value 45H into Register 34H. The contents of Working Register R14 are not affected.
Example:
If Working Register R12 contains the value 34H, and Register 34H contains the value FFH, the statement:
LD R13, @R12
Op Code: E3 DC
loads the value FFH into Working Register R13. The contents of Working Register R12 and Register R34 are not
affected.
Example:
If Working Register R13 contains the value 45H, and Working Register R12 contains the value 00H the statement:
LD @R13, R12
Op Code: F3 DC
loads the value 00H into Register 45H. The contents of Working Register R12 and Working Register R13 are not
affected.
Example:
If Register 45H contains the value CFH, the statement:
LD 34H, 45H
Op Code: E4 45 34
loads the value CFH into Register 34H. The contents of Register 45H are not affected.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-39
LD
LOAD
Example:
If Register 45H contains the value CFH and Register CFH contains the value FFH, the statement:
LD 34H, @45H
Op Code: E5 45 34
loads the value FFH into Register 34H. The contents of Register 45H and Register CFH are not affected.
Example:
The statement:
LD 34H, #A4H
Op Code: E6 34 A4
loads the value A4H into Register 34H.
Example:
If Working Register R14 contains the value 7FH, the statement:
LD @R14, #FCH
Op Code: E7 EE FC
loads the value FCH into Register 7FH. The contents of Working Register R14 are not affected.
Example:
If Register 34H contains the value CFH and Register 45H contains the value FFH, the statement:
LD @34H, 45H
Op Code: F5 45 34
loads the value FFH into Register CFH. The contents of Register 34H and Register 45H are not affected.
Example:
IIf Working Register R0 contains the value 08H and Register 2CH (24H + 08H = 2CH) contains the value 4FH, the
statement:
LD R10, 24H(R0)
Op Code: C7 A0 24
loads Working Register R10 with the value 4FH. The contents of Working Register R0 and Register 2CH are not
affected.
Example:
If Working Register R0 contains the value 0BH and Working Register R10 contains 83H the statement:
LD F0H(R0), R10
Op Code: D7 A0 F0
loads the value 83H into Register FBH (F0H + 0BH = FBH). Since this is the Interrupt Mask Register, the LOAD
statement has the effect of enabling IRQ0 and IRQ1. The contents of Working Registers R0 and R10 are unaffected
by the load.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-40
UM001601-0803
LDC
LOAD CONSTANT
LDC
Load Constant
LDC dst, src
Instruction Format:
Operation:
dst <-- src
This instruction is used to load a byte constant from program memory into a Working Register, or vice versa. The
address of the program memory location is specified by a Working Register Pair. The contents of the source operand
are not affected.
Example:
If Working Register Pair R6 and R7 contain the value 30A2H and program memory location 30A2H contains the
value 22H, the statement:
LDC R2, @RR6
Op Code: C2 26
loads the value 22H into Working Register R2. The value of program memory location 30A2H is unchanged by the
load.
Example:
If Working Register R2 contains the value 22H, and Working Register Pair R6 and R7 contains the value 10A2H,
the statement:
LDC @RR6, R2
Op Code: D2 26
loads the value 22H into program memory location 10A2H. The value of Working Register R2 is unchanged by the
load.
Note: This instruction format is valid only for MCUs which can address external program memory.
Cycles
OPC
Address Mode
(Hex)
dst src
12
D2 Irr r
12
C2 r Irr
OPC
OPC
dst src
src dst
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-41
LDCI
LOAD CONSTANT AUTO-INCREMENT
LDCI
Load Constant Auto-increment
LDCI dst, src
Instruction Format:
Operation:
dst <-- src
r <-- r + 1
rr <-- rr + 1
This instruction is used for block transfers of data between program memory and the Register File. The address of
the program memory location is specified by a Working Register Pair, and the address of the Register File location
is specified by Working Register. The contents of the source location are loaded into the destination location. Both
addresses in the Working Registers are then incremented automatically. The contents of the source operand are not
affected.
Example:
If Working Register Pair R6-R7 contains 30A2H, program memory location 30A2H and 30A3H contain 22H and
BCH respectively, and Working Register R2 contains 20H, the statement:
LDCI @R2, @RR6
Op Code: C3 26
loads the value 22H into Register 20H. Working Register Pair RR6 is incremented to 30A3H and Working Register
R2 is incremented to 21H. A second
LDCI @R2, @RR6
Op Code: C3 26
loads the value BCH into Register 21H. Working Register Pair RR6 is incremented to 30A4H and Working Register
R2 is incremented to 22H.
Cycles
OPC
Address Mode
(Hex)
dst src
18
D2 Irr Ir
18
C2 Ir Irr
OPC
OPC
dst src
src dst
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-42
UM001601-0803
LDCI
LOAD CONSTANT AUTO-INCREMENT
Example:
If Working Register R2 contains 20H, Register 20H contains 22H, Register 21H contains BCH, and Working
Register Pair R6-R7 contains 30A2H, the statement:
LDCI @RR6, @R2
Op Code: D3 26
loads the value 22H into program memory location 30A2H. Working Register R2 is incremented to 21H and
Working Register Pair R6-R7 is incremented to 30A3H. A second
LDCI @RR6, @R2
Op Code: D3 26
loads the value BCH into program memory location 30A3H. Working Register R2 is incremented to 22H and
Working Register Pair R6-R7 is incremented to 30A4H.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-43
LDE
LOAD EXTERNAL DATA
LDE
Load External Data
LDE dst, src
Instruction Format:
Operation:
dst <-- src
This instruction is used to load a byte from external data memory into a Working Register or vice versa. The address
of the external data memory location is specified by a Working Register Pair. The contents of the source operand
are not affected.
Example:
If Working Register Pair R6 and R7 contain the value 40A2H and external data memory location 40A2H contains
the value 22H, the statement:
LDE R2, @RR6
Op Code: 82 26
loads the value 22H into Working Register R2. The value of external data memory location 40A2H is unchanged
by the load.
Example:
If Working Register Pair R6 and R7 contain the value 404AH and Working Register R2 contains the value 22H,
the statement:
LDE @RR6, R2
Op Code: 92 26
loads the value 22H into external data memory location 404AH
Note: This instruction format is valid only for MCUs which can address external data memory.
Cycles
OPC
Address Mode
(Hex)
dst src
12
92 Irr r
12
82 r Irr
OPC
OPC
dst src
src dst
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-44
UM001601-0803
LDEI
LOAD EXTERNAL DATA AUTO-INCREMENT
LDEI
Load External Data Auto-increment
LDEI dst, src
Instruction Format:
Operation:
dst <-- src
r <-- r + 1
rr <-- rr + 1
This instruction is used for block transfers of data between external data memory and the Register File. The address
of the external data memory location is specified by a Working Register Pair, and the address of the Register File
location is specified by a Working Register. The contents of the source location are loaded into the destination
location. Both addresses in the Working Registers are then incremented automatically. The contents of the source
are not affected.
Example:
If Working Register Pair R6 and R7 contains 404AH, external data memory location 404AH and 404BH contain
ABH and C3H respectively, and Working Register R2 contains 22H, the statement:
LDEI @R2, @RR6
Op Code: 83 26
loads the value ABH into Register 22H. Working Register Pair RR6 is incremented to 404BH and Working Register
R2 is incremented to 23H. A second
LDEI @R2, @RR6
Op Code: 83 26
loads the value C3H into Register 23H. Working Register Pair RR6 is incremented to 404CH and Working Register
R2 is incremented to 24H.
Cycles
OPC
Address Mode
(Hex)
dst src
18
93 Irr Ir
18
83 Ir Irr
OPC
OPC
dst src
src dst
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-45
LDEI
LOAD EXTERNAL DATA AUTO-INCREMENT
Example:
If Working Register R2 contains 22H, Register 22H contains ABH, Register 23H contains C3H, and Working
Register Pair R6 and R7 contains 404AH, the statement:
LDEI @RR6, @R2
Op Code: 93 26
loads the value ABH into external data memory location 404AH. Working Register R2 is incremented to 23H and
Working Register Pair RR6 is incremented to 404BH. A second
LDEI @RR6, @R2
Op Code: 93 26
loads the value C3H into external data memory location 404BH. Working Register R2 is incremented to 24H and
Working Register Pair RR6 is incremented to 404CH.
Note: This instruction format is valid only for MCUs which can address external data memory.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-46
UM001601-0803
NOP
NO OPERATION
NOP
No Operation
NOP
Instruction Format:
Operation
No action is performed by this instruction. It is typically used for timing delays or clearing the pipeline.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-47
OR
LOGICAL OR
OR
Logical OR
OR dst, src
Instruction Format:
Operation:
dst <-- dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the destination
operand. The contents of the source operand are not affected. The OR operation results in a one bit being stored
whenever either of the corresponding bits in the two operands is a one. Otherwise, a zero bit is stored.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R1 contains 34H (00111000B) and Working Register R14 contains 4DH (10001101), the
statement:
OR R1, R14
Op Code: 42 1E
leaves the value BDH (10111101B) in Working Register R1. The S Flag is set, and the Z and V Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise
S:
Set if the result of bit 7 is set; cleared otherwise
V:
Always reset to 0
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-48
UM001601-0803
OR
LOGICAL OR
Example:
If Working Register R4 contains F9H (11111001B), Working Register R13 contains 7BH, and Register 7B contains
6AH (01101010B), the statement:
OR R4, @R13
Op Code: 43 4D
leaves the value FBH (11111011B) in Working Register R4. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Register 3AH contains the value F5H (11110101B) and Register 42H contains the value 0AH (00001010), the
statement:
OR 3AH, 42H
Op Code: 44 42 3A
leaves the value FFH (11111111B) in Register 3AH. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Working Register R5 contains 70H (01110000B), Register 45H contains 3AH, and Register 3AH contains 7FH
(01111111B), the statement:
OR R5, @45H
Op Code: 45 45 E5
leaves the value 7FH (01111111B) in Working Register R5. The Z, V, and S Flags are cleared.
Example:
If Register 7AH contains the value F3H (11110111B), the statement:
OR 7AH, #F0H
Op Code: 46 7A F0
leaves the value F3H (11110111B) in Register 7AH. The S Flag is set, and the Z and V Flags are cleared.
Example:
If Working Register R3 contains the value 3EH and Register 3EH contains the value 0CH (00001100B), the
statement:
OR @R3, #05H
Op Code: 57 E3 05
leaves the value 0DH (00001101B) in Register 3EH. The Z, V, and S Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-49
POP
POP
POP
Pop
POP dst
Instruction Format:
Operation:
dst <-- @SP
SP <-- SP + 1
The contents of the location specified by the SP (Stack Pointer) are loaded into the destination operand. The SP is
then incremented automatically.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If the SP (Control Registers FEH and FFH) contains the value 70H and Register 70H contains 44H, the statement:
POP 34H
Op Code: 50 34
loads the value 44H into Register 34H. After the POP operation, the SP contains 71H. The contents of Register 70
are not affected.
Example:
If the SP (Control Registers FEH and FFH) contains the value 1000H, external data memory location 1000H
contains 55H, and Working Register R6 contains 22H, the statement:
POP @R6
Op Code: 51 E6
loads the value 55H into Register 22H. After the POP operation, the SP contains 1001H. The contents of Working
Register R6 are not affected.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-50
UM001601-0803
PUSH
PUSH
PUSH
Push
PUSH src
Instruction Format:
Operation:
SP <-- SP - 1
@SP <-- src
The contents of the SP (stack pointer) are decremented by one, then the contents of the source operand are loaded
into the location addressed by the decremented SP, thus adding a new element to the stack.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If the SP contains 1001H, the statement:
PUSH FCH
Op Code: 70 FC
stores the contents of Register FCH (the Flag Register) in location 1000H. After the PUSH operation, the SP
contains 1000H.
Example:
If the SP contains 61H and Working Register R4 contains FCH, the statement:
PUSH @R4
Op Code: 71 E4
stores the contents of Register FCH (the Flag Register) in location 60H. After the PUSH operation, the SP contains
60H.
OPC
src
Cycles
OPC
(Hex)
Address Mode
dst
R
IR
10 Internal Stack
12 External Stack
10 Internal Stack
10 External Stack
70
71
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-51
RCF
RESET CARRY FLAG
RCF
Reset Carry Flag
RCF
Instruction Format:
Operation:
C <-- 0
The C Flag is reset to 0, regardless of its previous value.
Example:
If the C Flag is currently set, the statement:
RCF
Op Code: CF
resets the Carry Flag to 0.
Flags:
C:
Reset to 0
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-52
UM001601-0803
RET
RETURN
RET
Return
RET
Instruction Format:
Operation:
PC <-- @SP
SP <-- SP + 2
This instruction is normally used to return from a procedure entered by a CALL instruction. The contents of the
location addressed by the SP are popped into the PC. The next statement executed is the one addressed by the new
contents of the PC. The stack pointer is also incremented by two.
Note:
Each PUSH instruction executed within the subroutine should be countered with a POP instruction in order to
guarantee the SP is at the correct location when the RET instruction is executed. Otherwise the wrong address will
be loaded into the PC and the program will not operate as desired.
Example:
If SP contains 2000H, external data memory location 2000H contains 18H, and location 2001H contains B5H, the
statement:
RET
Op Code: AF
leaves the value 2002H in the SP, and the PC contains 18B5H, the address of the next instruction to be executed.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-53
RL
ROTATE LEFT
RL
Rotate Left
RL dst
Instruction Format:
Operation:
C <-- dst(7)
dst(0) <-- dst(7)
dst(1) <-- dst(0)
dst(2) <-- dst(1)
dst(3) <-- dst(2)
dst(4) <-- dst(3)
dst(5) <-- dst(4)
dst(6) <-- dst(5)
dst(7) <-- dst(6)
The contents of the destination operand are rotated left by one bit position. The initial value of bit 7 is moved to the
bit 0 position and also into the Carry Flag.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags:
C:
Set if the bit rotated from the most significant bit position was 1 ( i.e., bit 7 was 1).
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result in bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation);
cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-54
UM001601-0803
RL
ROTATE LEFT
Example:
If the contents of Register C6H are 88H (10001000B), the statement:
RL C6H
Op Code: 80 C6
leaves the value 11H (00010001B) in Register C6H. The C and V Flags are set, and the S and Z Flags are cleared.
Example:
If the contents of Register C6H are 88H, and the contents of Register 88H are 44H (01000100B), the statement:
RL @C6H
Op Code: 81 C6
leaves the value 88H in Register 88H (10001000B). The S and V Flags are set, and the C and Z Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-55
RLC
ROTATE LEFT THROUGH CARRY
RLC
Rotate Left Through Carry
RLC dst
Instruction Format:
Operation:
C<-- dst(7)
dst(0) <-- C
dst(1) <-- dst(0)
dst(2) <-- dst(1)
dst(3) <-- dst(2)
dst(4) <-- dst(3)
dst(5) <-- dst(4)
dst(6) <-- dst(5)
dst(7) <-- dst(6)
The contents of the destination operand along with the C Flag are rotated left by one bit position. The initial value
of bit 7 replaces the C Flag and the initial value of the C Flag replaces bit 0.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags:
C:
Set if the bit rotated from the most significant bit position was 1 (i.e., bit 7 was 1).
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation);
cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-56
UM001601-0803
RLC
ROTATE LEFT THROUGH CARRY
Example:
If the C Flag is reset and Register C6 contains 8F (10001111B), the statement:
RLC C6
Op Code: 10 C6
leaves Register C6 with the value 1EH (00011110B). The C and V Flags are set, and S and Z Flags are cleared.
Example:
If the C Flag is reset, Working Register R4 contains C6H, and Register C6 contains 8F (10001111B), the statement:
RLC @R4
Op Code: 11 E4
leaves Register C6 with the value 1EH (00011110B). The C and V Flags are set, and S and Z Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-57
RR
ROTATE RIGHT
RR
Rotate Right
RR dst
Instruction Format:
Operation:
C <-- dst(0)
dst(0) <-- dst(1)
dst(1) <-- dst(2)
dst(2) <-- dst(3)
dst(3) <-- dst(4)
dst(4) <-- dst(5)
dst(5) <-- dst(6)
dst(6) <-- dst(7)
dst(7) <-- dst(0)
The contents of the destination operand are rotated to the right by one bit position. The initial value of bit 0 is moved
to bit 7 and also into the C Flag.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags:
C:
Set if the bit rotated from the least significant bit position was 1 ( i.e., bit 0 was 1).
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation);
cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-58
UM001601-0803
RR
ROTATE RIGHT
Example:
If the contents of Working Register R6 are 31H (00110001B), the statement:
RR R6
Op Code: E0 E6
leaves the value 98H (10011000) in Working Register R6. The C, V, and S Flags are set, and the Z Flag is cleared.
Example:
If the contents of Register C6 are 31H and the contents of Register 31H are 7EH (01111110B), the statement:
RR @C6
Op Code: E1 C6
leaves the value 4FH (00111111) in Register 31H. The C, Z, V, and S Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-59
RRC
ROTATE RIGHT THROUGH CARRY
RRC
Rotate Right Through Carry
RRC dst
Instruction Format:
Operation:
C <-- dst(0)
dst(0) <-- dst(1)
dst(1) <-- dst(2)
dst(2) <-- dst(3)
dst(3) <-- dst(4)
dst(4) <-- dst(5)
dst(5) <-- dst(6)
dst(6) <-- dst(7)
dst(7) <-- C
The contents of the destination operand with the C Flag are rotated right by one bit position. The initial value of bit
0 replaces the C Flag and the initial value of the C Flag replaces bit 7.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags:
C:
Set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1).
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred (if the sign of the destination operand changed during rotation);
cleared otherwise.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-60
UM001601-0803
RRC
ROTATE RIGHT THROUGH CARRY
Example:
If the contents of Register C6H are DDH (11011101B) and the C Flag is reset, the statement:
RRC C6H
Op Code: C0 C6
leaves the value 6EH (01101110B) in register C6H. The C and V Flags are set, and the Z and S Flags are cleared.
Example:
If the contents of Register 2C are EDH, the contents of Register EDH is 00H (00000000B), and the C Flag is reset,
the statement:
RRC @2CH
Op Code: C1 2C
leaves the value 02H (00000010B) in Register EDH. The C, Z, S, and V Flags are reset.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-61
SBC
SUBTRACT WITH CARRY
SBC
Subtract With Carry
SBC dst, src
Instruction Format:
Operation:
dst <-- dst - src - C
The source operand, along with the setting of the C Flag, is subtracted from the destination operand and the result
is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed
by adding the two's complement of the source operand to the destination operand. In multiple precision arithmetic,
this instruction permits the carry (borrow) from the subtraction of low order operands to be subtracted from the
subtraction of high order operands.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Flags:
C:
Cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a
"borrow."
Z:
Set if the result is 0; cleared otherwise.
V:
Set if arithmetic overflow occurred (if the operands were of opposite sign and the sign of the result is the
same as the sign of the source); reset otherwise.
S:
Set if the result is negative; cleared otherwise.
H:
Cleared if there is a carry from the most significant bit of the low order four bits of the result; set
otherwise indicating a "borrow."
D:
Always set to 1.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-62
UM001601-0803
SBC
SUBTRACT WITH CARRY
Example:
Working Register R3 contains 16H, the C Flag is set to 1, and Working Register R11 contains 20H, the statement:
SBC R3, R11
Op Code: 32 3B
leaves the value F5H in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are all
cleared.
Example:
If Working Register R15 contains 16H, the C Flag is not set, Working Register R10 contains 20H, and Register 20H
contains 11H, the statement:
SBC R16, @R10
Op Code: 33 FA
leaves the value 05H in Working Register R15. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example
:If Register 34H contains 2EH, the C Flag is set, and Register 12H contains 1BH, the statement:
SBC 34H, 12H
Op Code: 34 12 34
leaves the value 13H in Register 34H. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register 4BH contains 82H, the C Flag is set, Working Register R3 contains 10H, and Register 10H contains
01H, the statement:
SBC 4BH, @R3
Op Code: 35 E3 4B
leaves the value 80H in Register 4BH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register 6CH contains 2AH, and the C Flag is not set, the statement:
SBC 6CH, #03H
Op Code: 36 6C 03
leaves the value 27H in Register 6CH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register D4H contains 5FH, Register 5FH contains 4CH, and the C Flag is set, the statement:
SBC @D4H, #02H
Op Code: 37 D4 02
leaves the value 4AH in Register 5FH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-63
SCF
SET CARRY FLAG
SCF
Set Carry Flag
SRC
Instruction Format:
Operation:
C <-- 1
The C Flag is set to 1, regardless of its previous value.
Example:
If the C Flag is currently reset, the statement:
SCF
Op Code: DF
sets the Carry Flag to 1.
Flags:
C:
Set to 1
Z
Unaffected
S
Unaffected
V
Unaffected
D
Unaffected
H
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-64
UM001601-0803
SRA
SHIFT RIGHT ARITHMETIC
SRA
Shift Right Arithmetic
SRA dst
Instruction Format:
Operation:
C <-- dst(0)
dst(0) <-- dst(1)
dst(1) <-- dst(2)
dst(2) <-- dst(3)
dst(3) <-- dst(4)
dst(4) <-- dst(5)
dst(5) <-- dst(6)
dst(6) <-- dst(7)
dst(7) <-- dst(7)
An arithmetic shift right by one bit position is performed on the destination operand. Bit 0 replaces the C Flag. Bit
7 (the Sign bit) is unchanged and its value is shifted into bit 6.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Flags:
C:
Set if the bit rotated from the least significant bit position was 1 (i.e., bit 0 was 1).
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to 0.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-65
SRA
SHIFT RIGHT ARITHMETIC
Example:
If the contents of Working Register R6 are 31H (00110001B), the statement:
SRA R6
Op Code: D0 E6
leaves the value 98H (00011000) in Working Register R6. The C Flag is set, and the Z, V, and S Flags are cleared.
Example:
If Register C6 contains the value DFH, and Register DFH contains the value B8H (10111000B), the statement:
SRA @C6
Op Code: D1 C6
leaves the value DCH (11011100B) in Register DFH. The C, Z, and V Flags are reset, and the S Flag is set.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-66
UM001601-0803
SRP
SET REGISTER POINTER
SRP
Set Register Pointer
SRP src
Instruction Format:
Operation:
RP <-- src
The specified value is loaded into the Register Pointer (RP) (Control Register FDH). Bits 7-4 determine the
Working Register Group. Bits 3-0 selects the Expanded Register Bank. Addressing of un-implemented Working
Register Group, while using Expanded Register Banks, will point to Bank 0.
Example: SRP TD addresses Working Register Group 7 of Bank 0.
Register Pointer
Working
Actual
(FDH)
Register Group
Registers
Contents (Bin)
(Hex)
(Hex)
1111 0000
F
F0-FF
1110 0000
E
E0-EF
1101 0000
D
D0-DF
1100 0000
C
C0-CF
1011 0000
B
B0-BF
1010 0000
A
A0-AF
1001 0000
9
90-9F
1000 0000
8
80-8F
0111 0000
7
70-7F
0110 0000
6
60-6F
0101 0000
5
50-5F
0100 0000
4
40-4F
0011 0000
3
30-3F
0010 0000
2
20-2F
0001 0000
1
10-1F
0000 0000
0
00-0F
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-67
SRP
SET REGISTER POINTER
Note:
When an Expanded Register Bank , other than Bank 0 is selected, access to the Z8 Standard Register File is possible
except for the Port Register and general purpose registers 04H to 0FH.
fpr Register Addresses 0H to FH.
Example:
The statement:
SRP F0H Op Code: 31 F0
sets the Register Pointer to access expanded Register Bank 0 and Working Register Group F in the Z8 Standard
Register File. All references to Working Registers now affect this group of 16 registers. Registers F0H to FFH can
be accessed as Working Registers R0 to R15
Example:
The statement:
SRP 0FH
Op Code: 31 0F
sets the Register Pointer to access Expanded Register Bank F, Reg 00H to Reg 0FH, as the current Working
Registers. All references to Working Registers now affect this group of 16 registers. These registers are now
accessed as Working Registers R0 to R15. Port Registers are now not accessable.
Register Pointer
Expanded
(FDH)
Register Bank
Contents (Hex)
(Hex)
xxxx 1111
F
xxxx 1110
E
xxxx 1101
D
xxxx 1100
C
xxxx 1011
B
xxxx 1010
A
xxxx 1001
9
xxxx 1000
8
xxxx 0111
7
xxxx 0110
6
xxxx 0101
5
xxxx 0100
4
xxxx 0011
3
xxxx 0010
2
xxxx 0001
1
xxxx 0000
0
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-68
UM001601-0803
SRP
SET REGISTER POINTER
Example:
Assume the RP currently addresses the Control and Peripheral Working Register Group and the program has just
entered an interrupt service routine. The statement:
SRP 70H
Op Code: 31 70
retains the contents of the Control and Peripheral Registers by setting the RP to 70H (01110000B). Any reference
to Working Registers in the interrupt routine will point to registers 70H to 7FH.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-69
STOP
STOP
STOP
Stop
STOP
Instruction Format:
Operation:
This instruction turns off the internal system clock (SCLK) and external crystal (XTAL) oscillation, and reduces
the standby current. The STOP mode is terminated by a RESET which causes the processor to restart the application
program at address 000CH.
Note:
In order to enter STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in
mid-instruction. The user must execute a NOP immediately before the execution of the STOP instruction.
Example:
The statements:
NOP
STOP
Op Codes: FF 6F
place the Z8 into STOP mode.
Flags:
C:
Unaffected
Z:
Unaffected
S:
Unaffected
V:
Unaffected
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-70
UM001601-0803
SUB
SUBTRACT
SUB
Subtract
SUB dst, src
Instruction Format:
Operation:
dst <-- dst - src
The source operand is subtracted from the destination operand and the result is stored in the destination operand.
The contents of the source operand are not affected. Subtraction is performed by adding the two's complement of
the source operand to the destination operand.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
]If Working Register R3 contains 16H, and Working Register R11 contains 20H, the statement:
SUB R3, R11
Op Code: 22 3B
leaves the value F6H in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are cleared.
Flags:
C:
Cleared if there is a carry from the most significant bit of the result; set otherwise, indicating a "borrow."
Z:
Set if the result is 0; cleared otherwise.
V:
Set if arithmetic overflow occurred (if the operands were of opposite sign and the sign of the result is the
same as the sign of the source); reset otherwise.
S:
Set if the result is negative; cleared otherwise.
H:
Cleared if there is a carry from the most significant bit of the low order four bits of the result; set
otherwise indicating a "borrow."
D:
Always set to 1.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-71
SUB
SUBTRACT
Example:
If Working Register R15 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11H, the
statement:
SUB R16, @R10
Op Code: 23 FA
leaves the value 05H in Working Register R15. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register 34H contains 2EH, and Register 12H contains 1BH, the statement:
SUB 34H, 12H
Op Code: 24 12 34
leaves the value 13H in Register 34H. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register 4BH contains 82H, Working Register R3 contains 10H, and Register 10H contains 01H, the statement:
SUB 4BH, @R3
Op Code: 25 E3 4B
leaves the value 81H in Register 4BH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register 6CH contains 2AH, the statement:
SUB 6CH, #03H
Op Code: 26 6C 03
leaves the value 27H in Register 6CH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Example:
If Register D4H contains 5FH, Register 5FH contains 4CH, the statement:
SUB @D4H, #02H
Op Code: 17 D4 02
leaves the value 4AH in Register 5FH. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-72
UM001601-0803
SWAP
SWAP NIBBLES
SWAP
Swap Nibbles
SWAP dst
Instruction Format:
Operation:
dst(7-4) <--> dst(3-0)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
Example:
If Register BCH contains B3H (10110011B), the statement:
SWAP B3H
Op Code: F0 B3
will leave the value 3BH (00111011B) in Register BCH. The Z and S Flags are cleared.
Example:
If Working Register R5 contains BCH and Register BCH contains B3H (10110011B), the statement:
SWAP @R5H
Op Code: F1 E5
will leave the value 3BH (00111011B) in Register BCH. The Z and S Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Undefined
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-73
TCM
TEST COMPLEMENT UNDER MASK
TCM
Test Complement Under Mask
TCM dst, src
Instruction Format:
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified
by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TCM instruction
complements the destination operand, and then ANDs it with the source mask (operand). The Zero (Z) Flag can
then be checked to determine the result. If the Z Flag is set, then the tested bits were 1. When the TCM operation
is complete, the destination and source operands still contain their original values.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to 0.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-74
UM001601-0803
TCM
TEST COMPLEMENT UNDER MASK
Example:
If Working Register R3 contains 45H (01000101B) and Working Register R7 contains the value 01H (00000001B)
(bit 0 is being tested if it is 1), the statement:
TCM R3, R7
Op Code: 62 37
will set the Z Flag indicating bit 0 in the destination operand is 1. The V and S Flags are cleared.
Example:
If Working Register R14 contains the value F3H (11110011B), Working Register R5 contains CBH, and Register
CBH contains 88H (10001000B) (bit 7 and bit 3 are being tested if they are 1), the statement:
TCM R14, @R5
Op Code: 63 E5
will reset the Z Flag, because bit 3 in the destination operand is not a 1. The V and S Flags are also cleared.
Example:
If Register D4H contains the value 04H (000001000B), and Working Register R0 contains the value 80H
(10000000B) (bit 7 is being tested if it is 1), the statement:
TCM D4H, R0
Op Code: 64 E0 D4
will reset the Z Flag, because bit 7 in the destination operand is not a 1. The S Flag will be set, and the V Flag will
be cleared.
Example:
If Register DFH contains the value FFH (11111111B), Register 07H contains the value 1FH, and Register 1FH
contains the value BDH (10111101B) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 1), the
statement:
TCM DFH, @07H
Op Code: 65 07 DF
will set the Z Flag indicating the tested bits in the destination operand are 1. The S and V Flags are cleared.
Example:
If Working Register R13 contains the value F2H (11110010B), the statement:
TCM R13, #02H
Op Code: 66 ED, 02
tests bit 1 of the destination operand for 1. The Z Flag will be set indicating bit 1 in the destination operand was 1.
The S and V Flags are cleared.
Example:
If Register 5DH contains A0H, and Register A0H contains 0FH (00001111B), the statement:
TCM @5D, #10H
Op Code: 67 5D 10
tests bit 4 of the Register A0H for 1. The Z Flag will be reset indicating bit 1 in the destination operand was not 1.
The S and V Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-75
TM
TEST UNDER MASK
TM
Test Under Mask
TM dst, src
Instruction Format:
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a 0 logical value. The bits to be tested are specified
by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TM instruction ANDs the
destination operand with the source operand (the mask). The Zero (Z) Flag can then be checked to determine the
result. If the Z Flag is set, then the tested bits were 0. When the TM operation is complete, the destination and source
operands still contain their original values.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R3 contains 45H (01000101B) and Working Register R7 contains the value 02H (00000010B)
(bit 1 is being tested if it is 0), the statement:
TM R3, R7
Op Code: 72 37
will set the Z Flag indicating bit 1 in the destination operand is 0. The V and S Flags are cleared.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to 0.
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-76
UM001601-0803
TM
TEST UNDER MASK
Example
Working Register R14 contains the value F3H (11110011B), Working Register R5 contains CBH, and Register
CBH contains 88H (10001000B) (bit 7 a bit 3 are being tested if they are 0), the statement:
TM R14, @R5
Op Code: 73 E5
will reset the Z Flag, because bit 7 iin the destination operand is not a 0. The S Flag will be set, and the V Flag is
cleared.
Example:
If Register D4H contains the value 08H (00001000B), and Working Register R0 contains the value 04H
(00000100B) (bit 2 is being tested if it is 0), the statement:
TM D4H, R0
Op Code: 74 E0 D4
will set the Z Flag, because bit 2 in the destination operand is a 0. The S and V Flags will be cleared.
Example:
If Register DFH contains the value 00H (00000000B), Register 07H contains the value 1FH, and Register 1FH
contains the value BDH (10111101B) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 0), the
statement:
TM DFH, @07H
Op Code: 75 07 DF
will set the Z Flag indicating the tested bits in the destination operand are 0. The S is set, and the V Flag is cleared.
Example:
If Working Register R13 contains the value F1H (11110001B), the statement:
TM R13, #02H
Op Code: 76 ED, 02
tests bit 1 of the destination operand for 0. The Z Flag will be set indicating bit 1 in the destination operand was 0.
The S and V Flags are cleared.
Example:
If Register 5DH contains A0H, and Register A0H contains 0FH (00001111B), the statement:
TM @5D, #10H
Op Code: 77 5D 10
tests bit 4 of the Register A0H for 0. The Z Flag will be set indicating bit 4 in the destination operand was 0. The S
and V Flags are cleared.
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-77
WDH
WATCH-DOG TIMER ENABLE DURING HALT MODE
WDH
Watch-Dog Timer Enable During HALT Mode
WDH
Instruction Format:
Operation:
When this instruction is executed it will enable the WDT (Watch-Dog Timer) during HALT mode. If this
instruction is not executed the WDT will stop when entering HALT mode. This instruction does not clear the
counter, it just makes it possible to have the WDT function running during HALT mode. A WDH instruction
executed without executing WDT (5FH) has no effect.
Note:
The WDH instruction should not be used following any instruction in which the condition of the flags is important.
Example:
If the WDT is enabled, the statement:
WDH
Op Code: .BYTE 4FH
will enable the WDT in HALT mode.
Note: This instruction format is valid only for the Z86C04/C08 and Z86E04/E07/E08.
Flags:
C:
Unaffected
Z:
Undefined
S:
Undefined
V:
Undefined
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-78
UM001601-0803
WDT
WATCH-DOG TIMER
WDT
Watch-Dog Timer
WDT
Instruction Format:
Operation:
The WDT (Watch-Dog Timer) is a retriggerable one shot timer that will reset the Z8 if it reaches its terminal count.
The WDT is initially enabled by executing the WDT instruction. Each subsequent execution of the WDT instruction
refreshes the timer and prevents the WDT from timing out.
Note:
The WDT instruction should not be used following any instruction in which the condition of the flags is important.
Example:
If the WDT is enabled, the statement:
WDT
Op Code: .BYTE 5FH
refreshes the Watch-Dog Timer.
Example:
The first execution of the statement:
WDT
Op Code: .BYTE 5FH
enables the Watch-Dog Timer.
Flags:
C:
Unaffected
Z:
Undefined
S:
Undefined
V:
Undefined
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001601-0803
12-79
XOR
LOGICAL EXCLUSIVE OR
XOR
Logical Exclusive OR
XOR dst, src
Instruction Format:
Operation:
dst <-- dst XOR src
The source operand is logically EXCLUSIVE ORed with the destination operand. The XOR operation results in a
1 being stored in the destination operand whenever the corresponding bits in the two operands are different,
otherwise a 0 is stored. The contents of the source operand are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R1 contains 34H (00111000B) and Working Register R14 contains 4DH (10001101B), the
statement:
XOR R1, R14
Op Code: B2 1E
leaves the value BDH (10111101B) in Working Register R1. The Z, and V Flags are cleared, and the S Flag is set.
Flags:
C:
Unaffected
Z:
Set if the result is zero; cleared otherwise.
S:
Set if the result of bit 7 is set; cleared otherwise.
V:
Always reset to 0
D:
Unaffected
H:
Unaffected
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-80
UM001601-0803
XOR
LOGICAL EXCLUSIVE OR
Example
If Working Register R4 contains F9H (11111001B), Working Register R13 contains 7BH, and Register 7B contains
6AH (01101010B), the statement:
XOR R4, @R13
Op Code: B3 4D
leaves the value 93H (10010011B) in Working Register R4. The S Flag is set, and the Z, and V Flags are cleared.
Example:
If Register 3AH contains the value F5H (11110101B) and Register 42H contains the value 0AH (00001010B), the
statement:
XOR 3AH, 42H
Op Code: B4 42 3A
leaves the value FFH (11111111B) in Register 3AH. The S Flag is set, and the C and V Flags are cleared.
Example:
If Working Register R5 contains F0H (11110000B), Register 45H contains 3AH, and Register 3A contains 7F
(01111111B), the statement:
XOR R5, @45H
Op Code: B5 45 E5
leaves the value 8FH (10001111B) in Working Register R5. The S Flag is set, and the C and V Flags are cleared.
Example:
If Register 7AH contains the value F7H (11110111B), the statement:
XOR 7AH, #F0H
Op Code: B6 7A F0
leaves the value 07H (00000111B) in Register 7AH. The Z, V and S Flags are cleared.
Example:
If Working Register R3 contains the value 3EH and Register 3EH contains the value 6CH (01101100B), the
statement:
XOR @R3, #05H
Op Code: B7 E3 05
leaves the value 69H (01101001B) in Register 3EH. The Z, V, and S Flags are cleared.