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Электронный компонент: Z86C4312VEC

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DS007601-Z8X0499
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86C34/C35/C36
Z86C44/C45/C46
CMOS Z8
MCU
S
WITH
ASCI UART
O
FFER
E
FFICIENT
, C
OST
-E
FFECTIVE
D
ESIGN
F
LEXIBILITY
FEATURES
28-Pin DIP, 28-Pin SOIC and PLCC Packages (C34,
C35, C36)
40-Pin DIP, 44-Pin PLCC and QFP Packages (C44,
C45, C46)
3.0- to 5.5-Volt Operating Range
Clock Free Watch-Dog Timer (WDT) Reset
Operating Temperature Ranges:
Standard: 0
C to 70
C
Extended: 40
C to +105
C
Expanded Register File (ERF)
Full-Duplex UART (ASCI)
Dedicated 16-Bit Baud Rate Generator
32 Input/Output Lines (C44/C45/C46)
24 Input/Output Lines (C34/C35/C36)
Vectored, Prioritized Interrupts with Programmable Po-
larity
Two Analog Comparators
Two Programmable 8-Bit Counter/Timers, Each with
Two 6-Bit Programmable Prescaler
Watch-Dog Timer (WDT)/Power-On Reset (POR)
On-Chip Oscillator that Accepts a Crystal, Ceramic Res-
onator, LC, RC, or External Clock
RAM and ROM Protect
Optional 32-kHz Oscillator
GENERAL DESCRIPTION
ZiLOG's Z8
MCU single-chip family now includes the
Z86C34/C35/C36/C44/C45/C46 product line, featuring en-
hanced wake-up circuitry, programmable Watch-Dog Tim-
ers (
WDT
), and low-noise/EMI options. Each of the new en-
hancements to the Z8 offer a more efficient, cost-effective
design and provide the user with increased design flexibility
over the standard Z8 microcontroller core. The low-power
consumption CMOS microcontroller offers fast execution,
efficient use of memory, sophisticated interrupts, input/out-
put bit manipulation capabilities, and easy hardware/soft-
ware system expansion.
The Z8 subfamily features an Expanded Register File (
ERF
)
to allow access to register-mapped peripheral and I/O cir-
cuits. Four basic address spaces are available to support this
wide range of configurations: Program Memory, Register
File, Data Memory, and
ERF
. The Register File is composed
of 236/237 bytes of general-purpose registers, four I/O port
registers, and 15 control and status registers. The
ERF
con-
sists of twelve control registers.
For applications demanding powerful I/O capabilities, the
Z86C34/C35/C36 offers 24 pins, and the Z86C44/C45/C46
offers 32 pins dedicated to input and output. These lines are
Device
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Z86C34
16
237
16
Z86C35
32
237
16
Z86C36
64
237
16
Z86C44
16
236
16
Z86C45
32
236
16
Z86C46
64
236
16
Note:
*General-Purpose.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
2
P R E L I M I N A R Y
DS007601-Z8X0499
GENERAL DESCRIPTION
(Continued)
configurable under software control to provide timing, sta-
tus signals, parallel I/O with or without handshake, and ad-
dress/data bus for interfacing external memory.
To unburden the system from coping with real-time tasks
such as counting/timing and data communication, the Z8
offer two on-chip counter/timers with a large number of
user-selectable modes.
With ROM/ROMless selectivity, the Z86C44/C45/C46
provide both external memory and preprogrammed ROM,
which enables this Z8
MCU to be used in high-volume ap-
plications, or where code flexibility is required.
Note:
All signals with an overline are active Low. For exam-
ple, B/
W
, for which WORD is active Low, and
B
/W, for
which BYTE is active Low.
Power connections follow these conventional descriptions:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Figure 1. Functional Block Diagram
Port 3
Counter/
Timers (2)
Interrupt
Control
Two Analog
Comparators
Port 2
I/O
(Bit Programmable)
ALU
FLAG
Register
Pointer
Register File
Machine
Timing & Inst.
Control
RESET
WDT, POR
Program
Memory
Program
Counter
V
GND
XTAL
4
4
Port 0
AS DS R/W RESET
Output
Input
Port 1
8
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
(C44/C45/C46 Only)
(C44/C45/C46 Only)
CC
Full-Duplex
UART
16-Bit Baud
Rate Generator
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
3
PIN DESCRIPTION
Figure 2. 28-Pin DIP/SOIC Pin Configuration
P25
P26
P27
P04
P05
P06
P07
V
CC
XTAL2
XTAL1
P31
P32
P33
P34
P24
P23
P22
P21
P20
P03
GND
P02
P01
P00
P30
P36
P37
P35
28
Z86C34/C35/C36
1
14
15
Figure 3. 28-Pin PLCC Pin Configuration
25
19
5
11
18
12
26
4
Z86C34/C35/C36
1
P21
P20
P03
GND
P02
P01
P00
P05
P06
P07
V
CC
XTAL2
XTAL1
P31
P04
P27
P26
P25
P24
P23
P22
P32
P33
P34
P35
P37
P36
P30
Table 1. 28-Pin DIP/SOIC/PLCC Pin Identification
Pin #
Symbol
Function
Direction
13
P2527
Port 2, Bits 5,6,7
In/Output
47
P0407
Port 0, Bits 4,5,6,7
In/Output
8
V
CC
Power Supply
9
XTAL2
Crystal Oscillator
Output
10
XTAL1
Crystal Oscillator
Input
1113
P3133
Port 3, Bits 1,2,3
Fixed Input
1415
P3435
Port 3, Bits 4,5
Fixed Output
16
P37
Port 3, Bit 7
Fixed Output
17
P36
Port 3, Bit 6
Fixed Output
18
P30
Port 3, Bit 0
Fixed Input
1921
P0002
Port 0, Bits 0,1,2
In/Output
22
GND
Ground
23
P03
Port 0, Bit 3
In/Output
2428
P2024
Port 2, Bits 0,1,2,3,4
In/Output
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
4
P R E L I M I N A R Y
DS007601-Z8X0499
PIN DESCRIPTION
(Continued)
Figure 4. 40-Pin DIP Configuration
R/W
P25
P26
P27
P04
P05
P06
P14
P15
P07
V
CC
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
AS
DS
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P10
P01
P00
P30
P36
P37
P35
RESET
40
Z86C44/C45/C46
1
20
21
Table 2. 40-Pin Dual-In-Line Package Pin Identification
Pin #
Symbol
Function
Direction
1
R/W
READ/WRITE
Output
24
P2527
Port 2, Bits 5,6,7
In/Output
57
P0406
Port 0, Bits 4,5,6
In/Output
89
P1415
Port 1, Bits 4,5
In/Output
10
P07
Port 0, Bit 7
In/Output
11
V
CC
Power Supply
1213
P1617
Port 1, Bits 6,7
In/Output
14
XTAL2
Crystal Oscillator
Output
15
XTAL1
Crystal Oscillator
Input
1618
P3133
Port 3, Bits 1,2,3
Input
19
P34
Port 3, Bit 4
Output
20
AS
Address Strobe
Output
21
RESET
Reset
Input
22
P35
Port 3, Bit 5
Output
23
P37
Port 3, Bit 7
Output
24
P36
Port 3, Bit 6
Output
25
P30
Port 3, Bit 0
Input
2627
P0001
Port 0, Bit 0,1
In/Output
2829
P1011
Port 1, Bit 0,1
In/Output
30
P02
Port 0, Bit 2
In/Output
31
GND
Ground
3233
P1213
Port 1, Bit 2,3
In/Output
34
P03
Port 0, Bit 3
In/Output
3539
P2024
Port 2, Bit 0,1,2,3,4
In/Output
40
DS
Data Strobe
Output
Table 2. 40-Pin Dual-In-Line Package Pin Identification
Pin #
Symbol
Function
Direction
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
5
Figure 5. 44-Pin PLCC Pin Configuration
Z86C44/C45/C46
7
17
P21
P22
P23
P24
DS
NC
R/W
P25
P26
P27
P04
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
V
CC
V
CC
P16
P17
XTAL2
XTAL1
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P00
1
28
18
40
39
29
6
Table 3. 44-Pin PLCC Pin Identification
Pin #
Symbol
Function
Direction
12
GND
Ground
34
P1213
Port 1, Bits 2,3
In/Output
5
P03
Port 0, Bit 3
In/Output
610
P2024
Port 2, Bits 0,1,2,3,4
In/Output
11
DS
Data Strobe
Output
12
NC
Not Connected
13
R/W
READ/WRITE
Output
1416
P2527
Port 2, Bits 5,6,7
In/Output
1719
P0406
Port 0, Bits 4,5,6
In/Output
2021
P1415
Port 1, Bits 4,5
In/Output
22
P07
Port 0, Bit 7
In/Output
2324
V
CC
Power Supply
2526
P1617
Port 1, Bits 6,7
In/Output
27
XTAL2
Crystal Oscillator
Output
28
XTAL1
Crystal Oscillator
Input
2931
P3133
Port 3, Bits 1,2,3
Input
32
P34
Port 3, Bit 4
Output
33
AS
Address Strobe
Output
34
R/RL
ROM/ROMless Control Input
35
RESET
Reset
Input
36
P35
Port 3, Bit 5
Output
37
P37
Port 3, Bit 7
Output
38
P36
Port 3, Bit 6
Output
39
P30
Port 3, Bit 0
Input
4041
P0001
Port 0, Bits 0,1
In/Output
4243
P1011
Port 1, Bits 0,1
In/Output
44
P02
Port 0, Bit 2
In/Output
Table 3. 44-Pin PLCC Pin Identification
Pin #
Symbol
Function
Direction
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
6
P R E L I M I N A R Y
DS007601-Z8X0499
PIN DESCRIPTION
(Continued)
Figure 6. 44-Pin QFP Pin Configuration
34
44
P21
P22
P23
P24
DS
NC
R/W
P25
P26
P27
P04
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
V
CC
V
CC
P16
P17
XTAL2
XTAL1
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P00
1
23
33
Z86C44/C45/C46
11
22
12
Table 4. 44-Pin QFP Pin Identification
Pin #
Symbol
Function
Direction
12
P0506
Port 0, Bits 5,6
In/Output
34
P1415
Port 1, Bits 4,5
In/Output
5
P07
Port 0, Bit 7
In/Output
67
V
CC
Power Supply
89
P1617
Port 1 Bits 6,7
In/Output
10
XTAL2
Crystal Oscillator
Output
11
XTAL1
Crystal Oscillator
Input
1214 P3133
Port 3, Bits 1,2,3
Input
15
P34
Port 3, Bit 4
Output
16
AS
Address Strobe
Output
17
R/RL
ROM/ROMless Control
Input
18
RESET
Reset
Input
19
P35
Port 3, Bit 5
Output
20
P37
Port 3, Bit 7
Output
21
P36
Port 3, Bit 6
Output
22
P30
Port 3, Bit 0
Input
2324 P0001
Port 0, Bits 0,1
In/Output
2526 P1011
Port 1, Bits 0,1
In/Output
27
P02
Port 0, Bit 2
In/Output
2829 GND
Ground
3031 P1213
Port 1, Bits 2,3
In/Output
32
P03
Port 0, Bit 3
In/Output
3337 P2024
Port 2, Bits 0,1,2,3,4
In/Output
38
DS
Data Strobe
Output
39
NC
Not Connected
40
R/W
READ/WRITE
Output
Table 4. 44-Pin QFP Pin Identification
Pin #
Symbol
Function
Direction
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
7
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
rating is a stress rating only. Functional operation of the de-
vice at any condition above those indicated in the opera-
tional sections of these specifications is not implied. Expo-
sure to absolute maximum rating conditions for an extended
period may affect device reliability.
Total power dissipation should not exceed 1.21 W for the
package. Power dissipation is calculated as follows:
Parameter
Min
Max
Units
Notes
Ambient Temperature under Bias
40
+105
C
Storage Temperature
65
+150
C
Voltage on any Pin with Respect to V
SS
0.6
+7
V
1
Voltage on V
DD
Pin with Respect to V
SS
0.3
+7
V
Voltage on XTAL1 and RESET Pins with Respect to V
SS
0.6
V
DD
+1
V
2
Total Power Dissipation
1.21
W
Maximum Allowable Current out of V
SS
220
mA
Maximum Allowable Current into V
DD
180
mA
Maximum Allowable Current into an Input Pin
600
+600
A
3
Maximum Allowable Current into an Open-Drain Pin
600
+600
A
4
Maximum Allowable Output Current Sunk by Any I/O Pin
25
mA
Maximum Allowable Output Current Sourced by Any I/O Pin
25
mA
Notes:
1. Applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to V
DD
and current into pin is limited to 600 A.
3. Excludes XTAL pins.
4. Device pin is not at an output Low state.
Total Power Dissipation = V
DD
x [I
DD
(sum of I
OH
),
+ sum of [(V
DD
V
OH
) x I
OH
]
+ sum of (V
OL
x I
OL
)
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
8
P R E L I M I N A R Y
DS007601-Z8X0499
STANDARD TEST CONDITIONS
The characteristics listed in following pages apply for stan-
dard test conditions as noted. All voltages are referenced
to
GND
. Positive current flows into the referenced pin (see
Figure 7.)
CAPACITANCE
T
A
= 25C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins to GND
Figure 7. Test Load Diagram
From Output
Under Test
150 pF
Parameter
Min
Max
Input capacitance
0
12 pF
Output capacitance
0
12 pF
I/O capacitance
0
12 pF
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
9
DC ELECTRICAL CHARACTERISTICS
Table 5. DC Characteristics
T
A
=
0C to +70C
T
A
=
40C to +105C
Sym
Parameter
V
CC
1
Min
Max
Min
Max
Typical
2
@25C
Units Conditions
Notes
V
CH
Clock Input
High
Voltage
3.0V
0.7 V
CC
V
CC
+0.3
0.7 V
CC
V
CC
+0.3
1.8
V
Driven by
External Clock
Generator
5.5V
0.7 V
CC
V
CC
+0.3
0.7 V
CC
V
CC
+0.3
2.6
V
Driven by
External Clock
Generator
V
CL
Clock Input
Low
Voltage
3.0V
GND0.3
0.2 V
CC
GND0.3
0.2 V
CC
1.2
V
Driven by
External Clock
Generator
5.5V
GND0.3
0.2 V
CC
GND0.3
0.2 V
CC
2.1
V
Driven by
External Clock
Generator
V
IH
Input High
Voltage
3.0V
0.7 V
CC
V
CC
+0.3
0.7 V
CC
V
CC
+0.3
1.8
V
5.5V
0.7 V
CC
V
CC
+0.3
0.7 V
CC
V
CC
+0.3
2.6
V
V
IL
Input Low
Voltage
3.0V
GND0.3
0.2 V
CC
GND0.3
0.2 V
CC
1.1
V
5.5V
GND0.3
0.2 V
CC
GND0.3
0.2 V
CC
1.6
V
V
OH
Output
High
Voltage
(Low-EMI
Mode)
3.0V
V
CC
0.4
V
CC
0.4
3.1
V
I
OH
= 0.5 mA
5.0V
V
CC
0.4
V
CC
0.4
4.8
V
I
OH
= 0.5 mA
V
OH1
Output
High
Voltage
3.0V
V
CC
0.4
V
CC
0.4
3.1
V
I
OH
= 2.0 mA
3
5.5V
V
CC
0.4
V
CC
0.4
4.8
V
I
OH
= 2.0 mA
3
V
OL
Output Low
Voltage
(Low-EMI
Mode)
3.0V
0.6
0.6
0.2
V
I
OL
= 1.0 mA
5.0V
0.4
0.4
0.1
V
I
OL
= 1.0 mA
V
OL1
Output Low
Voltage
3.0V
0.6
0.6
0.2
V
I
OL
= +4.0 mA
3
5.5V
0.4
0.4
0.1
V
I
OL
= +4.0 mA
3
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V
CC
= 3.3V, and the V
CC
voltage
specification of 5.5V guarantees 5.0V 0.5V with typicals at V
CC
= 5.0V.
2. Typicals are at V
CC
= 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
CC
.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0C to 70C (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V
LV
voltage increases as the temperature decreases and overlaps lower V
CC
operating region.
12. 40C to 150C (extended temperature).
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
10
P R E L I M I N A R Y
DS007601-Z8X0499
DC ELECTRICAL CHARACTERISTICS (Continued)
V
OL2
Output Low
Voltage
3.0V
1.2
1.2
0.3
V
I
OL
= +6 mA
3
5.5V
1.2
1.2
0.4
V
I
OL
= +12 mA
3
V
RH
Reset Input
High
Voltage
3.0V
.8 V
CC
V
CC
.8 V
CC
V
CC
1.8
V
4
5.5V
.8 V
CC
V
CC
.8 V
CC
V
CC
2.6
V
4
V
Rl
Reset Input
Low
Voltage
3.0V
GND0.3
0.2 V
CC
GND0.3
0.2 V
CC
1.1
V
4
5.5V
GND0.3
0.2 V
CC
GND0.3
0.2 V
CC
1.6
V
4
V
OLR
Reset
Output Low
Voltage
3.0V
0.6
0.6
0.3
V
I
OL
= +1.0 mA
4
5.5V
0.6
0.6
0.3
V
I
OL
= +1.0 mA
4
V
OFFSET
Comparator
Input Offset
Voltage
3.0V
25
25
10
mV
5
5.5V
25
25
10
mV
5
I
IL
Input
Leakage
3.0V
1
2
1
2
0.004
A
V
IN
= 0V, V
CC
5.5V
1
2
1
2
0.004
A
V
IN
= 0V, V
CC
I
OL
Output
Leakage
3.0V
1
1
1
2
0.004
A
V
IN
= 0V, V
CC
5.5V
1
1
1
2
0.004
A
V
IN
= 0V, V
CC
IIR
Reset Input
Current
3.0V
20
130
18
130
60
A
5.5V
20
180
18
180
85
A
I
CC
Supply
Current
3.0V
20
20
7
mA @ 16 MHz
6
5.5V
25
25
20
mA @ 16 MHz
6
3.0V
15
15
5
mA @ 12 MHz
6
5.5V
20
20
15
mA @ 12 MHz
6
Table 5. DC Characteristics (Continued)
T
A
=
0C to +70C
T
A
=
40C to +105C
Sym
Parameter
V
CC
1
Min
Max
Min
Max
Typical
2
@25C
Units Conditions
Notes
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V
CC
= 3.3V, and the V
CC
voltage
specification of 5.5V guarantees 5.0V 0.5V with typicals at V
CC
= 5.0V.
2. Typicals are at V
CC
= 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
CC
.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0C to 70C (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V
LV
voltage increases as the temperature decreases and overlaps lower V
CC
operating region.
12. 40C to 150C (extended temperature).
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
11
I
CC1
Standby
Current
(HALT
Mode)
3.0V
4.5
4.5
2.0
mA V
IN
= 0V, V
CC
@ 16 MHz
6
5.5V
8
8
3.7
mA V
IN
= 0V, V
CC
@ 16 MHz
6
3.0V
3.4
3.4
1.5
mA Clock Divide-
by-16 @ 16
MHz
6
5.5V
7.0
7.0
2.9
mA Clock Divide-
by-16 @ 16
MHz
6
I
CC2
Standby
Current
(STOP
Mode)
3.0V
8
8
2
A
V
IN
= 0V, V
CC
WDT is not
Running
7,8
5.5V
10
10
4
A
V
IN
= 0V, V
CC
WDT is not
Running
7,8
3.0V
500
600
310
A
V
IN
= 0V, V
CC
WDT is
Running
7,8,9
5.5V
800
1000
600
A
V
IN
= 0V, V
CC
WDT is
Running
7,8,9
V
ICR
Input
Common
Mode
Voltage
Range
3.0V
0
V
CC
1.0V
0
V
CC
1.5V
V
5
5.5V
0
V
CC
1.0V
0
V
CC
1.5V
V
5
I
ALL
Auto Latch
Low
Current
3.0V
0.7
8
0.7
10
3
A
0V < V
IN
< V
CC
10
5.5V
1.4
15
1.4
20
5
A
0V < V
IN
< V
CC
10
I
ALH
Auto Latch
High
Current
3.0V
0.6
5
0.6
7
3
A
0V < V
IN
< V
CC
10
5.5V
1.0
8
1.0
10
6
A
0V < V
IN
< V
CC
10
Table 5. DC Characteristics (Continued)
T
A
=
0C to +70C
T
A
=
40C to +105C
Sym
Parameter
V
CC
1
Min
Max
Min
Max
Typical
2
@25C
Units Conditions
Notes
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V
CC
= 3.3V, and the V
CC
voltage
specification of 5.5V guarantees 5.0V 0.5V with typicals at V
CC
= 5.0V.
2. Typicals are at V
CC
= 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
CC
.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0C to 70C (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V
LV
voltage increases as the temperature decreases and overlaps lower V
CC
operating region.
12. 40C to 150C (extended temperature).
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
12
P R E L I M I N A R Y
DS007601-Z8X0499
DC ELECTRICAL CHARACTERISTICS (Continued)
V
LV
V
CC
Low
Voltage
Protection
Voltage
2.0
3.3
2.8
V
4 MHz max
Int. CLK Freq.
11,12
2.2
3.1
2.8
6 MHz max
Int. CLK Freq.
9,11
Table 5. DC Characteristics (Continued)
T
A
=
0C to +70C
T
A
=
40C to +105C
Sym
Parameter
V
CC
1
Min
Max
Min
Max
Typical
2
@25C
Units Conditions
Notes
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V with typicals at V
CC
= 3.3V, and the V
CC
voltage
specification of 5.5V guarantees 5.0V 0.5V with typicals at V
CC
= 5.0V.
2. Typicals are at V
CC
= 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at V
CC
.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0C to 70C (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The V
LV
voltage increases as the temperature decreases and overlaps lower V
CC
operating region.
12. 40C to 150C (extended temperature).
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
13
AC ELECTRICAL CHARACTERISTICS
External I/O or Memory READ and WRITE Timing
Figure 8. External I/O or Memory READ and WRITE Timing
R/W
9
12
18
3
16
13
4
5
8
11
6
17
10
15
7
14
2
1
Port 0, DM
Port 1
AS
DS
(Read)
Port1
DS
(Write)
D7D0 IN
D7D0 OUT
A7A0
A7A0
19
20
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
14
P R E L I M I N A R Y
DS007601-Z8X0499
AC ELECTRICAL CHARACTERISTICS (Continued)
Table 6. External I/O or Memory READ and WRITE Timing (C44/C45/C46 Only)
(SCLK/TCLK = XTAL/2)
T
A
= 0C to 70C
T
A
= 40C to +105C
12 MHz
16 MHz
12 MHz
16 MHz
No
Symbol
Parameter
V
CC
1
Min
Max
Min
Max
Min
Max
Min
Max Units Notes
1
TdA(AS)
Address Valid to AS
Rise Delay
3.0
35
25
35
25
ns
2
5.5
35
25
35
25
ns
2
2
TdAS(A)
AS Rise to Address
Float Delay
3.0
45
35
45
35
ns
2
5.5
45 35
45
35
ns
2
3
TdAS(DR)
AS Rise to Read
Data Req'd Valid
3.0
250 180
250
180
ns
2,3
5.5
250 180
250
180
ns
2
4
TwAS
AS Low Width
3.0
55
40
55
40
ns
2
5.5
55 40
55
40
ns
2
5
TdAS(DS)
Address Float to DS
Fall
3.0
0
0
0
0
ns
5.5
0
0
0
0
ns
6
TwDSR
DS (Read) Low
Width
3.0
200
135
200
135
ns
2,3
5.5
200
135
200
135
ns
2,3
7
TwDSW
DS (WRITE) Low
Width
3.0
110 80
110
80
ns
2,3
5.5
110 80
110
80
ns
2,3
8
TdDSR(DR)
DS Fall to Read Data
Req'd Valid
3.0
150 75
150
75
ns
2,3
5.5
150 75
150
75
ns
2,3
9
ThDR(DS)
Read Data to DS
Rise Hold Time
3.0
0
0
0
0
ns
2
5.5
0
0
0
0
ns
2
10
TdDS(A)
DS Rise to Address
Active Delay
3.0
45
50
45
50
ns
2
5.5
55
50
55
50
ns
2
11
TdDS(AS)
DS Rise to AS Fall
Delay
3.0
30
35
30
35
ns
2
5.5
45
35
45
55
ns
2
12
TdR/W(AS)
R/W Valid to AS Rise
Delay
3.0
45
25
45
25
ns
2
5.5
45
25
45
25
ns
2
13
TdDS(R/W)
DS Rise to R/W Not
Valid
3.0
45
35
45
35
ns
2
5.5
45
35
45
35
ns
2
14
TdDW(DSW) WRITE Data Valid to
DS Fall (WRITE)
Delay
3.0
55
25
55
25
ns
2
5.5
55
25
55
25
ns
2
15
TdDS(DW)
DS Rise to WRITE
Data Not Valid Delay
3.0
45
35
45
35
ns
2
5.5
45
35
45
35
ns
2
16
TdA(DR)
Address Valid to
Read Data Req'd
Valid
3.0
310 230
310
230
ns
2,3
5.5
310 230
310
230
ns
2,3
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V
0.5V.
2. Timing numbers provided are for minimum TpC.
3. When using extended memory timing add 2 TpC.
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
15
17
TdAS(DS)
AS Rise to DS Fall
Delay
3.0
65
45
65
45
ns
2
5.5
65
45
65
45
ns
2
18
TdDM(AS)
DM Valid to AS Fall
Delay
3.0
35
30
35
30
ns
2
5.5
35
30
35
30
ns
2
19
TdDs(DM)
DS Rise to DM Valid
Delay
3.0
5.5
45
45
35
35
45
45
35
35
ns
ns
2
2
20
ThDS(AS)
DS Valid to Address
Valid Hold Time
3.0
5.5
45
45
35
35
45
45
35
35
ns
ns
2
2
Table 6. External I/O or Memory READ and WRITE Timing (C44/C45/C46 Only)
(SCLK/TCLK = XTAL/2) (Continued)
T
A
= 0C to 70C
T
A
= 40C to +105C
12 MHz
16 MHz
12 MHz
16 MHz
No
Symbol
Parameter
V
CC
1
Min
Max
Min
Max
Min
Max
Min
Max Units Notes
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V
0.5V.
2. Timing numbers provided are for minimum TpC.
3. When using extended memory timing add 2 TpC.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
16
P R E L I M I N A R Y
DS007601-Z8X0499
AC ELECTRICAL CHARACTERISTICS (Continued)
Additional Timing Diagram
Figure 9. Additional Timing
Clock
1
3
4
8
2
2
3
TIN
IRQN
6
5
7
7
11
Clock
Setup
10
9
Stop
Mode
Recovery
Source
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
17
Table 7. Additional Timing (SCLK/TCLK = XTAL/2)
T
A
= 0C to +70C
T
A
= 40C to +105C
12 MHz
16 MHz
12 MHz
16 MHz
No Symbol
Parameter
V
CC
1
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes D1,D0
1
TpC
Input Clock
Period
3.0V
83
DC
62.5
DC
83
DC
62.5
DC
ns
2,3,4
5.5V
83
DC
62.5
DC
83
DC
62.5
DC
ns
2,3,4
3.0V
250
DC
250
DC
250
DC
250
DC
ns
2,3
5.5V
250
DC
250
DC
250
DC
250
DC
ns
2,3
2
TrC,TfC
Clock Input
Rise & Fall
Times
3.0V
15
15
15
15
ns
2,3
5.5V
15
15
15
15
ns
2,3
3
TwC
Input Clock
Width
3.0V
41
31
41
31
ns
2,3,4
5.5V
41
31
41
31
ns
2,3,4
3.0V
125
125
125
125
ns
2,3
5.5V
125
125
125
125
ns
2,3
4
TwTinL
Timer Input
Low Width
3.0V
100
100
100
100
ns
2,3
5.5V
70
70
70
70
ns
2,3
5
TwTinH
Timer Input
High Width
3.0V
5TpC
5TpC
5TpC
5TpC
2,3
5.5V
5TpC
5TpC
5TpC
5TpC
2,3
6
TpTin
Timer Input
Period
3.0V
8TpC
8TpC
8TpC
8TpC
2,3
5.5V
8TpC
8TpC
8TpC
8TpC
2,3
7
TrTin,
TfTin
Timer Input
Rise & Fall
Timer
3.0V
100
100
100
100
ns
2,3
5.5V
100
100
100
100
ns
2,3
8A TwIL
Int. Request
Low Time
3.0V
100
100
100
100
ns
2,3,5
5.5V
70
70
70
70
ns
2,3,5
8B TwIL
Int. Request
Low Time
3.0V
5TpC
5TpC
5TpC
5TpC
2,3,6
5.5V
5TpC
5TpC
5TpC
5TpC
2,3,6
9
TwIH
Int. Request
Input High
Time
3.0V
5TpC
5TpC
5TpC
5TpC
2,3,5
5.5V
5TpC
5TpC
5TpC
5TpC
2,3,5
10 Twsm
Stop-Mode
Recovery
Width Spec
3.0V
12
12
12
12
ns
7
5.5V
12
12
12
12
ns
7
11 Tost
Oscillator
Startup Time
3.0V
5TpC
5TpC
5TpC
5TpC
7,8
5.5V
5TpC
5TpC
5TpC
5TpC
7,8
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V
0.5V.
2. Timing Reference uses 0.7 V
CC
for a logic
1
and 0.2 V
CC
for a logic
0
.
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31P33).
6. Interrupt request via Port 3 (P30).
7. SMRD5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
9. Register WDTMR.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
18
P R E L I M I N A R Y
DS007601-Z8X0499
AC ELECTRICAL CHARACTERISTICS (Continued)
12 Twdt
Watch-Dog
Timer Delay
Timer before
time-out
3.0V
7
7
7
7
ms
9
0,0
5.5V
3.5
3.5
3.5
3.5
ms
9
0,0
3.0V
14
14
14
14
ms
9
0,1
5.5V
7
7
7
7
ms
9
0,1
3.0V
28
28
28
28
ms
9
1,0
5.5V
14
14
14
14
ms
9
1,0
3.0V
112
112
112
112
ms
9
1,1
5.5V
56
56
56
56
ms
9
1,1
13 TPOR
Power-On
Reset Delay
3.0V
3
24
3
24
3
25
3
25
ms
5.5V
1.5
13
1.5
13
1
14
1
14
ms
Table 7. Additional Timing (SCLK/TCLK = XTAL/2) (Continued)
T
A
= 0C to +70C
T
A
= 40C to +105C
12 MHz
16 MHz
12 MHz
16 MHz
No Symbol
Parameter
V
CC
1
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes D1,D0
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V
0.5V.
2. Timing Reference uses 0.7 V
CC
for a logic
1
and 0.2 V
CC
for a logic
0
.
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31P33).
6. Interrupt request via Port 3 (P30).
7. SMRD5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
9. Register WDTMR.
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
19
Table 8. Additional Timing
(Divide-By-One Mode, SCLK/TCLK = XTAL)
T
A
= 0C to
+70C
T
A
= 40C to
+105C
V
CC
1
8 MHz
8 MHz
No
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
1
TpC
Input Clock Period
3.0V
250
DC
250
DC
ns
2,3,4
5.5V
250
DC
250
DC
ns
2,3,4
3.0V
125
DC
125
DC
ns
2,3
5.5V
125
DC
125
DC
ns
2,3
2
TrC,TfC
Clock Input Rise
& Fall Times
3.0V
25
25
ns
2,3
5.5V
25
25
ns
2,3
3
TwC
Input Clock Width
3.0V
125
125
ns
2,3,4
5.5V
125
125
ns
2,3,4
3.0V
62
62
ns
2,3
5.5V
62
62
ns
2,3
4
TwTinL
Timer Input Low Width
3.0V
100
100
ns
2,3
5.5V
70
70
ns
2,3
5
TwTinH
Timer Input High Width
3.0V
3TpC
3TpC
2,3
5.5V
3TpC
3TpC
2,3
6
TpTin
Timer Input Period
3.0V
4TpC
4TpC
2,3
5.5V
4TpC
4TpC
2,3
7
TrTin,
TfTin
Timer Input Rise
& Fall Timer
3.0V
100
100
ns
2,3
5.5V
100
100
ns
2,3
8A
TwIL
Int. Request Low Time
3.0V
100
100
ns
2,3,5
5.5V
70
70
ns
2,3,5
8B
TwIL
Int. Request Low Time
3.0V
3TpC
3TpC
2,3,6
5.5V
3TpC
3TpC
2,3,6
9
TwIH
Int. Request Input
High Time
3.0V
3TpC
3TpC
2,3,5
5.5V
3TpC
2TpC
2,3,5
10
Twsm
Stop-Mode Recovery
Width Spec
3.0V
12
12
ns
7
5.5V
12
12
ns
7
11
Tost
Oscillator Startup Time
3.0V
5TpC
5TpC
7,8
5.5V
5TpC
5TpC
7,8
Notes:
1. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V
0.5V.
2. Timing Reference uses 0.7 V
CC
for a logic "1" and 0.2 V
CC
for a logic "0".
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31P33).
6. Interrupt request via Port 3 (P30).
7. SMRD5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
20
P R E L I M I N A R Y
DS007601-Z8X0499
AC ELECTRICAL CHARACTERISTICS (Continued)
Handshake Timing Diagrams
Figure 10. Input Handshake Timing
Data In
1
2
3
4
DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
5
6
Figure 11. Output Handshake Timing
Data Out
DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8
9
10
11
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
21
Table 9. Handshake Timing
1
T
A
= 0C to +70C
T
A
= 40C to +105C
12 MHz
16 MHz
12 MHz
16 MHz
Data
Direction
No
Symbol
Parameter
V
CC
2
Min Max Min Max Min Max Min Max
1
TsDI(DAV)
Data In Setup Time
3.0V
0
0
0
0
IN
5.5V
0
0
0
0
IN
2
ThDI(RDY)
Data In Hold Time
3.0V
0
0
0
0
IN
5.5V
0 0
0
0
IN
3
TwDAV
Data Available Width
3.0V
155
155
155
155
IN
5.5V
110
110
110
110
IN
4
TdDAVI(RDY)
DAV Fall to RDY Fall
Delay
3.0V
0
0
0
0
IN
5.5V
0
0
0
0
IN
5
TdDAVId(RDY) DAV Out to DAV Fall
Delay
3.0V
120
120
120
120
IN
5.5V
80
80
80
80
IN
6
RDY0d(DAV)
RDY Rise to DAV Fall
Delay
3.0V
0
0
0
0
IN
5.5V
0
0
0
0
IN
7
TdD0(DAV)
Data Out to DAV Fall
Delay
3.0V
42
31
42
31
OUT
5.5V
42
31
42
31
OUT
8
TdDAV0(RDY)
DAV Fall to RDY Fall
Delay
3.0V
0
0
0
0
OUT
5.5V
0
0
0
0
OUT
9
TdRDY0(DAV)
RDY Fall to DAV Rise
Delay
3.0V
160
160
160
160
OUT
5.5V
115
115
115
115
OUT
10
TwRDY
RDY Width
3.0V
110
110
110
110
OUT
5.5V
80
80
80
80
OUT
11
TdRDY0d(DAV) RDY Rise to DAV Fall
Delay
3.0V
110
110
110
110
OUT
5.5V
80
80
80
80
OUT
Note:
1. Timing Reference uses 0.7 V
CC
for a logic
1
and 0.2 V
CC
for a logic
0
.
2. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V. The V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
22
P R E L I M I N A R Y
DS007601-Z8X0499
PIN FUNCTIONS
R/
RL
(input, active Low).
The ROM/ROMless pin, when
connected to
GND
, disables the internal ROM and forces
the device to function as a ROMless Z8. (Not available for
devices in the 28-pin package.)
Notes: When left unconnected or pulled High to
V
CC
, the
device functions normally as a Z8 ROM version.
When using in ROM Mode in a high-EMI (noisy)
environment, the ROMless pins should be connected
directly to
V
CC
.
DS
(output, active Low).
Data Strobe is activated one
time for each external memory transfer. For a
READ
oper-
ation, data must be available prior to the trailing edge of
DS
.
For
WRITE
operations, the falling edge of
DS
indicates that
output data is valid. (Not available for devices in the 28-
pin package.)
AS
(output, active Low).
Address Strobe is pulsed one
time at the beginning of each machine cycle for external
memory transfer. Address output is from Port 0/Port 1 for
all external programs. Memory address transfers are valid
at the trailing edge of
AS
. Under program control,
AS
is
placed in the high-impedance state along with Ports 0 and
1, Data Strobe, and
READ/WRITE
. (Not available for de-
vices in the 28-pin package.)
XTAL1 Crystal 1 (time-based input).
This pin connects a
parallel-resonant crystal, ceramic resonator,
LC
, or
RC
net-
work, or an external single-phase clock to the on-chip os-
cillator input.
XTAL2 Crystal 2 (time-based output).
This pin connects
a parallel-resonant crystal, ceramic resonant,
LC
, or
RC
net-
work to the on-chip oscillator output.
R/
W
(output, WRITE Low).
The
READ/WRITE
signal is
Low when the Z8 is writing to the external program or data
memory. (Not available for devices in the 28-pin package.)
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
23
Port 0 (P00P07).
Port 0 is an 8-bit, bidirectional, CMOS-
compatible port. These eight I/O lines are configured under
software control as a nibble I/O port (
P03P00
input/output
and
P07P04
input/output), or as an address port for inter-
facing external memory. The input buffers are Schmitt-trig-
gered and nibble-programmed as outputs and can be glo-
bally programmed as either push-pull or open-drain. Low-
EMI output buffers can be globally programmed by the soft-
ware. Port 0 is placed under handshake control. In this con-
figuration, Port 3, lines
P32
and
P35
are used as the hand-
shake control
DAV0
and
RDY0
. Handshake signal direction
is dictated by the I/O direction (input or output) of Port 0
of the upper nibble
P04P07
. The lower nibble must indi-
cate the same direction as the upper nibble.
For external memory references, Port 0 provides address
bits
A11A8
(lower nibble) or
A15A8
(lower and upper
nibble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of Port
0 can be programmed independently as I/O while the lower
nibble is used for addressing. If one or both nibbles are re-
quired for I/O operation, they are configured by writing to
the Port 0 mode register.
In ROMless mode, after a hardware
RESET
, Port 0 is con-
figured as address lines
A15A8
, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
input after
RESET
.)
Port 0 can be placed in a high-impedance state along with
Port 1,
AS
,
DS
and
R/W
, allowing the Z8 to share common re-
sources in multiprocessor and DMA applications (Figure 12).
Figure 12. Port 0 Configuration
Port 0
(I/O or A15A8)
Handshake Controls
DAV0 and RDY0
(P32 and P35)
Z8
4
4
Open-Drain
OE
Out
In
1.5 2.3 Hysteresis @ V = 5.0V
PAD
Pull-Up
Transistor Enable
(Mask Option)
Auto Latch
(mask option)
R
500K
CC
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
24
P R E L I M I N A R Y
DS007601-Z8X0499
PIN FUNCTIONS (Continued)
Port 1 (P17P10).
Port 1 is an 8-bit, bidirectional, CMOS-
compatible port (Figure 13), with multiplexed Address
(
A7A0
) and Data (
D7D0
) ports. For the ROM device,
these eight I/O lines are programmed as inputs or outputs,
or can be configured under software control as an Ad-
dress/Data port for interfacing external memory. The input
buffers are Schmitt-triggered and byte-programmed as out-
puts and can be globally programmed as either push-pull
or open-drain. Low-EMI output buffers can be globally pro-
grammed by the software.
Note: Port 1 is not available on the devices in the 28-pin pack-
age, and
P01M
Register must set Bit
D4,D3
as
00
. Low-
EMI mode is not supported on the emulator for Port1.
PCON
register
D4
must be
1
.
Port 1 may be placed under handshake control. In this con-
figuration, Port 3, lines
P33
and
P34
are used as the hand-
shake controls
RDY1
and
DAV1
(Ready and Data Avail-
able). Memory locations greater than the internal ROM
address are referenced through Port 1, except for Z86C46.
To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If more than 256
external locations are required, Port 0 outputs the additional
lines.
Port 1 can be placed in the high-impedance state along with
Port 0,
AS
,
DS
, and
R/W
, allowing the Z8 to share common
resources in multiprocessor and DMA applications.
Figure 13. Port 1 Configuration
Open Drain
OE
Out
In
1.5 2.3 Hysteresis @ V
CC
= 5.0V
PAD
Auto Latch
(mask option)
R
500 K
Port 1
(I/O or AD7AD0)
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Z8
8
Pull-Up
Transistor Enable
(Mask Option)
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
25
Port 2 (P27P20).
Port 2 is an 8-bit, bidirectional, CMOS-
compatible I/O port. These eight I/O lines are configured
under software control as an input or output, independently.
Port 2 is always available for I/O operation. The input buff-
ers are Schmitt-triggered. Bits programmed as outputs may
be globally programmed as either push-pull or open-drain.
Low-EMI output buffers can be globally programmed by
the software.
Port 2 may be placed under handshake control. In this Hand-
shake Mode, Port 3 lines
P31
and
P36
are used as the hand-
shake controls lines
DAV2
and
RDY2
. The handshake signal
assignment for Port 3 lines
P31
and
P36
is dictated by the di-
rection (input or output) assigned to Bit 7, Port 2 (Figure 14).
Figure 14. Port 2 Configuration
Open Drain
OE
Out
In
1.5 2.3 Hysteresis @ V
CC
= 5.0V.
PAD
Auto Latch
(mask option)
Port 2 (I/O)
Handshake Controls
Z8
R
500 K
DAV2 and RDY2
(P31 and P36)
Pull-Up
Transistor Enable
(Mask Option)
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
26
P R E L I M I N A R Y
DS007601-Z8X0499
PIN FUNCTIONS (Continued)
Port 3 (P37P30).
Port 3 is an 8-bit, CMOS-compatible
port, with four fixed inputs (
P33P30
) and four fixed out-
puts (
P34P37
). It is configured under software control for
Input/Output, Counter/Timers, interrupt, port handshake,
and Data Memory functions. Port 3, bit
0
input is Schmitt-
triggered, and pins
P31
,
P32
, and
P33
are standard CMOS
inputs (no Auto Latches). Pins
P34
,
P35
,
P36
,
P37
are push-
pull output lines. Low-EMI output buffers can be globally
programmed by the software.
Two onboard comparators can process analog signals on
P31
and
P32
with reference to the voltage on
P33
. The an-
alog function is enabled by programming Port 3 Mode Reg-
ister (
P3M
bit
1
). For Interrupt functions, Port 3, bit
0
and
pin
3
are falling edge interrupt inputs.
P31
and
P32
are pro-
grammable as rising, falling, or both edge triggered inter-
rupts (
IRQ
register Bits
6
and
7
).
P33
is the comparator ref-
erence voltage input when in Analog mode. Access to
Counter/Timers 1 is made through
P31
(
T
IN
) and
P36
(
T
OUT
). Handshake lines for Ports 0, 1, and 2 are available
on
P31
through
P36
.
Port 3 also provides the following control functions: hand-
shake for Ports 0, 1, and 2 (
DAV
and
RDY
); four external
interrupt request signals (
IRQ3IRQ0
); timer input and out-
put signals (
T
IN
and
T
OUT
); Data Memory Select (
DM
, see
Table 10 and Figure 15).
P34
output can be software-programmed to function as a
Data Memory Select (
DM
). The Port 3 mode register (
P3M
)
Bit
D3
,
D4
selects this function. When accessing external
Data Memory, the
P34
goes active Low; when accessing
external Program Memory, the
P34
goes High.
An onboard UART (ASCI) can be enabled by software by
setting the
RE
and
TE
bits of the ASCI Control Register A
(
CNTLA
). When enabled,
P30
is the receive input and
P37
is the transmit output.
Comparator Inputs and Outputs.
Port 3, pins
P31
and
P32
each feature a comparator front end. The comparator
reference voltage, pin
P33
, is common to both comparators.
In analog mode, the
P31
and
P32
are the positive inputs to
the comparators and
P33
is the reference voltage supplied
to both comparators. In digital mode, pin
P33
can be used
as a
P33
register input or
IRQ1
source.
P34
and
P37
outputs
the comparator outputs by software-programming the
PCON
Register Bit
D0
to
1
(see Figure 16).
Note: The user must add a two-
NOP
delay after selecting the
P3M
bit
D1
to
1
before the comparator output is valid.
IRQ0
,
IRQ1
, and
IRQ2
should be cleared in the IRQ reg-
ister when the comparator is enabled or disabled.
Table 10. Port 3 Pin Assignments
Pin
I/O
CTC1
Analog
Int.
P0 HS
P1 HS
P2 HS
Ext
UART
P30
IN
IRQ3
RX
P31
IN
T
IN
AN1
IRQ2
D/R
P32
IN
AN2
IRQ0
D/R
P33
IN
REF
IRQ1
D/R
P34
OUT
AN1OUT
R/D
DM
P35
OUT
R/D
P36
OUT
T
OUT
R/D
P37
OUT
AN2OUT
TX
Notes:
HS = Handshake Signals
D = DAV
R = RDY
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
27
Figure 15. Port 3 Configuration
D1
R247 = P3M
P31 (AN1)
P32 (AN2)
P33 (REF)
From Stop-Mode
Recovery Source
1 = Analog
0 = Digital
IRQ2,
T
IN
, P31 Data Latch
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
DIG.
AN.
Auto Latch
(mask option)
P30 Data
Latch IRQ3
Port 3
(I/O or Control)
Z8
+
+
P30
R
500K
P30
P31
P32
P33
P34
P35
P37
P36
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
28
P R E L I M I N A R Y
DS007601-Z8X0499
PIN FUNCTIONS (Continued)
Auto Latch.
The Auto Latch places valid CMOS levels on
all CMOS inputs (except
P33P31
) that are not externally
driven. Whether this level is
0
or
1
cannot be determined.
A valid CMOS level, rather than a floating node, reduces
excessive supply current flow in the input buffer. Auto
Latches are available on Port 0, Port 1, Port 2, and
P30
.
There are no Auto Latches on
P31
,
P32
, and
P33
.
Note: Deletion of all Port Auto Latches is available as a ROM
Mask option. The Auto Latch Delete option is selected
by the customer when the ROM code is submitted.
RESET
(input, active Low).
Initializes the MCU. Reset is
accomplished either through Power-On Reset, Watch-Dog
Timer reset, Stop-Mode Recovery, or external reset. During
Power-On Reset and Watch-Dog Reset, the internally-gen-
erated reset is driving the
RESET
pin Low for the
POR
time.
Any devices driving the
RESET
line must be open-drain to
avoid damage from a possible conflict during
RESET
con-
ditions.
RESET
depends on oscillator operation to achieve
full reset conditions, except for conditions wherein a
WDT
reset is permanently enabled. Pull-up is provided internally.
Note: The
RESET
pin is not available on devices in the 28-pin
package.
After the
POR
time,
RESET
is a Schmitt-triggered input.
During the
RESET
cycle,
DS
is held active Low while
AS
cycles at a rate of
T
P
C/2
. Program execution begins at lo-
cation
000Ch
, after the
RESET
is released. For Power-On
Reset, the reset output time is
T
POR
ms.
When program execution begins,
AS
and
DS
toggles only
for external memory accesses. The Z8 does not reset
WDTMR
,
SMR
,
P2M
,
PCON
, and
P3M
registers on a Stop-
Mode Recovery operation or from a
WDT
reset out of
STOP
mode.
Figure 16. Port 3 Configuration
P34 OUT
P31
+
REF (P33)
P34
PAD
P37 OUT
P32
+
REF (P33)
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
PCON
D0
P37
PAD
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
29
FUNCTIONAL DESCRIPTION
The Z8 MCU incorporates the following special functions
to enhance the standard Z8
architecture to provide the user
with increased design flexibility.
RESET.
The device is reset in one of the following condi-
tions:
Power-On Reset
Watch-Dog Timer
Stop-Mode Recovery Source
External Reset
Low Voltage Recovery
Auto Power-On Reset circuitry is built into the Z8, elimi-
nating the requirement for an external reset circuit to reset
upon power-up. The internal pull-up resistor is on the Reset
pin, so a pull-up resistor is not required; however, in a high-
EMI (noisy) environment, it is recommended that a small
value pull-up resistor be used.
Note: The
RESET
pin is not available on devices in the 28-pin
package.
Program Memory.
The first 12 bytes of program memory
are reserved for the interrupt vectors. These locations con-
tain six 16-bit vectors that correspond to the six available
interrupts. For ROM mode, address 12 to address
65535
(C36/C46)/
32767
(C35/C45)/
16383
(C34/C44) consists
of on-chip mask-programmed ROM. The Z86C44/C45 can
access external program and data memory from addresses
16384/32768 to 65535.
The
6 5 5 3 5
(C36/C46)/
3 2 7 6 7
(C35/C45)/
1 6 3 8 3
(C34/C44) program memory is mask programmable. A
ROM protect feature prevents dumping of the ROM con-
tents by inhibiting execution of
LDC
,
LDCI
,
LDE
, and
LDEI
instructions to Program Memory in external program
mode
. ROM look-up tables can be used with this feature.
The ROM Protect option is mask-programmable, to be se-
lected by the customer when the ROM code is submitted.
Data Memory (
DM
).
The ROMless version can address up
to 64 KB of external data memory. External data memory
may be included with, or separated from, the external pro-
gram memory space.
DM
, an optional I/O function that can
be programmed to appear on pin
P34
, is used to distinguish
between data and program memory space (Figure 18). The
state of the
DM
signal is controlled by the type of instruction
being executed. An
LDC
Op Code references
PROGRAM
(
DM
inactive) memory, and an
LDE
instruction references
data (
DM
active Low) memory. The user must configure
Port 3 Mode Register (
P3M
) bits
D3
and
D4
for this mode.
This feature is not usable for devices in 28-pin package.
When used in ROM mode, the Z86C46 cannot access any
external data memory.
The Z86C44/C45 can access exter-
Figure 17. Program Memory Map
for Z86C34/35/44/45
12
11
10
9
8
7
6
5
4
3
2
1
0
On-Chip
ROM
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IRQ5
16383/32767
External/Internal
ROM and RAM
65535
16382/32766
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
30
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
n a l p r o g r a m a n d d a t a m e m o r y f r o m a d d r e s s e s
16384
/
32768
to
65535
.
Expanded Register File (ERF).
The Z8 register file is ex-
panded to allow for additional system control registers, and
for mapping of additional peripheral devices along with I/O
ports into the register address area. The Z8 register address
space
R0
through
R15
is implemented as 16 groups of 16
registers per group (Figure 19). These register groups are
known as the Expanded Register File (
ERF
). Bits 74 of reg-
ister
RP
select the working register group. Bits
30
of reg-
ister
RP
select the expanded register group. Three system
configuration registers reside in the Expanded Register File
at Bank F (
PCON
,
SMR
,
WDTMR
). The rest of the Expand-
ed Register is not physically implemented, and is open for
future expansion.
Figure 18. Data Memory Map
65535
16384/32768
0
External
Data
Memory
Not Addressable
16383/32767
ROM Mode
65535
0
External
Data
Memory
ROMless Mode
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
31
Register File.
The register file consists of four I/O port reg-
isters, 236 general-purpose registers and 15 control and sta-
tus registers (
R0R3
,
R4R239
and
R240R255
, respective-
ly), plus three system configuration registers in the
expanded register group. The instructions access registers
directly or indirectly through an 8-bit address field. As a re-
sult, a short, 4-bit register address can use the Register
Pointer (Figure 20). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16
Figure 19. Expanded Register File Architecture
7
6
5
4
3
2
1
0
Working Register
Group Pointer
Expanded Register
Group Pointer
%FF
%FO
%7F
%0F
%00
Z8 Reg. File
REGISTER POINTER
% FF
% FE
% FD
% FC
% FB
% FA
% F9
% F8
% F7
% F6
% F5
% F4
% F3
% F2
% F1
% F0
SPL
SPH
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
0
U
0
0
U
0
0
1
U
U
U
U
0
% (F) 0F
% (F) 0E
% (F) 0D
% (F) 0C
% (F) 0B
% (F) 0A
% (F) 09
% (F) 08
% (F) 07
% (F) 06
% (F) 05
% (F) 04
% (F) 03
% (F) 02
% (F) 01
% (F) 00
WDTMR
SMR
0
U
U
0
U
1
0
1
U
U
U
U
0
0
U
U
0
U
0
0
1
U
U
U
U
0
0
U
U
0
U
0
0
1
U
U
U
U
0
0
U
U
0
U
1
0
1
U
U
U
U
0
0
U
U
0
U
1
0
1
U
U
U
U
0
0
U
U
0
U
0
0
1
U
U
0
U
0
0
U
U
0
U
1
0
1
0
U
0
U
0
U
U
U
0
1
1
0
1
0
0
1
0
0
0
0
0
1
1
1
1
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
REGISTER
EXPANDED REG. GROUP (F)
RESET CONDITION
REGISTER
EXPANDED REG. GROUP(0)
RESET CONDITION
REGISTER
Z8 STANDARD CONTROL REGISTERS
RESET CONDITION
% (0) 03
P3
% (0) 02
P2
% (0) 01
P1
% (0) 00
P0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
*
*
*
**
Reserved
Reserved
SMR2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
*
*
*
1
1
1
1
1
1
1
0
Notes:
U = Unknown
For ROMless Reset condition: "10110110".
*Will not be reset with a STOP-Mode Recovery.
**Will not be reset with a STOP-Mode Recovery, except bit D0.
Not available on 28-pin packages.
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
U
U
U
U
0
0
*
X
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
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32
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
continuous locations. The Register Pointer addresses the
starting location of the active working register group.
Figure 20. Register Pointer
D7
D6
D5
D4
D3
D2
D1
D0
Expanded Register Group
Working Register Group
RP
R253
Default setting after RESET = 00000000
Figure 21. Register Pointer--Detail
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7 r6
r5 r4
R253
(Register Pointer)
I/O Ports
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register
r3 r2
r1 r0
Register Group 1
Register Group 0
R15 to R0
Register Group F
R15 to R4
R3 to R0
R15 to R0
FF
F0
0F
00
1F
10
2F
20
3F
30
4F
40
5F
50
6F
60
7F
70
Z86C34/C35/C36/C44/C45/C46
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CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
33
General-Purpose Registers (GPR).
These registers are
undefined after the device is powered up. The registers keep
their most recent value after any
RESET
, as long as the
RE-
SET
occurs in the
V
CC
voltage-specified operating range.
These do not keep their most recent state from a Low Volt-
age Protection
(
V
LV
)
RESET
if the
V
CC
drops below 1.8V.
Note: Register Bank
E0EF
is only accessed through working
register and indirect addressing modes.
RAM Protect.
The upper portion of the RAM's address
spaces
%80F
to
%EF
(excluding the control registers) are
protected from writing. The RAM Protect bit option is
mask-programmable and is selected by the customer when
the ROM code is submitted. After the mask option is se-
lected, the user activates this feature from the internal ROM
code to turn off/on the RAM Protect by loading either a
0
or
1
into the
IMR
register, bit
D6
. A
1
in
D6
enables RAM
Protect.
Stack.
The Z8 internal register file is used for the stack. The
16-bit Stack Pointer (
R254R255
) is used for the external
stack, which can reside anywhere in the data memory for
ROMless mode. An 8-bit Stack Pointer (
R255
) is used for
the internal stack that resides within the 236 general-pur-
pose registers (
R4R239
). Stack Pointer High
(SPH)
is used
as a general-purpose register when using internal stack
only. The devices in 28-pin packages use the 8-bit stack
pointer (
R255
) for internal stack only.
Note:
R254
and
R255
are set to
00h
after any
RESET
or Stop-
Mode Recovery.
Counter/Timers.
There are two 8-bit programmable
counter/timers (
T0T1
), each driven by its own 6-bit pro-
grammable prescaler. The
T1
prescaler is driven by internal
or external clock sources; however, the
T0
prescaler is driv-
en by the internal clock only (Figure 22).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each pres-
caler drives its counter, which decrements the value (
1
to
256
) that is loaded into the counter. When the counter
reaches the end of the count, a timer interrupt request,
IRQ4
(
T0
) or
IRQ5
(
T1
), is generated.
The counters can be programmed to
START
,
STOP
, restart
to
CONTINUE
, or restart from the initial value. The counters
can also be programmed to
STOP
upon reaching
0
(single
pass mode) or to automatically reload the initial value and
continue counting (modulon continuous mode).
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for
T1
is user-definable and is either the internal mi-
croprocessor clock divide-by-four, or an external signal in-
put through Port 3. The Timer Mode register configures the
external timer input (
P31
) as an external clock, a trigger in-
put that can be retriggerable or nonretriggerable, or as a gate
input for the internal clock. The counter/timers can be cas-
caded by connecting the
T0
output to the input of
T1
.
T
IN
Mode is enabled by setting
R243 PRE1
bit
D1
to
0
.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
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34
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
Interrupts.
The Z8 features six different interrupts from six
different sources. These interrupts are maskable, prioritized
(Figure 23) and the six sources are divided as follows: four
sources are claimed by Port 3 lines
P33P30
, and two in
counter/timers (Table 11). The Interrupt Mask Register glo-
bally or individually enables or disables the six interrupt re-
quests.
Figure 22. Counter/Timer Block Diagram
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
16
4
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
2
Clock
Logic
IRQ4
T
P36
IRQ5
Internal Data Bus
Write
Write
Read
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
Write
Read
Internal Data Bus
External Clock
Internal
Clock
D0 (SMR)
4
2
OSC
D1 (SMR)
OUT
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CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
35
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. An interrupt ma-
chine cycle activates when an interrupt request is granted.
This action disables all subsequent interrupts, saves the Pro-
gram Counter and Status Flags, and then branches to the
program memory vector location reserved for that interrupt.
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte con-
tain the 16-bit address of the interrupt service routine for
that particular interrupt request. To accommodate polled in-
terrupt systems, interrupt inputs are masked and the Inter-
rupt Request register is polled to determine which of the in-
terrupt requests require service.
Figure 23. Interrupt Block Diagram
Table 11. Interrupt Types, Sources, and Vectors
Name
Source
Vector
Location
Comments
IRQ0
DAV0, IRQ0
0, 1
External (P32), Rise Fall Edge Triggered
IRQ1,
IRQ1
2, 3
External (P33), Fall Edge Triggered
IRQ2
DAV2, IRQ2, T
IN
4, 5
External (P31), Rise Fall Edge Triggered
IRQ3
UART (ASCI)
6, 7
External (P30), Fall Edge Triggered
IRQ4
T0
8, 9
Internal
IRQ5
T1
10, 11
Internal
Interrupt
Edge
Select
IRQ (D6, D7)
IRQ1, 3, 4, 5
IRQ
IMR
IPR
PRIORITY
LOGIC
6
Global
Interrupt
Enable
Vector Select
Interrupt
Request
IRQ0 IRQ2
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
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36
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
An interrupt resulting from
AN1
maps to
IRQ2
, and an in-
terrupt from
AN2
maps to
IRQ0
. Interrupts
IRQ2
and
IRQ0
may be rising, falling, or both edge-triggered, and are pro-
grammable by the user. The software may poll to identify
the state of the pin. When in analog mode, the
IRQ1
gener-
ates by the Stop-Mode Recovery source selected by
SMR
Reg. bits
D4
,
D3
,
D2
, or
SMR2
D1
or
D0
.
Programming bits for the Interrupt Edge Select are located
in the IRQ register (
R250
), bits
D7
and
D6
. The configura-
tion is indicated in Table 12.
Clock.
The Z8 on-chip oscillator features a high-gain, par-
allel-resonant amplifier for connection to a crystal,
LC
,
RC
,
ceramic resonator, or any suitable external clock source
(
XTAL1 = INPUT
,
XTAL2 = OUTPUT
). The crystal should
be AT-cut, 16 MHz maximum, with a series resistance (
RS
)
of less than or equal to 100 Ohms when counting from
1 MHz to 16 MHz.
The crystal should be connected across
XTAL1
and
XTAL2
using the vendor's recommended capacitor values from
each pin directly to the device Ground pin to reduce ground-
noise injection into the oscillator. The
RC
oscillator option
is mask-programmable on the Z8 and is selected by the cus-
tomer at the time when the ROM code is submitted.
Notes: The
RC
option is available up to 8 MHz. The
RC
oscillator configuration must be an external resistor
connected from
XTAL1
to
XTAL2
, with a frequency-
setting capacitor from
XTAL1
to Ground (Figure 24).
For better noise immunity, the capacitors should be tied
directly to the device Ground pin (
V
SS
).
Table 12. IRQ Register
IRQ
Interrupt Edge
D7
D6
P31
P32
0
0
F
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Z86C34/C35/C36/C44/C45/C46
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CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
37
Power-On-Reset (POR).
A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (
POR
) timer function. The
POR
time allows
V
CC
and the
oscillator circuit to stabilize before instruction execution
begins.
The
POR
timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power fail to Power OK status.
2. Stop-Mode Recovery (if
D5
of
SMR = 1
).
3.
WDT
time-out.
The
POR
time is specified as
T
POR
. Bit
5
of the Stop-Mode
Register determines whether the
POR
timer is bypassed af-
ter Stop-Mode Recovery (typical for external clock,
RC
/
LC
oscillators).
HALT. HALT
turns off the internal CPU clock, but not the
XTAL
oscillation. The counter/timers and external inter-
rupts
IRQ0
,
IRQ1
,
IRQ2
, and
IRQ3
remain active. The de-
vices are recovered by interrupts and are either externally
or internally generated. An interrupt request must be en-
abled and executed to exit
HALT
mode. After the interrupt
service routine, the program continues from the instruction
after the
HALT
.
In order to enter
STOP
(or
HALT
) mode, it is necessary to
first flush the instruction pipeline to avoid suspending ex-
ecution in mid-instruction. Therefore, the user must execute
a
NOP
(Op Code =
FFH
) immediately before the appropriate
sleep instruction. For example:
STOP.
This instruction turns off the internal clock and ex-
ternal crystal oscillation. It also reduces the standby current
to 10 A or less. The
STOP
mode is terminated by a
RESET
only, either by
WDT
time-out,
POR
,
SMR
recovery, or ex-
ternal reset. As a result, the processor restarts the applica-
tion program at address
000Ch
. A
WDT
time-out in
STOP
mode affects all registers the same as if a Stop-Mode Re-
covery occurred via a selected Stop-Mode Recovery source
except that the
POR
delay is enabled even if the delay is se-
lected for disable.
Note: If a permanent
WDT
is selected, the
WDT
runs in all
modes and cannot be stopped or disabled if the onboard
RC
oscillator is selected to drive the
WDT
.
Port Configuration Register (PCON).
The
PCON
regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
Figure 24. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
C1
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator or
Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
LC
C1, C2 = 22 pF
L = 130 uH *
f = 3 MHz *
RC
@ 5V V (TYP)
C1 = 33 pF *
R = 1K *
f = 6 MHz *
External Clock
L
R
*Preliminary value including pin parasitics
**Device ground pin
V **
SS
V **
SS
V **
SS
V **
SS
V **
SS
CC
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT Mode
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
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P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
0, 1, 2, and 3, and low-EMI oscillator. The
PCON
register
is located in the expanded register file at Bank F, location
00h
(Figure 25).
Comparator Output Port 3 (D0).
Bit
0
controls the com-
parator use in Port 3. A
1
in this location brings the com-
parator outputs to
P34
and
P37
, and a
0
releases the Port to
its standard I/O configuration. The default value is
0
.
Port 1 Open-Drain (D1).
Port 1 can be configured as an
open-drain by resetting this bit (
D1 = 0
) or configured as
push-pull active by setting this bit (
D1 = 1
). The default val-
ue is
1
. The user must set
D1 = 1
for devices in 28-pin pack-
ages.
Port 0 Open-Drain (D2).
Port 0 can be configured as an
open-drain by resetting this bit (
D2 = 0
) or configured as
push-pull active by setting this bit (
D2 = 1
). The default val-
ue is
1
.
Low-EMI Port 0 (D3).
Port 0 can be configured as a low-
EMI port by resetting this bit (
D3 = 0
) or configured as a
Standard Port by setting this bit (
D3 = 1
). The default value
is
1
.
Low-EMI Port 1 (D4).
Port 1 can be configured as a low-
EMI port by resetting this bit (
D4 = 0
) or configured as a
Standard Port by setting this bit (
D4 = 1
). The default value
is
1
. The user must set
D4 = 1
for devices in 28-pin packages.
Note: For emulator, this bit must be set to
1
.
Low-EMI Port 2 (D5).
Port 2 can be configured as a low-
EMI port by resetting this bit (
D5 = 0
) or configured as a
Standard Port by setting this bit (
D5 = 1
). The default value
is
1
.
Low-EMI Port 3 (D6).
Port 3 can be configured as a low-
EMI port by resetting this bit (
D6 = 0
) or configured as a
Standard Port by setting this bit (
D6 = 1
). The default value
is
1
.
Low-EMI OSC (D7).
This bit of the
PCON
Register con-
trols the low-EMI noise oscillator. A
1
in this location con-
figures the oscillator,
DS
,
AS
and
R/W
with standard drive,
while a
0
configures the oscillator,
DS
,
AS
and
R/W
with
low noise drive. The low-EMI mode reduces the drive of
the oscillator (OSC). The default value is
1
.
Note: Maximum external clock frequency of 4 MHz when run-
ning in the
low-EMI
oscillator mode.
Low-EMI Emission.
The Z8 can be programmed to operate
in a low-EMI emission mode in the
PCON
register. The os-
cillator and all I/O ports can be programmed as low-EMI
emission mode independently. Use of this feature results in:
The pre-drivers slew rate reduced to 10 ns (typical)
Low-EMI output drivers exhibit resistance of 200 Ohms
(typical)
Low-EMI Oscillator
Internal
SCLK/TCLK = XTAL
operation limited to a
maximum of 4 MHz250 ns cycle time, when
LOW
EMI OSCILLATOR
is selected and system clock (
SCLK
= XTAL
,
SMR REGISTER BIT D1 = 1
)
Stop-Mode Recovery Register (SMR).
This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figures 26 and 27). All bits are
WRITE ONLY
, except bit
7
, which is
READ
ONLY
. Bit
7
is a flag bit that is hardware set on the condition of
STOP
recovery and
RESET
by a power-on cycle. Bit
6
controls
whether a low level or a high level is required from the re-
covery source. Bit
5
controls the reset delay after recovery.
Bits 2, 3, and 4, or the
SMR
register, specify the source of
the Stop-Mode Recovery signal. Bits
0
and
1
determine the
time-out period of the
WDT
. The
SMR
is located in Bank
F of the Expanded Register Group at address
0BH
.
Figure 25. Port Configuration Register (PCON)
(WRITE ONLY)
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
D7
D6
D5
D4
D3
D2
D1
D0
PCON (FH) 00H
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
*Default Setting After Reset
Must be set to one for devices
in 28-pin packages
0 Port 1 Open Drain
1 Port 1 Push-pull Active*
0 Port 1 Low EMI
1
Port 1
Standard*
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CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
39
SCLK/TCLK Divide-by-16 Select (D0).
D0 of the
SMR
controls a divide-by-16 prescaler of
SCLK/TCLK
. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (
SCLK
control) and/or
HALT
mode (where
TCLK
sources
counter/timers and interrupt logic). This bit is reset to
D0
= 0
after a Stop-Mode Recovery.
External Clock Divide-by-Two (D1).
This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (
SCLK
) and Timer Clock (
TCLK
) are
equal to the external clock frequency divided by 2. The
SCLK/TCLK
is equal to the external clock frequency when
this bit is set (
D1 = 1
). Using this bit together with
D7
of
PCON
further helps lower EMI (that is,
D7
(
PCON
) = 0,
D1
(SMR) = 1
). The default setting is
0
. Maximum external
clock frequency is 4 MHz when
SMR BIT D1 = 1
where
SCLK/TCLK = XTAL
.
Stop-Mode Recovery Source (D2, D3, and D4).
T h e s e
three bits of the
SMR
specify the wake-up source of the
STOP
recovery (Figure 28 and Table 13). When the Stop-
Mode Recovery Sources are selected in this register, then
SMR2
register bits
D0
,
D1
must be set to
0
.
Note: If the Port 2 pin is configured as an output, this output
level is read by the
SMR
circuitry.
Figure 26. Stop-Mode Recovery Register
(WRITE ONLY Except Bit D7, Which Is READ ONLY)
Figure 27. Stop-Mode Recovery Register 2
(0F) DH: WRITE ONLY
D7
D6
D5
D4
D3
D2
D1
D0
SMR (FH) 0B
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
*
Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
D7
D6
D5
D4
D3
D2
D1
D0
SMR2 (0F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
40
P R E L I M I N A R Y
DS007601-Z8X0499
FUNCTIONAL DESCRIPTION (Continued)
Stop-Mode Recovery Delay Select (D5).
T h i s b i t , i f
High, enables the
T
POR
RESET
delay after Stop-Mode Re-
covery. The default configuration of this bit is
1
. If the fast
wake up is selected, the Stop-Mode Recovery source must
be kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6).
A
1
in this bit
position indicates that a high level on any one of the recov-
ery sources wakes the Z8 from
STOP
mode. A
0
indicates
low-level recovery. The default is
0
on
POR
(Figure 28).
This bit is used for either
SMR
or
SMR2
.
Cold or Warm Start (D7).
This bit is set by the device
upon entering
STOP
mode. A
0
in this bit (cold) indicates
that the device resets by
POR
/
WDT
RESET
. A
1
in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note: If the Port 2 pin is configured as an output, this output
level is read by the
SMR2
circuitry.
Figure 28. Stop-Mode Recovery Source
P30
P31
P32
P33
P27
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
RESET
SMR
SMR
SMR
D4 D3 D2
0 0 1
0 1 0
0 1 1
D4 D3 D2
1 0 0
D4 D3 D2
1 0 1
MUX
SMR
SMR
D4 D3 D2
1 1 0
D4 D3 D2
1 1 1
P20
P23
P20
P27
SMR2
SMR2
D1 D0
1 1
D1 D0
1 1
P20
P23
P20
P27
SMR D4 D3 D2
0 0 0
V
SMR2 D1 D0
0 0
DD
V
DD
Table 13. Stop-Mode Recovery Source
SMR:432
D4 D3 D2
Operation
Description of Action
0
0
0
POR and/or external reset recovery
0
0
1
P30 transition
0
1
0
P31 transition (not in Analog Mode)
0
1
1
P32 transition (not in Analog Mode)
1
0
0
P33 transition (not in Analog Mode)
1
0
1
P27 transition
1
1
0
Logical NOR of P20 through P23
1
1
1
Logical NOR of P20 through P27
Z86C34/C35/C36/C44/C45/C46
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CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
41
Stop-Mode Recovery Register 2 (SMR2).
This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then
SMR
Register. Bits
D2
,
D3
, and
D4
must be
0
.
Watch-Dog Timer Mode Register (WDTMR).
The
WDT
is a retriggerable one-shot timer that resets the Z8 if it reach-
es its terminal count. The
WDT
is initially enabled by exe-
cuting the
WDT
instruction and refreshed on subsequent ex-
ecutions of the
WDT
instruction. The
WDT
circuit is driven
by an onboard
RC
oscillator or external oscillator from the
XTAL1
pin. The
POR
clock source is selected with bit
4
of
the
WDT
register (Figure 29).
WDT
instruction affects the Z (Zero), S (Sign), and V (Over-
flow) flags. The
WDTMR
must be written to within 64 in-
ternal system clocks. After that, the
WDTMR
is
WRITE
-pro-
tected.
Note:
WDT
time-out while in
STOP
mode does not reset
SMR
,
PCON
,
WDTMR
,
P2M
,
P3M
, Ports 2 & 3 Data Registers,
but the
POR
delay counter is still enabled even though
the
SMR
stop delay is disabled.
WDT Time Select. (D0,D1).
Selects the
WDT
time period
and is configured as indicated in Table 15.
Table 14. Stop-Mode Recovery Source
SMR:10
D1 D0
Operation
Description of Action
0
0
POR and/or external reset recovery
0
1
Logical AND of P20 through P23
1
0
Logical AND of P20 through P27
Figure 29. Watch-Dog Timer Mode Register (WRITE ONLY)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP INT RC OSC External Clock
00 3.5 ms 128 TpC
01
*
7 ms 256 TpC
10 14 ms 512 TpC
11 56 ms 2048 TpC
WDT During HALT
0 OFF
1 ON
*
WDT During STOP
0 OFF
1 ON
*
XTAL1/INT RC Select for WDT
0 On-Board RC
*
1 XTAL
Reserved (must be 0)
*
Default setting after RESET
Table 15. WDT Time Select
D1
D0
Timeout of
Internal RC OSC
Timeout of
System Clock
0
0
3.5 ms min
128 SCLK
0
1
7 ms min
256 SCLK
1
0
14 ms min
512 SCLK
1
1
56 ms min
2048 SCLK
Notes:
SCLK = system bus clock cycle.
The default on RESET is 7 ms.
Values provided are for V
CC
= 5.0V.
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FUNCTIONAL DESCRIPTION (Continued)
WDTMR During HALT (D2).
This bit determines whether
or not the
WDT
is active during
HALT
mode. A
1
indicates
active during
HALT
. The default is
1
.
WDTMR During STOP (D3).
This bit determines whether
or not the
WDT
is active during
STOP
mode. Because
XTAL
clock is stopped during
STOP
mode, the on-board
RC
must
be selected as the clock source to the
POR
counter. A
1
in-
dicates active during
STOP
. The default is
1
.
Note: If permanent
WDT
is selected, the
WDT
runs in all
modes and can not be stopped or disabled if the on board
RC
oscillator is selected as the clock source for
WDT
.
Clock Source for WDT (D4).
This bit determines which
oscillator source is used to clock the internal
POR
and
WDT
counter chain. If the bit is a
1
, the internal
RC
oscillator is
bypassed and the
POR
and
WDT
clock source is driven from
the external pin,
XTAL1
. The default configuration of this
bit is
0
which selects the internal
RC
oscillator.
WDTMR Register Accessibility.
The
WDTMR
register is
accessible only during the first 60 internal system clock cy-
cles from the execution of the first instruction after Power-
On Reset, Watch-Dog Reset, or Stop-Mode Recovery. Af-
ter this point, the register cannot be modified by any means,
intentional or otherwise. The
WDTMR
cannot be read and
is located in bank F of the Expanded Register Group at ad-
dress location
0FH
(Figure 30).
Note: The
WDT
can be permanently enabled (automatically
enabled after
RESET
) through a mask programming op-
tion. The option is selected by the customer at the time
of ROM code submission. In this mode,
WDT
is always
activated when the device comes out of
RESET
. Execu-
tion of the
WDT
instruction serves to refresh the
WDT
time-out period.
WDT
operation in the
HALT
and
STOP
Modes is controlled by
WDTMR
programming. If this
mask option is not selected at the time of ROM code sub-
mission, the
WDT
must be activated by the user through
the
WDT
instruction and is always disabled by any reset
to the device.
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43
Low Voltage Protection.
An onboard Voltage Compara-
tor checks that
V
CC
is at the required level to ensure correct
operation of the device.
RESET
is globally driven if
V
CC
is
below the specified voltage (Low Voltage Protection). The
minimum operating voltage is varying with the temperature
and operating frequency, while the Low Voltage Protection
(
V
LV
) varies with temperature only.
The Low Voltage Protection trip voltage (
V
LV
) is less than
3V and more than 1.4V under the following conditions.
Note: The internal clock frequency relationship to the
XTAL
clock is dependent on
SMR BIT 0 1
setting.
The device functions normally at or above 3.0V under all
conditions. Below 3.0V, the device functions normally until
the Low Voltage Protection trip point (
V
LV
) is reached, for
the temperatures and operating frequencies in Case 1 and
Case 2, above. The device is guaranteed to function normally
at supply voltages above the Low Voltage Protection trip
point. The actual Low Voltage Protection trip point is a func-
tion of temperature and process parameters (Figure 36).
Figure 30. Resets and WDT
CLK
18 Clock RESET
Generator
RESET
Clear
WDT TAP SELECT
Internal
RC OSC.
CK
CLR
5ms POR
5ms 15ms 25ms 100ms
2V Operating
Voltage Det.
Internal
RESET
WDT Select
(WDTMR)
CLK Source
Select
(WDTMR)
XTAL
V
V
From Stop
Mode
Recovery
Source
WDT
Stop Delay
Select (SMR)
+
4 Clock
Filter
WDT/POR Counter Chain
M
U
X
Reset
DD
LV
Table 16. Maximum (V
LV
) Conditions:
Case 1:
T
A
= 40C, +105C, Internal Clock
Frequency equal or less than 4 MHz
Case 2:
T
A
= 40C, +85C, Internal Clock
Frequency equal or less than 6 MHz
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DS007601-Z8X0499
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (ASCI)
Key features of the ASCI include:
Full-duplex operation
Programmable data format
7 or 8 data bits with optional ninth bit for multiprocessor
communication
P30
and
P37
can be used as general-purpose I/O as long
as the ASCI channels are disabled
One or two
STOP
bits
Odd, even or no parity
Programmable interrupt conditions
Four level data/status FIFOs for the receiver
Receive parity, framing and overrun error detection
Break detection and generation
Transmit Data Register.
Data written to the ASCI Trans-
mit Data Register (
TDR
) is transferred to the Transmit Shift
Register(
TSR
) as soon as the
TSR
is empty. Data can be
written while the
TSR
is shifting out the previous byte of
data, providing double buffering for the transmit data. The
TDR
is
READ
- and
WRITE
-accessible. Reading from the
TDR
does not affect the ASCI data transmit operation cur-
rently in progress.
Transmit Shift Register.
When the ASCI Transmit Shift
Register (
TSR
) receives data from the ASCI Transmit Data
Register, the data is shifted out to the
TX
(
P37
) pin. When
transmission is completed, the next byte (if available) is au-
tomatically loaded from the
TDR
into the
TSR
and the next
transmission starts. If no data is available for transmission,
the
TSR
idles at a continuous High level. This register is
not program-accessible.
Receive Shift Register.
When the
RE
bit is set in the
CNTLA
register, the
RX
(
P30
) pin is monitored for a Low.
One-half bit-time after a Low is sensed at
RX
, the ASCI
samples
RX
again. If
RX
goes back to High, the ASCI
ignores the previous Low and resumes looking for a new
Low, but if
RX
is still Low, it considers
RX
a
START
bit
and proceeds to clock in the data based upon the selected
baud rate. The number of data bits, parity, multiprocessor
and
STOP
bits are selected by the
MOD2
,
MOD1
,
MOD0
and multiprocessor mode (
MP
) bits in the
CNTLA
and
CNTLB
registers.
After the data is received, the appropriate
MP
, parity and
one
STOP
bit are checked. Data and any errors are clocked
into the receive data and status FIFO during the
STOP
bit
if there is an empty position available. Interrupts and Re-
ceive Data Register Full Flag also goes active during this
time. If there is no space in the FIFO at the time that the
RSR
attempts to transfer the received data into it, an overrun
error occurs.
Receive Data FIFO.
When a complete incoming data byte
is assembled in the
RSR
, it is automatically transferred to
the 4-byte FIFO, which serves to reduce the incidence of
overrun errors. The top (oldest) character in the FIFO (if
any) can be read via the Receive Data Register (
RDR
).
The next incoming data byte can be shifted into the
RSR
while the FIFO is full, thus providing an additional level of
buffering. However, an overrun occurs if the receive FIFO
is still full when the receiver completes assembly of that
character and is ready to transfer it to the FIFO. If this sit-
uation occurs, the overrun error bit associated with the pre-
vious byte in the FIFO is set. The latest data byte is not trans-
ferred from the shift register to the FIFO in this case, and
is lost. When an overrun occurs, the receiver does not place
any further data in the FIFO until the most recent good byte
received arrives at the top of the FIFO and sets the Overrun
latch, and software then clears the Overrun latch by a
WRITE
of
0
to the
EFR
bit. Assembly of bytes continues in
the shift register, but this data is ignored until the byte with
the overrun error reaches the top of the FIFO and the status
is cleared.
When a break occurs (defined as a framing error with the
data equal to all zeros), the all-zero byte with its associated
error bits are transferred to the FIFO if it is not full and the
Break Detect bit in the
ASEXT
register is set. If the FIFO
is full, an overrun is generated, but the break, framing error
and data are not transferred to the FIFO. Any time a break
is detected, the receiver does not receive any more data until
the
RX
pin returns to a high state.
If the channel is set in multiprocessor mode and the
MPE
bit of the
CNTLA
register is set to
1
,then break, errors and
data are ignored unless the MP bit in the received character
is a
1
. The two conditions listed above could cause the miss-
ing of a break condition if the FIFO is full and the break
occurs or if the MP bit in the transmission is not a one with
the conditions specified above.
ASCI Status FIFO/Registers.
This FIFO contains Parity
Error, Framing Error,
RX
Overrun, and Break status bits as-
sociated with each character in the receive data FIFO. The
status of the oldest character (if any) can be read from the
ASCI status register, which also provides several other,
non-FIFOed status conditions.
The outputs of the error FIFO go to the set inputs of soft-
ware-accessible error latches in the status register. Writing
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45
a
0
to the
EFR
bit in
CNTLA
is the only way to clear these
latches. In other words, when an error bit reaches the top
of the FIFO, it sets an error latch. If the FIFO contains more
data and the software reads the next byte out of the FIFO,
the error latch remains set until the software writes a
0
to
the
EFR
bit. The error bits are cumulative, so if additional
errors are in the FIFO they set any unset error latches as they
reach the top.
Baud Rate Generator.
The baud rate generator features
two modes. The first provides a dual set of fixed clock di-
vide ratios as defined in
CNTLB
. In the second mode, the
BRG
is configured as a sixteen-bit down counter that divides
the processor clock by the value in a software accessible,
sixteen-bit, time-constant register. As a result, virtually any
frequency can be created by appropriately selecting the
main processor clock frequency. The
BRG
can also be dis-
abled in favor of the
SCLK
.
The Receiver and Transmitter subsequently divide the out-
put of the Baud rate Generator (or the signal from the
CLK
pin) by 1, 16 or 64 under the control of the
DR
bit in the
CNTLB
register and the
X1
bit in the ASCI Extension Con-
trol Register (
ASEXT
).
RESET.
During
RESET
, the ASCI is forced to the following
conditions:
FIFO Empty
All Error Bits Cleared (including those in the FIFO)
Receive Enable Cleared (
CNTLA BIT 6 = 0
)
Transmit Enable Cleared (
CNTLA BIT 5 = 0
)
Figure 31. ASCI Interface Diagram
Internal Address/Data Bus
ASCI Transmit Data Register
ASCI Status FIFO/Register
TDR (Bank:Ah,Addr :01h)
ASCI Transmit Shift Register
TSR
ASCI Receive Data FIFO
RDR (Bank:Ah,Addr:02h)
ASCI Receive Shift Register
RSR
ASCI Control Register A
CNTLA (Bank:Ah,Addr:03h)
ASCI Control Register B
CNTLB (Bank:Ah,Addr:04h)
STAT (Bank:Ah,Addr:08h)
ASCI Extension Control Reg.
ASEXT (Bank:Ah,Addr:05h)
ASCI Time Constant High
ASCI Time Constant Low
ASTCL (Bank:Ah,Add:06h)r
Baud Rate Generator
SCLK
(P37) TX
(P30) RX
ASCI
Control
IRQ3
Interrupt Request
**
**
Note: **Not Program
Accessible
ASTCH (Bank:Ah,Addr:07h)
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P R E L I M I N A R Y
DS007601-Z8X0499
INTERRUPTS
The ASCI channel generates one interrupt (
IRQ3
) from two
sources of interrupts: a receiver and a transmitter. In addi-
tion, there are several conditions that may cause these in-
terrupts to trigger. Figure 32 illustrates the different condi-
tions for each interrupt source enabled under program
control.
Figure 32. ASCI Interrupt Conditions and Sources
FIFO full
Overrun error
Framing Error
Parity Error
Start Bit
Receiver
Interrupt
Sources
Buffer Empty
Transmitter
Interrupt
Sources
ASCI
Interrupt
(IRQ3)
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EXPANDED REGISTER GROUP (A)
Figure 33. Expanded Register Group (A) Registers
%(A)0D RESERVED
%(A)0C RESERVED
%(A)0E RESERVED
%(A)0F RESERVED
%(A)00 RESERVED
%(A)01 TDR
%(A)02 RDR
%(A)03 CNTLA
%(A)04 CNTLB
%(A)05 ASEXT
%(A)06 ASTCL
%(A)07 ASTCH
%(A)08 STAT
%(A)09 GEN PURPOSE
u u u u u u u u
0 0 0 0 0 0 1 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1
0 0 0 1 0 0 0 0
u u u u u u u u
u u u u u u u u
*
*
*
*
*
*
*
*
* Not reset with a STOP-Mode Recovery.
%(A)0B RESERVED
%(A)0A RESERVED
B7
B6
B5
B4
B3
B2
B1
B0
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ASCI TRANSMIT DATA REGISTER (TDR)
(%(A)01H: READ/WRITE)
Data written to the ASCI Transmit Data Register (
TDR
) is
transferred to the Transmit Shift Register (
TSR
) as soon as
the
TSR
is empty. The
TSR
is not not software-accessible.
The ASCI transmitter is double-buffered so data can be
written to the
TDR
while the
TSR
is shifting out the previous
byte. Data can be written into and read out of the
TDR
. When
the
TDR
is read, the data transmit operation is not affected.
ASCI RECEIVE DATA REGISTER (RDR)
(%(A)02H: READ/WRITE)
When a complete incoming data byte is assembled in the
Receive Shift Register (
RSR
), it is automatically transferred
to the highest available location in the Receive Data FIFO.
The Receive Data Register (
RDR
) is the highest location in
the Receive Data FIFO. The
RDRF
bit in the
STAT
register
is set when one or more bytes is available from the FIFO.
The FIFO status for the character in the
RDR
is available
in the
STAT
register via bits
6
,
5
and
4
.
STAT
should be
read before reading the
RDR
. The data in both FIFO loca-
tions is popped when the character is read from the
RDR
.
ASCI CONTROL REGISTER A (CNTLA)
(%(A)03H: READ/WRITE)
Table 17. TDR Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
Transmit Data
W
Reset
U
U
U
U
U
U
U
U
Table 18. RDR Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
Receive Data
W
Reset
U
U
U
U
U
U
U
U
Table 19. CNTLA Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
Multiprocessor
Enable
(MPE)
Receiver
Enable
(RE)
Transmitter
Enable
(TE)
Reserved
Multiprocessor
Bit Received
(MPBR)
MOD2 MOD1 MOD0
W
Error Flag
Receive
(EFR)
Mode Select
Reset
0
0
0
1
0
0
0
0
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49
Bit 7 is the Multiprocessor Enable
The ASCI features a multiprocessor communication mode
that utilizes an extra data bit for selective communication
when a number of processors share a common serial bus.
Multiprocessor data format is selected when the
MP
bit in
the corresponding register is set to
1
. If multiprocessor
mode is not selected (
MP
bit in
CNTLB = 0
), multiprocessor
enable (
MPE
) has no effect. If multiprocessor mode is se-
lected (
MP
bit in
CNTLB = 1
),
MPE
enables or disables the
wake-up feature as follows. If
MPE
is set to
1
, only received
bytes in which the multiprocessor bit
(
MPB
) = 1 are treated
as valid data characters and loaded into the receiver FIFO
with corresponding error flags in the status FIFO. Bytes
with
MPB = 0
are ignored by the ASCI. If
MPE
is reset to
0
, all bytes are received by the ASCI, regardless of the state
of the
MPB
data bit.
Bit 6 is the Receiver Enable
When Receiver Enable(
RE
) is set to
1
,the ASCI receiver is
enabled. When
RE
is reset to
0
, the receiver is disabled and
any receive operation in progress is aborted. However, the
previous contents of the receiver data and status FIFO are
not affected.
Bit 5 is the Transmitter Enable
When Transmitter Enable(
TE
) is set to
1
,the ASCI trans-
mitter is enabled. When
TE
is reset to
0
, the transmitter is
disabled and any transmit operation in progress is aborted.
However, the previous contents of the transmitter data reg-
ister and the
TDRE
flag are not affected.
Bit 4 is Reserved
Bit 3 is the Multiprocessor Bit Receive
(Read only)
When multiprocessor mode is enabled (
MP
in
CNTLB = 1
),
this bit, when read, contains the value of the
MPB
bit for
the data byte currently available at the Receive Data Reg-
ister (the top of the receiver FIFO).
Bit 3 is the Error Flag Reset (WRITE ONLY)
When written to
0
, the error flags (
OVRN
,
FE
;
PE
in
STAT
and
BRK
in
ASEXT
) are cleared to
0
. This command self-
resets, and as a result, writing
EFR
to a
1
is not required.
Bits 20 are the ASCI Data Format Mode 2,1,0
These bits program the ASCI data format.
If
MOD1 = 1
, parity is checked on received data and a parity
bit is appended to the data bits in the transmitted data. Parity
Even/Odd (
PEO
) in
CNTLB
selects even or odd parity.
The ASCI serial data format is illustrated in Figure 34.
Table 20. Format Mode Control Bits
Bit
Name Function
Bit = 0
Bit = 1
2
MOD2 Number of Data Bits
7
8
1
MOD1 Parity Enabled
No
Parity
With
Parity
0
MOD0 Number of Stop Bits
1
2
Figure 34. ASCI Serial Data Format
7 or 8 bits Data Field
Start
Parity
Bit
Bit
1 or 2
Stop Bit(s)
it
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ASCI CONTROL REGISTER B (CNTLB)
(%(A)04H: READ/WRITE)
BIT 7 is the Multiprocessor Bit Transmit
When multiprocessor format is selected (
MP BIT = 1
), Mul-
tiprocessor Bit Transmit (
MPBT
) is used to specify the
MPB
data bit for transmission. If
MPBT = 1
, then a
1
is transmitted
in the
MPB
bit position. If
MPBT = 0
, a
0
is transmitted.
BIT 6 is the Multiprocessor Mode
When Multiprocessor Mode (
MP
) is set to
1
, the serial data
format is configured for multiprocessor mode, adding a bit
position whose value is specified in
MPBT
immediately af-
ter the specified number of data bits and preceding the spec-
ified number of
STOP
bits.
Note: The multiprocessor format does not provide parity. The
serial data format while in MP mode is illustrated in Fig-
ure 35.
If
MP = 0
, the data format is based on
MOD20
in
CNTLA
and may include parity.
Bit 5 is the BRG Prescaler
The Prescale bit specifies the baud rate generator prescale
factor when using the
SS2
0
bits to define the ASCI baud
rate (
BRG MODE = 0
). Writing a
0
to this bit sets the BRG
Prescaler to divide by 10. Setting this bit to a
1
sets the BRG
Prescaler to divide by 30. See the
Baud Rate Generation
Summary
for more information on setting the ASCI baud
rate.
Bit 4 is the Parity Even/Odd
Parity Even/Odd (
PEO
) controls the parity bit transmitted
on the serial output and the parity check on the serial input.
If
PEO
is cleared to
0
, even parity is transmitted and checked
If
PEO
is set to
1
, odd parity is transmitted and checked.
Bit 3 is the Divide Ratio
The Divide Ratio bit specifies the divider used to obtain the
baud rate from the data sampling clock when using the
SS20
bits to define the ASCI baud rate (
BRG MODE = 0
).
If
DR
is
0
, then
DIVIDE-BY-16
is used. If
DR
is set to a
1
,
then
DIVIDE-BY-64
is used. See the
Baud Rate Generation
Summary
for more information on setting the ASCI baud
rate.
Table 21. CNTLB Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
Multiprocessor
Bit
Transmitter
(MPBT)
Multiprocessor
Mode
(MP)
Parity
Even/Odd
(PEO)
Divide Ratio
(DR)
SS2
SS1
SS0
W
Prescale
(PR)
Clock Source
and Speed
Reset
0
0
0
0
0
1
1
1
Figure 35. MP Mode Serial Data Format
7 or 8 bits Data Field
Start Bit
MPB
1 or 2
Stop Bit(s)
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Bit 2,1 are the Clock Source and Speed Select
When the
BRG
mode bit in the
ASEXT
register is set to
0
,
these 3 bits, along with
DR
and
PR
in this register define
the ASCI baud rate. Bits
2
,
1
and
0
specify a power-of-two
divider of the
SCLK
as defined in Table 22. These bits
should never be set to all
1
s or erratic results may occur.
See the
Baud Rate Generation Summary
for more informa-
tion on setting the ASCI baud rate.
DR
Sampling Clock
0
Divide by 16
1
Divide by 64
Table 22. Clock Source and Speed Bits
SS2
SS1
SS0
Divider (DIV)
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
Reserved
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
52
P R E L I M I N A R Y
DS007601-Z8X0499
ASCI EXTENSION CONTROL REGISTER (ASEXT)
(%(A)05H: READ/WRITE)
BIT 7 is the RX State (READ ONLY)
Provides the real time state of
RX
, the channel's receive data
input pin--
P30
.
BIT 6 is Reserved
When read, this bit reflects the default value
0
. When
WRITE
, this bit is ignored.
Bit 5 is Reserved
When read, this bit reflects the default value
0
. When
WRITE
, this bit is ignored.
Bit 4 is the X1 Bit Clock
Reserved--must be set to
0
or erratic results may occur.
Bit 3 is the BRG Mode
When this bit is set to a
1
, the ASCI's baud rate is set by
the 16-bit programmable divider programmed in ASCI
Time Constant High
(ASTH
) and ASCI Time Constant Low
(
ASTL
). If this bit is set to a
0
, the baud rate is defined by
the
PR
bit, the
DR
bit, and the
SS20
bits in the
CNTLB
reg-
ister. In either case, the source for the baud rate generator
is the
SCLK
. See the
Baud Rate Generation Summary
for
more information on setting the ASCI baud rate.
Bit 2 is the Rx Interrupt on Start
If software sets this bit to
1
,a receive interrupt is requested
(in a combinatorial fashion) when a
START
bit is detected
on
RX
. Such a receive interrupt is always followed by the
setting of
RDRF
in the middle of the
STOP
bit. This interrupt
request must be cleared by writing this bit back to a
0
. Writ-
ing a
1
to this bit has no effect. One function of this feature
is to wake the part from Sleep mode when a character ar-
rives, so that the ASCI receives clocking with which to pro-
cess the character. Another function is to ensure that the as-
sociated interrupt service routine is activated in time to
sense the setting of
RDRF
in the status register, and to start
a timer for baud rate measurement at that time.
Bit 1 is the Break Detect (READ ONLY)
This status bit is set to a
1
when a Break is detected, defined
as a framing error with the data bits all equal to
0
. The all-
zero byte with its associated error bits are transferred to the
FIFO if it is not full. If the FIFO is full, an overrun is gen-
erated, but the break, framing error and data are not trans-
ferred to the FIFO. Any time a break is detected, the receiver
do not receive any more data until the
RX
pin returns to a
High state. When set, this bit remains set until it is cleared
by writing a
0
to the
EFR
bit in the
CNTLA
register.
Bit 0 is the Send Break
Setting this bit to a
1
forces the channel's transmitter data
output pin,
TX
, to a Low for as long as it remains set. Before
starting the break, any character(s) in the
TSR
and in the
TDR
are completely transmitted. If a character is loaded into
the
TDR
while a break is being generated, that character is
held until the break is terminated and transmitted.
Table 23. ASEXT Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
RX State
(RX)
Reserved
Reserved
Reserved
(must be 0)
BRG Mode
(BRGM)
RX
Interrupt on
Start Bit
(RIS)
Break
Detect
(BD)
Send Break
(SB)
W
Reset
P30
0
0
0
0
0
0
0
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
53
ASCI TIME CONSTANT REGISTER (ASTL)
(%(A)06H: READ/WRITE)
ASCI TIME CONSTANT REGISTER (ASTH)
(%(A)07H: READ/WRITE)
The
ASTL
and
ASTH
registers are only used when the
BRG
mode bit in the
ASEXT
register is set to a
1
. These two 8-
bit registers form a 16-bit counter with a flip-flop logic cir-
cuit (
DIVIDE-BY-2
) on the output so that the final BRG out-
put is symmetrical. The values written to these registers de-
termine the time constant from which the baud rate is
generated.
Table 24. ASTL Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
ASCI Time Constant Low
W
Reset
1
1
1
1
1
1
1
1
Table 25. ASTH Register Bit Functions
Bit
7
6
5
4
3
2
1
0
R
ASCI Time Constant High
W
Reset
1
1
1
1
1
1
1
1
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
54
P R E L I M I N A R Y
DS007601-Z8X0499
ASCI STATUS REGISTER (STAT)
(%(A)08H: READ/WRITE)
BIT 7 is the Receive Data Register Full
RDRF
is set to
1
when the receiver transfers a character from
the
RSR
into an empty
Rx
FIFO.
Note: If a framing or parity error occurs,
RDRF
is still set and
the receive data (which generated the error) is still load-
ed into the FIFO.
When there is more than one character in the FIFO, and soft-
ware reads a character,
RDRF
either remains set or is cleared
and immediately set again.
RDRF
is cleared to
0
when the
FIFO becomes empty after reading the
RDR
and during
Power-On Reset.
Bit 6 is the Overrun Error
An overrun occurs if the receive FIFO is still full when the
receiver completes assembly of a character and is ready to
transfer it to the FIFO. If this situation occurs, the overrun
error bit associated with the previous byte in the FIFO is
set. In this case, the latest data byte is not transferred from
the shift register to the FIFO and is lost.
When an overrun occurs, the receiver does not place any
further data in the FIFO until the most recent good byte
received (the byte with the associated overrun error bit set)
moves to the top of the FIFO and sets the Overrun latch,
and software then clears the Overrun latch. Assembly of
bytes continues in the shift register, but this data is ignored
until the byte with the overrun error reaches the top of the
FIFO and the status is cleared. When set, the bit remains
set until it is cleared by writing a
0
to the
EFR
bit in the
CNTLA
register. The bit is also cleared during Power-On
Reset.
Bit 5 is the Parity Error
A parity error is detected when parity generation and check-
ing is enabled by the
MOD1
bit in the
CNTLA
register and
a character has been assembled in which the parity does not
match that specified by the
PEO
bit in
CNTLB
.
Note:
PE
is FIFOed and the error bit is not actually set until the
associated data becomes available for reading in the
RDR
.
When set, the bit remains set until it is cleared by writing
a
0
to the
EFT
bit in the
CNTLA
register. The bit is cleared
at Power-On Reset.
Bit 4 is the Framing Error
A framing error is detected when the
STOP
bit of a character
is sampled as a
0
(space). Like
PE
,
FE
is FIFOed and the
error bit is not actually set until the associated data becomes
available for reading in the
RDR
. When set, the bit remains
set until it is cleared by writing a
0
to the
EFR
bit in the
CNTLA
register. The bit is cleared at Power-On Reset.
Bit 3 is the Receiver Interrupt Enable
RIE
should be set to a
1
to enable ASCI receive interrupt
requests. An interrupt (
IRQ3
) is generated when
RDRF
(bit
7
of the
STAT
register) is a
1
. A receive interrupt is also
generated if this bit is set to a
1
, bit
2
of the
ASEXT
register
(
RX
interrupt on the
START
bit) is set to a
1
, and a
START
bit is detected by the receiver.
Table 26. ASCI Status Register (STAT)
Bit
7
6
5
4
3
2
1
0
R
Receive
Data
Register
Full
(RDRF)
Overrun
Error
(OE)
Parity Error
(PE)
Framing
Error
(FE)
Receiver
Interrupt
Enable
(RIE)
Reserved
Transmit
Data
Register
Empty
TDRE)
Transmitter
Interrupt
Enable
(TIE)
W
Reset
0
0
0
0
0
0
0
0
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
55
Bit 2 is Reserved
When read, this bit reflects the default value
0
. When
WRITE
, this bit is ignored.
Bit 1 is the Transmit Data Register Empty
TDRE = 1
indicates that the Transmit Data Register (
TDR
)
is empty and that the next data byte to be transmitted can
be written into the
TDR
.
TDRE
is cleared to
0
after the byte
is written to
TDR
, until the ASCI transfers the byte from the
TDR
to the Transmit Shift Register (
TSR
), and then
TDRE
is again set to
1
.
TDRE
is set to
1
at Power-On Reset.
Bit 0 is the Transmit Interrupt Enable
TIE
should be set to a
1
to enable ASCI transmit interrupt
requests. An interrupt (
IRQ3
) is generated when
TDRE
(bit
1
of the
STAT
register) is a
1
.
TIE
is cleared to
0
at Power-
On Reset.
An anomaly exists that requires setting of the
RIE
bit to al-
low the generation of transmit interrupts. If
RIE
is not set,
transmit interrupts are not generated, even if
TIE
is set. See
Precautions
.
Baud Rate Generation Summary
The application can select between one of two baud rate
generators for the ASCI. If the BRG Mode bit in the ASEXT
register is set to a 0, the SS2,1,0 bits, the DR, bit and the
PR bit in CNTLB are used to select the baud rate. If the BRG
Mode bit is set to a 1, the ASTL and ASTH registers are
used to select the baud rate.
The following formulas are used to calculate the baud rate
from the two baud rate generators:
If
BRG
mode =
0
:
Where:
1.
SCLK
is the system clock.
2.
PS
=
1
or
0
and is bit
5
of
CNTLB
.
3.
DIV
=
1
,
2
,
4
,
8
,
16
,
32
or
64
as reflected by
SS20
in
CNTLB
.
4.
DIVIDE RATIO
=
16
or
64
, as defined by
DR
in
CNTLB
.
If
BRG
mode =
1
:
or
Where:
1.
SCLK
is the system clock.
2.
TC
is the 16-bit value programmed into
ASTL
and
ASTH
.
3.
DIVIDE RATIO
=
16
or
64
, as defined by
DR
in
CNTLB
.
4. Baud Rate is the desired baud rate.
Baud Rate =
SCLK
(10 + 20 x PS) x DIV x Divide Ratio
Baud Rate =
SCLK
(2 x (TC + 2) x Divide Ratio
TC =
SCLK
2
2 x Baud Rate x Divide Ratio
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
56
P R E L I M I N A R Y
DS007601-Z8X0499
ASCI STATUS REGISTER (STAT) (Continued)
Table 27. Baud Rate List (BRG Mode = 0)
Prescaler
Sampling
Rate
Baud Rate
General
Divide Ratio
Example Baud Rate (bps)
PS
Divide
Ratio
DR
Rate
SS2
SS1
SS0
Divide
Ratio
SCLK =
6.144
MHz
SCLK =
4.608
MHz
SCLK =
3.072
MHz
0
SCLK
10
0
16
0
0
0
1
SCLK 160
38400
19200
0
0
1
2
SCLK 320
19200
9600
0
1
0
4
SCLK 640
9600
4800
0
1
1
8
SCLK 1280
4800
2400
1
0
0
16
SCLK 2560
2400
1200
1
0
1
32
SCLK 5120
1200
600
1
1
0
64
SCLK 10240
600
300
1
64
0
0
0
1
SCLK 640
9600
4800
0
0
1
2
SCLK 1280
4800
2400
0
1
0
4
SCLK 2560
2400
1200
0
1
1
8
SCLK 5120
1200
600
1
0
0
16
SCLK 10240
600
300
1
0
1
32
SCLK 20480
300
150
1
1
0
64
SCLK 40960
150
75
1
SCLK
30
0
16
0
0
0
1
SCLK 480
4800
0
0
1
2
SCLK 960
2400
0
1
0
4
SCLK 1920
1200
0
1
1
8
SCLK 3840
600
1
0
0
16
SCLK 7680
300
1
0
1
32
SCLK 15360
150
1
1
0
64
SCLK 30720
75
1
64
0
0
0
1
SCLK 1920
2400
0
0
1
2
SCLK 3840
1200
0
1
0
4
SCLK 7680
600
0
1
1
8
SCLK 15360
300
1
0
0
16
SCLK 30720
150
1
0
1
32
SCLK 61440
75
1
1
0
64
SCLK 122880
37.5
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
57
LOW VOLTAGE PROTECTION
Figure 36. Typical Low Voltage Protection vs. Temperature
V
CC
(Volts)
3.60
3.20
3.00
2.80
2.60
2.40
-60
-40
-20
0
20
40
60
80
100
120
140
3.80
3.40
Temperature (C)
V (Typical)
LV
A
B
A
B
RUN/HALT Mode
STOP Mode
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
58
P R E L I M I N A R Y
DS007601-Z8X0499
MASK OPTIONS
Below is an example of the ROM mask bit option selection
for this product.
ROM Protect.
Selecting the
DISABLE ROM PROTECT
op-
tion
READ
s the software program that is in the program
memory using ZiLOG's internal factory test mode. How-
ever, none of the standard methods for reading or verifying
the code in the microcontroller uses an EPROM program-
mer. With this option disabled, ZiLOG is able to fully test
the ROM memory and provides its standard warranty for
the part. Selecting the
ENABLE ROM PROTECT
option ne-
gates the possibility of reading the code out of the part using
a tester, programmer, or any other standard method. ZiLOG
will be unable to test the ROM memory at any time prior
to customer delivery.
The
ROM PROTECT
option bit only affects the ability to
read the code and does not affect the operation of the part
in an application. If the
ROM PROTECT
option is disabled,
ZiLOG tests the part for ROM fallout and parts which fail
are not shipped to the customer. When the
ROM PROTECT
option is enabled, ZiLOG cannot perform these tests on the
ROM. When
ROM PROTECT
is enabled, except for the im-
proper transfer of the code by ZiLOG, all ROM memory
software errors shall be the responsibility of the Buyer and
ZiLOG shall have no obligation to repair or replace product
containing software errors. Selecting the
ENABLE ROM
PROTECT
option waives all warranties of ZiLOG, ex-
pressed or implied, on microcontrollers containing ROM
failures including, but not limited to, the implied warranty
of merchantability and fitness for a particular purpose.
RAM Protect.
Selecting the
DISABLE RAM PROTECT
op-
tion does not affect the RAM memory. RAM memory op-
erates as defined in this Product Specification for all address
locations. Selecting the
ENABLE RAM PROTECT
option,
allows protection (under software control) of a portion of
the RAM's address space from being read or written.
System Clock Source.
Selecting the
RC OSCILLATOR
ENABLE
option, configures the oscillator circuit on the mi-
crocontroller to work with an external RC circuit. Selecting
the
CRYSTAL/OTHER CLOCK SOURCE
option configures
the oscillator circuit to work with an external crystal, ce-
ramic resonator, or LC oscillator.
Oscillator Operational Mode.
Selecting the
NORMAL
HIGH FREQUENCY OPERATION ENABLED
option en-
ables the part to operate using a standard crystal or resona-
tor, but it does not operate using a 32-kHz crystal. Selecting
the
32-KHZ
OPERATION ENABLED
option enables the mi-
crocontroller to work with a 32-kHz crystal and an external
feedback resistor--these must be supplied between the
XTAL1
and
XTAL2
pins. (If
RC OSCILLATOR ENABLED
is selected in the
SYSTEM CLOCK SOURCE
option, this
option defaults to the
NORMAL HIGH FREQUENCY OP-
ERATION ENABLED
bit.)
WDT Mode.
Selecting the
WDT ENABLED BY SOFT-
WARE ONLY
option operates the Watch Dog Timer (WDT)
when turned on under software control. Selecting the
WDT
ENABLED AUTOMATICALLY AFTER RESET
option starts
the WDT automatically at
RESET
.There is no way to dis-
able or stop this mode, making it necessary in the code to
periodically clear the WDT to prevent it from resetting the
microcontroller. If the
WDT ENABLED AUTOMATICAL-
LY AFTER RESET
option and the
WDT DRIVEN BY SYS-
TEM CLOCK
option (if offered) are selected, the WDT nev-
Options
Option Selections
ROM Protect
Disable ROM Protect
Enable ROM Protect
RAM Protect
Disable RAM Protect
Enable RAM Protect
System Clock Source
RC Oscillator Enable
Crystal/Other Clock Source
Oscillator Operational Mode
Normal High-Frequency Operation
Enabled
32-kHz Crystal Operation Enabled
(Limits High-Frequency Operation)
WDT Mode
WDT Enabled by Software Only
WDT Enabled Automatically After
RESET
Auto Latch Mode
Disable Auto Latches
Enable Auto Latches
Port 0 Pull-Ups
Disable Pull-Ups
Enable Pull-Ups
Port 1 Pull-Ups
Disable Pull-Ups
Enable Pull-Ups
Port 2 Pull-Ups
Disable Pull-Ups
Enable Pull-Ups
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
59
er operates in
STOP
mode, and cannot be enabled, by any
means, to operate in
STOP
mode.
Auto Latch Mode.
Selecting the
DISABLE AUTOLATCH-
ES
option disables the autolatches on the Port pins. These
pins will float rather than be pulled to a valid CMOS level
when they are inputs and not connected to an external sig-
nal. Selecting the
ENABLE AUTOLATCHES
option enables
the autolatches on the Port pins and pulls the pins to a valid
CMOS level when they are not connected to an external sig-
nal.
Port 0 Pull-Ups.
Selecting
DISABLE PULL-UPS
disables
the input pull-up circuitry on all Port 0 pins. Selecting
EN-
ABLE PULL-UPS
enables the input pull-up circuitry on all
Port 0 pins. This option bit does not affect any of the other
port pins on the part.
Port 1 Pull-Ups.
Selecting
DISABLE PULL-UPS
disables
the input pull-up circuitry on all Port 1 pins. Selecting
EN-
ABLE PULL-UPS
enables the input pull-up circuitry on all
Port 1 pins. This option bit does not affect any of the other
port pins on the part.
Port 2 Pull-Ups.
Selecting
DISABLE PULL-UPS
disables
the input pull-up circuitry on all Port 2 pins. Selecting
EN-
ABLE PULL-UPS
enables the input pull-up circuitry on all
Port 2 pins. This option bit does not affect any of the other
port pins on the part.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
60
P R E L I M I N A R Y
DS007601-Z8X0499
EXPANDED REGISTER FILE CONTROL REGISTERS
Figure 37. Stop-Mode Recovery Register
(WRITE ONLY, except Bit D7, which is READ ONLY)
Figure 38. Stop-Mode Recovery Register2
D7
D6
D5
D4
D3
D2
D1
D0
SMR (FH) 0B
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
*
Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
D7
D6
D5
D4
D3
D2
D1
D0
SMR2 (0F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Figure 39. Watch-Dog Timer Mode Register
(WRITE ONLY)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP INT RC OSC System Clock
00 3.5 ms 128 SCLK
01 10 ms 256 SCLK
10 14 ms 512 SCLK
11 56 ms 2048 SCLK
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
*
Default setting after RESET
*
*
*
*
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
61
Z8 CONTROL REGISTERS
Figure 40. Port Configuration Register (PCON)
(WRITE ONLY)
Figure 41. Timer Mode Register
(F1
H
: READ/WRITE)
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
D7
D6
D5
D4
D3
D2
D1
D0
PCON (FH) 00H
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
*Default Setting After Reset
Must be set to one for devices
in 28-pin packages
0 Port 1 Open Drain
1 Port 1 Push-pull Active*
0 Port 1 Low EMI
1
Port 1
Standard*
D7
D6
D5
D4
D3
D2
D1
D0
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T0
0 No Function
1 Load T1
0 Disable T1 Count
1 Enable T1 Count
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
R241 TMR
Figure 42. Counter/Timer 1 Register
(F2
H
: READ/WRITE)
Figure 43. Prescaler 1 Register
(F3
H
: WRITE ONLY)
Figure 44. Counter/Timer 0 Register
(F4
H
: READ/WRITE)
D7
D6
D5
D4
D3
D2
D1
D0
T Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T Current Value
(When Read)
1
1
R242 T1
D7
D6
D5
D4
D3
D2
D1
D0
Count Mode
0 T1 Single Pass
1 T1 Modulo N
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R243 PRE1
D7
D6
D5
D4
D3
D2
D1
D0
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
R244 T0
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
62
P R E L I M I N A R Y
DS007601-Z8X0499
Z8 CONTROL REGISTERS (Continued)
Figure 45. Prescaler 0 Register
(F5
H
: WRITE ONLY)
Figure 46. Port 2 Mode Register
(F6
H
: WRITE ONLY)
Figure 47. Port 3 Mode Register
(F7
H
: WRITE ONLY)
0 T0 Single Pass
1 T0 Modulo N
D7
D6
D5
D4
D3
D2
D1
D0
Count Mode
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R245 PRE0
D7
D6
D5
D4
D3
D2
D1
D0
P20 - P27 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M
0 Port 2 Pull-Ups Open Drain
1 Port 2 Push-Pull Active
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0
P35 = RDY0/DAV0
00 P33 = Input
P34 = Output
01 P33 = Input
10 P34 = DM
P34 = RDY1/DAV1
0 P31 = Input (T
IN
)
P36 = Output (T
OUT
)
1 P31 = DAV2/RDY2
P36 = RDY2/DAV2
0 P30 = Input
Reserved (must be 0)
11 P33 = DAV0/RDY0
P37 = Output
Figure 48. Port 0 and 1 Mode Register
(F8
H
: WRITE ONLY)
Figure 49. Interrupt Priority Register
(F9
H
: WRITE ONLY)
D7
D6
D5
D4
D3
D2
D1
D0
R248 P01M
P00P03 Mode
00 Output
01 Input
1X A11A8
Stack Selection
0 External
1 Internal
P10 - P17 Mode
00 Byte Output
01 Byte Input
10 AD7 - AD0
11 High-Impedance AD7AD0,
AS, DS, R/W, A11A8,
A15A12, If Selected
P04P07 Mode
00 Output
01 Input
1X A15A12
External Memory Timing
0 Normal
1 Extended
For 28 pin device, the user must set:
D2=1
D3=0
D4=0
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0)
R249 IPR
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
63
Figure 50. Interrupt Request Register
(FA
H
: READ/WRITE)
Figure 51. Interrupt Mask Register
(FB
H
: READ/WRITE)
Figure 52. Flag Register
(FC
H
: READ/WRITE)
D7
D6
D5
D4
D3
D2
D1
D0
R250 IRQ
Inter Edge
P31
P32
= 00
P31
P32
= 01
P31
P32
= 10
P31
P32
= 11
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input
IRQ4 = T0
IRQ5 = T1
D7
D6
D5
D4
D3
D2
D1
D0
1 Enables RAM Protect *
1 Enables IRQ0-IRQ5
(D0 = IRQ0)
1 Enables Interrupts
R251 IMR
* This option must be selected when ROM code is
submitted for ROM Masking, otherwise this control bit
is disabled permanently.
D7
D6
D5
D4
D3
D2
D1
D0
R252 FLAGS
User Flag F1 *
User Flag F2 *
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
* Not affected by reset
Figure 53. Register Pointer
(FD
H
: READ/WRITE)
Figure 54. Stack Pointer High
(FE
H
: READ/WRITE)
Figure 55. Stack Pointer Low
(FF
H
: READ/WRITE)
D7
D6
D5
D4
D3
D2
D1
D0
R253 RP
Expanded Register File
Working Register Pointer
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Upper
Byte (SP8 - SP15)
R254 SPH
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Lower
Byte (SP0 - SP7)
R255 SPL
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
64
P R E L I M I N A R Y
DS007601-Z8X0499
PACKAGE INFORMATION
Figure 56. 28-Pin DIP Package Diagram
Figure 57. 28-Pin SOIC Package Diagram
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
65
Figure 58. 28-Pin PLCC Package Diagram
Figure 59. 40-Pin DIP Package Diagram
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
66
P R E L I M I N A R Y
DS007601-Z8X0499
Figure 60. 44-Pin PLCC Package Diagram
Figure 61. 44-Pin QFP Package Diagram
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
67
ORDERING INFORMATION
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
Z86C34
Standard Temperature
Extended Temperature
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C3416PSC
Z86C3416SSC
Z86C3416VSC
Z86C3416PEC
Z86C3416SEC
Z86C3416VEC
Z86C35
Standard Temperature
Extended Temperature
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C3516PSC
Z86C3516SSC
Z86C3516VSC
Z86C3516PEC
Z86C3516SEC
Z86C3516VEC
Z86C36
Standard Temperature
Extended Temperature
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C3616PSC
Z86C3616SSC
Z86C3616VSC
Z86C3616PEC
Z86C3616SEC
Z86C3616VEC
Z86C44
Standard Temperature
Extended Temperature
40-Pin DIP
44-Pin PLCC
44-Pin QFP
40-Pin DIP
44-Pin PLCC
44-Pin QFP
Z86C4416PSC
Z86C4416VSC
Z86C4416FSC
Z86C4416PEC
Z86C4416VEC
Z86C4416FEC
Z86C45
Standard Temperature
Extended Temperature
40-Pin DIP
44-Pin PLCC
44-Pin QFP
40-Pin DIP
44-Pin PLCC
44-Pin QFP
Z86C4516PSC
Z86C4516VSC
Z86C4516FSC
Z86C4516PEC
Z86C4516VEC
Z86C4516FEC
Z86C46
Standard Temperature
Extended Temperature
40-Pin DIP
44-Pin PLCC
44-Pin QFP
40-Pin DIP
44-Pin PLCC
44-Pin QFP
Z86C4616PSC
Z86C4616VSC
Z86C4616FSC
Z86C4616PEC
Z86C4616VEC
Z86C4616FEC
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
68
P R E L I M I N A R Y
DS007601-Z8X0499
PRECAUTIONS
(Continued)
PRECAUTIONS
1. Enabling the transmit interrupt (bit
0
in the ASCI
STAT register) does not make the device ready for
transmitter-related interrupts. The receiver interrupt
(bit
3
in the
ASCI STAT
register) must also be enabled.
Workaround
: For transmit interrupts to be generated,
the
RIE
bit must also be set. When
IRQ3
is generated,
the software should check the
STAT
register for
details on the interrupt source.
2. When using the device in full-duplex mode under in-
terrupts (both transmit and receive interrupts enabled),
a small window exists where a transmit or receive in-
terrupt may be lost. This situation occurs when an in-
terrupt is generated by one side (either the transmitter
or receiver) and, before the interrupt is serviced, an-
other interrupt is generated by the other side. The sec-
ond interrupt may be lost.
Workaround
: The only workaround is not to use
transmitter interrupts when using the ASCI in full-
duplex mode. Use the transmitter in polled mode and
the receiver in interrupt mode for full duplex
operation. In half-duplex operation, this anomaly does
not create a problem.
Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8 MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
69
CODES
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
Example:
The Z86C36 is a 16-MHz PLCC, 0C to 70C, with Plastic
Standard Flow.
Pre-Characterization Product
The product represented by this document is newly introduced
and ZiLOG has not completed the full characterization of the
product. The document states what ZiLOG knows about this
product at this time, but additional features or nonconformance
with some aspects of the document may be found, either by
ZiLOG or its customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
1999 by ZiLOG, Inc. All rights reserved. Information in this
publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be
superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY
FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES
NOT ASSUME LIABILITY FOR INTELLECTUAL
PROPERTY INFRINGEMENT RELATED IN ANY
MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE.
Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of
life support systems is not authorized. No licenses are conveyed,
implicitly or otherwise, by this document under any intellectual
property rights.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX (408) 558-8300
Internet:
http://www.zilog.com
Preferred Package
P = Plastic DIP
V = Plastic Chip Carrier
Longer Lead Time
F = Plastic Quad Flat Pack
S = Small Outline
Integrated Chip
Preferred Temperature
S = 0C to +70C
Longer Lead Time
E = 40C to +105C
Speed
16 = 16 MHz
Environmental
C = Plastic Standard
Z
ZiLOG Prefix
86C36
Product Number
16
Speed
P
Package
S
Temperature
C
Environmental Flow
Z86C34/C35/C36/C44/C45/C46
CMOS Z8 MCUs with ASCI UART
ZiLOG
70
P R E L I M I N A R Y
DS007601-Z8X0499