ChipFind - документация

Электронный компонент: Z86E74

Скачать:  PDF   ZIP

Document Outline

1
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
FEATURES
ROM
RAM*
One-Time
Speed
Part
(Kbyte)
(Kbyte) Programmable
(MHz)
Z86E73
32
1004
Yes
8
Z86L73
32
492
No
8
Z86E74
32
1004
Yes
8
Z86L74
32
1004
No
8
* General-Purpose
s
40-Pin DIP, 44-Pin PLCC/QFP Packages (E73/L73)
64-Pin DIP, 68-Pin PLCC Packages (E74/L74)
s
2.0V to 3.9V Operating Range (L73/L74)
4.5V to 5.5V Operating Range (E73/E74)
s
Low-Power Consumption
(Typical: 40 mw for L73/L74)
(Typical: 60 mw for E73/E74)
s
0
C to +70
C Temperature Range
s
Expanded Register Files (ERF)
s
31 Input/Output Lines (E73/L73)
51 Input/Output Lines (E74/L74*)
*Note: With Auto Latch on Port 4, 5 and 6.
s
Five Prioritized Interrupts with Programmable Polarity
s
Two Comparators
s
8-Bit Counter/Timer with Two Capture Registers and
16-Bit Counter/Timer with One Capture Register
s
Watch-Dog Timer (WDT)/Power-On Reset (POR)
s
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
s
Low-Voltage Detection and Protection
s
32-KHz Mask Option to Disable Internal Feedback
Resistor (L73/L74)
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
CP95LVO0801
Z86E73/E74 32K OTP
Z86L73/L74 32K ROM
I
NFRARED
R
EMOTE
C
ONTROLLERS
GENERAL DESCRIPTION
The Z86E73/L73/E74/L74 are ROM-based members of
Zilog's Z8
single-chip microcontroller family of infrared
(IR) consumer controller processors featuring fast and
flexible code execution. The Z86E73/E74 devices offer a
one-time programmable (OTP) option.
For applications demanding powerful I/O capabilities, the
Z86E73/L73's dedicated input and output lines are grouped
into four ports, and into seven ports for the Z86E74/L74.
They are configurable under software control to provide
timing, status signals, or parallel I/O.
Four address spaces, the Program Memory, Register File,
Data Memory, and Expanded Register File (ERF) support
a wide range of memory configurations. Through the ERF
the designer has access to three additional control registers
that provide extra peripheral devices, I/O ports, and register
addresses.
Two on-chip counter/timers, with a large number of
selectable modes, offload the system of administering
real-time tasks such as counting/timing and I/O
datacommunications.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
2
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
GENERAL DESCRIPTION
(Continued)
Functional Block Diagram
Port 0
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P31
P32
P33
/AS
/DS
R/W
/RESET
Port 3
Port 1
Port 2
Register File
512 or 1K x 8-bit
ROM
16K/32K x 8
Z8 Core
Register Bus
Internal
Address Bus
Internal Data Bus
Extended
Register
File
Extended
Register Bus
Counter/Timer 8
8-Bit
Counter/Timer 16
16-Bit
Machine
Timing
&
Instruction
Control
Power
XTAL
VDD
VSS
P34
P35
P36
P37
4
4
8
Port 4
Port 5
Port 6
8
8
4
I/O Bit
Programmable
Z86E74/L74
version only
3
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
PIN DESCRIPTION
1
2
9
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
/DS
P24
P12
P23
P22
P21
P20
P03
P13
R//W
XTAL2
P27
P04
P05
P06
P14
31
30
29
28
27
14
10
11
12
13
XTAL1
VDD
P16
P17
P25
VSS
P02
P11
P10
P01
Z86E73/L73
DIP
15
26
25
24
23
22
21
20
16
17
18
19
P15
P07
P26
P31
P34
/AS
P33
P32
P36
P00
Pref1
P37
P35
/RESET
P56
R/W
P25
P26
VDD
P40
P41
P42
P43
P44
P45
P16
R//RL
P54
P53
/DS
P51
P50
P24
P23
P22
P21
P20
P03
P13
P12
VSS
VSS
P52
P57
P02
P46
P27
P04
P05
P06
P14
P15
P07
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Z86E74/L74
DIP
P17
XTAL2
XTAL1
P31
P47
P11
P10
P01
21
22
23
24
43
42
41
40
P34
P60
P61
/AS
P63
P55
P00
PREF1
P36
P37
P35
/RESET
VSS
P62
P32
P33
25
26
27
28
29
30
31
32
39
38
37
36
35
34
33
64
Z86E73 (Standard Mode)
Z86L73 40-Pin DIP
Pin Assignments
Z86E74 (Standard Mode)
Z86L74 64-Pin DIP
Pin Assignments
4
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
Z86E73 (Standard Mode)
Z86L73 44-Pin QFP
Pin Assignments
PIN DESCRIPTION
Z86E73 (Standard Mode)
Z86L73 44-Pin PLCC
Pin Assignments
P20
P03
P13
P12
VSS
VSS
P02
P1
1
P10
P01
P00
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
Pref1
P36
P37
P35
/RESET
VSS
/AS
P34
P33
P32
P31
P21
P22
P23
P24
/DS
R//RL
R//W
P25
P26
P27
P04
XT
AL1
XT
AL2
7
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
39
Z86E73/L73
PLCC
6
5
4
3
2
1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
34
35
36
37
38
39
40
41
42
43
44
21
20
19
18
17
16
15
14
13
12
22
33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6
7 8 9 10 11
Z86E73/L73
QFP
P20
P03
P13
P12
VSS
VSS
P02
P1
1
P10
P01
P00
P21
P22
P23
P24
/DS
R//RL
R//W
P25
P26
P27
P04
Pref1
P36
P37
P35
/RESET
VSS
/AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VDD
VDD
P16
P17
XT
AL1
XT
AL2
5
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
Z86E74/L74
PLCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
7
8
9
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PREF1
P36
P37
P35
/RESET
VSS
P62
P55
N/C
P63
/AS
P61
P60
P34
P33
P32
P31
P21
P22
P23
P24
P50
P51
/DS
P53
P54
R//RL
P56
R//W
N/C
P25
P26
P27
P04
P20
P03
P13
P12
VSS
VSS
N/C
N/C
P52
P57
P02
P46
P47
P1
1
P10
P01
P00
P05
P06
P14
P15
P07
VDD
VDD
P40
P41
P42
P43
P44
P45
P16
P17
XT
AL2
XT
AL1
Z86E74 (Standard Mode)
Z86L74 68-Pin PLCC Pin Assignments
PIN DESCRIPTION
(Continued)
6
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended
period may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
Max
Units
V
CC
Supply Voltage (*)
0.3
+7.0
V
T
STG
Storage Temp.
65
+150
C
T
A
Oper. Ambient Temp.
C
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load).
From Output
Under Test
150 pF
I
STANDARD TEST CONDITIONS
Test Load Diagram
CAPACITANCE
T
A
= 25
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Max
Input capacitance
12 pF
Output capacitance
12 pF
I/O capacitance
12 pF
Notes:
* Voltage on all pins with respect to GND.
See Ordering Information.
7
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
DC CHARACTERISTICS (Z86E73/E74)
T
A
= 0
C to +70
C
Typ @
Sym
Parameter
V
CC
Min
Max
25
C
Units
Conditions
Notes [3]
Max Input Voltage
4.0V
7
V
I
IN
250
A
5.5V
7
V
I
IN
250
A
V
CH
Clock Input
4.0V
0.9 V
CC
V
CC
+ 0.3
V
Driven by External
High Voltage
Clock Generator
5.5V
0.9 V
CC
V
CC
+ 0.3
V
Driven by External
Clock Generator
V
CL
Clock Input
40V
V
SS
0.3
0.2 V
CC
V
Driven by External
Low Voltage
Clock Generator
5.5V
V
SS
0.3
0.2 V
CC
V
Driven by External
Clock Generator
V
IH
Input High Voltage
4.0V
0.7 V
CC
V
CC
+ 0.3
1.3
V
5.5V
0.7 V
CC
V
CC
+ 0.3
2.5
V
V
IL
Input Low Voltage
4.0V
V
SS
0.3
0.2 V
CC
0.5
V
5.5V
V
SS
0.3
0.2 V
CC
0.9
V
V
OH1
Output High Voltage
4.0V
V
CC
0.4
1.7
V
I
OH
= 0.5 mA
5.5V
V
CC
0.4
3.7
V
I
OH
= 0.5 mA
V
OH2
Output High Voltage
4.0V
0.7
V
I
OH
= 7 mA
[10]
(P36, P37)
5.5V
0.7
V
I
OH
,= 7 mA
[10]
V
OL1
Output Low Voltage
4.0V
0.4
0.2
V
I
OL
= 1.0 mA
5.5V
0.4
0.1
V
I
OL
= 4.0 mA
V
OL2
Output Low Voltage
4.0V
0.8
0.3
V
I
OL
= 2.0 mA
3 Pin Max
5.5V
0.8
0.5
V
I
OL
= 8.0 mA
3 Pin Max
V
OL2
Output Low Voltage
4.0V
0.8
0.3
V
I
OL
= 10 mA
[9]
(P20-P22, P36,
P00, P01, P07)
5.5V
0.8
0.5
V
I
OL
= 10 mA
[9]
2 O/P only
V
RH
Reset Input
4.0V
0.8 V
CC
V
CC
1.5
V
High Voltage
5.5V
0.8 V
CC
V
CC
3.0
V
V
Rl
Reset Input
4.0V
V
SS
0.3
0.2 V
CC
0.5
Low Voltage
5.5V
V
SS
0.3
0.2 V
CC
0.9
V
OFFSET
Comparator Input
4.0V
25
10
mV
Offset Voltage
5.5V
25
10
mV
I
IL
Input Leakage
4.0V
1
1
< 1
A
V
IN
= OV, V
CC
5.5V
1
1
< 1
A
V
IN
= OV, V
CC
I
OL
Output Leakage
4.0V
1
1
< 1
A
V
IN
= OV, V
CC
5.5V
1
1
< 1
A
V
IN
= OV, V
CC
I
IR
Reset Input Current
4.0V
45
20
A
5.5V
55
30
A
I
CC
Supply Current
4.0V
10
4
mA
@ 8.0 MHz
[4, 5]
5.5V
15
10
mA
@ 8.0 MHz
[4, 5]
4.0V
100
10
A
@ 32 kHz
[4, 5,11]
5.5V
300
10
A
@ 32 kHz
[4, 5,11]
8
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
Notes:
[1]
I
CC1
Typ
Max
Unit
Frequency
Crystal/Resonator
3.0 mA
5
mA
8.0 MHz
External Clock Drive
0.3 mA
5
mA
8.0 MHz
[2]
GND = 0V.
[3]
4.0V to 5.5V.
[4]
All outputs unloaded, I/O pins floating, inputs at rail.
[5]
CL1 = CL2 = 100 pF.
[6]
Same as note [4] except inputs at V
CC
.
[7]
The V
LV
increases as the temperature decreases.
[8]
Oscillator stopped.
[9]
Two outputs at a time, independent to other outputs.
[10] One at a time.
[11] 32 kHz clock driver input.
DC CHARACTERISTICS (Z86E73/E74)
(Continued)
T
A
= 0
C to +70
C
Typ @
Sym
Parameter
V
CC
Min
Max
25
C
Units
Conditions
Notes [3]
I
CC1
Standby Current
4.0V
3
1
mA
HALT Mode
[4,5]
V
IN
= OV, V
CC
@ 8.0 MHz
5.5V
5
4
mA
HALT Mode
[4,5]
V
IN
= OV, V
CC
@ 8.0 MHz
4.0V
2
0.8
mA
Clock Divide-by-16
[4,5]
@ 8.0 MHz
5.5V
4
2.5
mA
Clock Divide-by-16
[4,5]
@ 8.0 MHz
I
CC2
Standby Current
4.0V
8
2
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is not Running
5.5V
10
3
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is not Running
4.0V
500
310
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is Running
5.5V
800
600
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is Running
T
POR
Power-On Reset
4.0V
15
75
13
ms
5.5V
5
20
7
ms
V
LV
V
CC
Low Voltage Protection
3.3
2.75
V
8 MHz max
[7]
Ext. CLK Freq.
9
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
T
A
= 0
C to +70
C
Typ @
Sym
Parameter
V
CC
Min
Max
25
C
Units
Conditions
Notes [3]
Max Input Voltage
2.0V
7
V
I
IN
250
A
3.9V
7
V
I
IN
250
A
V
CH
Clock Input
2.0V
0.9 V
CC
V
CC
+ 0.3
V
Driven by External
High Voltage
Clock Generator
3.9V
0.9 V
CC
V
CC
+ 0.3
V
Driven by External
Clock Generator
V
CL
Clock Input
2.0V
V
SS
0.3
0.2 V
CC
V
Driven by External
Low Voltage
Clock Generator
3.9V
V
SS
0.3
0.2 V
CC
V
Driven by External
Clock Generator
V
IH
Input High Voltage
2.0V
0.7 V
CC
V
CC
+ 0.3
1.3
V
3.9V
0.7 V
CC
V
CC
+ 0.3
2.5
V
V
IL
Input Low Voltage
2.0V
V
SS
0.3
0.2 V
CC
0.5
V
3.9V
V
SS
0.3
0.2 V
CC
0.9
V
V
OH1
Output High Voltage
2.0V
V
CC
0.4
1.7
V
I
OH
= 0.5 mA
3.9V
V
CC
0.4
3.7
V
I
OH
= 0.5 mA
V
OH2
Output High Voltage
2.0V
0.7
V
I
OH
= 7 mA
[10]
(P36, P37)
3.9V
0.7
V
I
OH
,= 7 mA
[10]
V
OL1
Output Low Voltage
2.0V
0.4
0.2
V
I
OL
= 1.0 mA
3.9V
0.4
0.1
V
I
OL
= 4.0 mA
V
OL2
Output Low Voltage
2.0V
0.8
0.3
V
I
OL
= 2.0 mA
3 Pin Max
3.9V
0.8
0.5
V
I
OL
= 8.0 mA
3 Pin Max
V
OL2
Output Low Voltage
2.0V
0.8
0.3
V
I
OL
= 10 mA
[9]
(P20-P22, P36,
P00, P01, P07)
3.9V
0.8
0.5
V
I
OL
= 10 mA
[9]
2 O/P only
V
RH
Reset Input
2.0V
0.8 V
CC
V
CC
1.5
V
High Voltage
3.9V
0.8 V
CC
V
CC
3.0
V
V
Rl
Reset Input
2.0V
V
SS
0.3
0.2 V
CC
0.5
Low Voltage
3.9V
V
SS
0.3
0.2 V
CC
0.9
V
OFFSET
Comparator Input
2.0V
25
10
mV
Offset Voltage
3.9V
25
10
mV
I
IL
Input Leakage
2.0V
1
1
< 1
A
V
IN
= OV, V
CC
3.9V
1
1
< 1
A
V
IN
= OV, V
CC
I
OL
Output Leakage
2.0V
1
1
< 1
A
V
IN
= OV, V
CC
3.9V
1
1
< 1
A
V
IN
= OV, V
CC
I
IR
Reset Input Current
2.0V
45
20
A
3.9V
55
30
A
I
CC
Supply Current
2.0V
10
4
mA
@ 8.0 MHz
[4, 5]
3.9V
15
10
mA
@ 8.0 MHz
[4, 5]
2.0V
100
10
A
@ 32 kHz
[4, 5,11]
3.9V
300
10
A
@ 32 kHz
[4, 5,11]
DC CHARACTERISTICS (Z86L73/L74)
10
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
DC CHARACTERISTICS (Z86L73/L74)
(Continued)
T
A
= 0
C to +70
C
Typ @
Sym
Parameter
V
CC
Min
Max
25
C
Units
Conditions
Notes [3]
I
CC1
Standby Current
2.0V
3
1
mA
HALT Mode
[4,5]
V
IN
= OV, V
CC
@ 8.0 MHz
3.9V
5
4
mA
HALT Mode
[4,5]
V
IN
= OV, V
CC
@ 8.0 MHz
2.0V
2
0.8
mA
Clock Divide-by-16
[4,5]
@ 8.0 MHz
3.9V
4
2.5
mA
Clock Divide-by-16
[4,5]
@ 8.0 MHz
I
CC2
Standby Current
2.0V
8
2
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is not Running
3.9V
10
3
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is not Running
2.0V
500
310
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is Running
3.9V
800
600
A
STOP Mode
[6,8]
V
IN
= OV, V
CC
WDT is Running
T
POR
Power-On Reset
2.0V
15
75
13
ms
3.9V
5
20
7
ms
V
LV
V
CC
Low Voltage Protection
2.15
1.7
V
8 MHz max
[7]
Ext. CLK Freq.
Notes:
[1]
I
CC1
Typ
Max
Unit
Frequency
Crystal/Resonator
3.0 mA
5
mA
8.0 MHz
External Clock Drive
0.3 mA
5
mA
8.0 MHz
[2]
GND = 0V.
[3]
2.0V to 3.9V.
[4]
All outputs unloaded, I/O pins floating, inputs at rail.
[5]
CL1 = CL2 = 100 pF.
[6]
Same as note [4] except inputs at V
CC
.
[7]
The V
LV
increases as the temperature decreases.
[8]
Oscillator stopped.
[9]
Two outputs at a time, independent to other outputs.
[10] One at a time.
[11] 32 kHz clock driver input.
11
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
R//W
9
12
8
3
16
13
4
5
8
11
6
17
10
15
7
14
2
1
Port 0, /DM
Port 1
/AS
/DS
(Read)
Port 1
/DS
(Write)
A7 - A0
D7 - D0 IN
D7 - D0 OUT
A7 - A0
19
20
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
External I/O or Memory Read/Write Timing
12
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS (Z86E73/E74)
External I/O or Memory Read and Write Timing Table
T
A
= 0
C to +70
C
V
CC
8.0 MHz
No.
Symbol
Parameter
Note [3]
Min
Max
Units
Notes
1
TdA(AS)
Address Valid to
4.0V
55
ns
[2]
/AS Rising Delay
5.5V
55
ns
2
TdAS(A)
/AS Rising to Address
2.0V
70
ns
[2]
Float Delay
5.5V
70
ns
3
TdAS(DR)
/AS Rising to Read
4.0V
400
ns
[1, 2]
Data Required Valid
5.5V
400
ns
4
TwAS
/AS Low Width
4.0V
80
ns
[2]
5.5V
80
ns
5
Td
Address Float to
4.0V
0
ns
/DS Falling
5.5V
0
ns
6
TwDSR
/DS (Read) Low Width
4.0V
300
ns
[1, 2]
5.5V
300
ns
7
TwDSW
/DS (Write) Low Width
4.0V
165
ns
[1, 2]
5.5V
165
ns
8
TdDSR(DR)
/DS Falling to Read
4.0V
260
ns
[1, 2]
Data Required Valid
5.5V
260
ns
9
ThDR(DS)
Read Data to
4.0V
0
ns
[2]
/DS Rising Hold Time
5.5V
0
ns
10
TdDS(A)
/DS Rising to Address
4.0V
85
ns
[2]
Active Delay
5.5V
95
ns
11
TdDS(AS)
/DS Rising to /AS
4.0V
60
ns
[2]
Falling Delay
5.5V
70
ns
12
TdR/W(AS)
R//W Valid to /AS
4.0V
70
ns
[2]
Rising Delay
5.5V
70
ns
13
TdDS(R/W)
/DS Rising to
4.0V
70
ns
[2]
R//W Not Valid
5.5V
70
ns
14
TdDW(DSW)
Write Data Valid to /DS
4.0V
80
ns
[2]
Falling (Write) Delay
5.5V
80
ns
15
TdDS(DW)
/DS Rising to Write
4.0V
70
ns
[2]
Data Not Valid Delay
5.5V
80
ns
16
TdA(DR)
Address Valid to Read
4.0V
475
ns
[1, 2]
Data Required Valid
5.5V
475
ns
17
TdAS(DS)
/AS Rising to
4.0V
100
ns
[2]
/DS Falling Delay
5.5V
100
ns
18
TdDM(AS)
/DM Valid to /AS
4.0V
55
ns
[2]
Falling Delay
5.5V
55
ns
19
TdDS(DM)
/DS Rise to
4.0V
70
ns
/DM Valid Delay
5.5V
70
ns
20
ThDS(A)
/DS Rise to Address
4.0V
70
ns
Valid Hold Time
5.5V
70
ns
Notes:
[1]
When using extended memory timing add 2 TpC.
[2]
Timing numbers given are for minimum TpC.
[3]
4.0V to 5.5V.
Standard Test Load.
All timing references use 0.9 V
CC
for a logic 1 and 0.1 V
CC
for a logic 0.
13
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS (Z86L73/L74)
External I/O or Memory Read and Write Timing Table
T
A
= 0
C to +70
C
V
CC
8.0 MHz
No.
Symbol
Parameter
Note [3]
Min
Max
Units
Notes
1
TdA(AS)
Address Valid to
2.0V
55
ns
[2]
/AS Rising Delay
3.9V
55
ns
2
TdAS(A)
/AS Rising to Address
2.0V
70
ns
[2]
Float Delay
3.9V
70
ns
3
TdAS(DR)
/AS Rising to Read
2.0V
400
ns
[1, 2]
Data Required Valid
3.9V
400
ns
4
TwAS
/AS Low Width
2.0V
80
ns
[2]
3.9V
80
ns
5
Td
Address Float to
2.0V
0
ns
/DS Falling
3.9V
0
ns
6
TwDSR
/DS (Read) Low Width
2.0V
300
ns
[1, 2]
3.9V
300
ns
7
TwDSW
/DS (Write) Low Width
2.0V
165
ns
[1, 2]
3.9V
165
ns
8
TdDSR(DR)
/DS Falling to Read
2.0V
260
ns
[1, 2]
Data Required Valid
3.9V
260
ns
9
ThDR(DS)
Read Data to
2.0V
0
ns
[2]
/DS Rising Hold Time
3.9V
0
ns
10
TdDS(A)
/DS Rising to Address
2.0V
85
ns
[2]
Active Delay
3.9V
95
ns
11
TdDS(AS)
/DS Rising to /AS
2.0V
60
ns
[2]
Falling Delay
3.9V
70
ns
12
TdR/W(AS)
R//W Valid to /AS
2.0V
70
ns
[2]
Rising Delay
3.9V
70
ns
13
TdDS(R/W)
/DS Rising to
2.0V
70
ns
[2]
R//W Not Valid
3.9V
70
ns
14
TdDW(DSW)
Write Data Valid to /DS
2.0V
80
ns
[2]
Falling (Write) Delay
3.9V
80
ns
15
TdDS(DW)
/DS Rising to Write
2.0V
70
ns
[2]
Data Not Valid Delay
3.9V
80
ns
16
TdA(DR)
Address Valid to Read
2.0V
475
ns
[1, 2]
Data Required Valid
3.9V
475
ns
17
TdAS(DS)
/AS Rising to
2.0V
100
ns
[2]
/DS Falling Delay
3.9V
100
ns
18
TdDM(AS)
/DM Valid to /AS
2.0V
55
ns
[2]
Falling Delay
3.9V
55
ns
19
TdDS(DM)
/DS Rise to
2.0V
70
ns
/DM Valid Delay
3.9V
70
ns
20
ThDS(A)
/DS Rise to Address
2.0V
70
ns
Valid Hold Time
3.9V
70
ns
Notes:
[1]
When using extended memory timing add 2 TpC.
[2]
Timing numbers given are for minimum TpC.
[3]
2.0V to 3.9V.
Standard Test Load.
All timing references use 0.9 V
CC
for a logic 1 and 0.1 V
CC
for a logic 0.
14
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS
Additional Timing Diagram
Clock
1
3
4
8
2
2
3
T
IRQ
IN
N
6
5
7
7
11
Clock
Setup
10
9
Stop
Mode
Recovery
Source
Additional Timing
15
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS (Z86E73/E74)
Additional Timing Table
T
A
= 0
C to +70
C
V
CC
8.0 MHz
No
Symbol
Parameter
Note [3]
Min
Max
Units
Notes
1
TpC
Input Clock Period
4.0V
121
DC
ns
[1]
5.5V
121
DC
ns
[1]
2
TrC,TfC
Clock Input Rise
4.0V
25
ns
[1]
and Fall Times
5.5V
25
ns
[1]
3
TwC
Input Clock Width
4.0V
37
ns
[1]
5.5V
37
ns
[1]
4
TwTinL
Timer Input
4.0V
100
ns
[1]
Low Width
5.5V
70
ns
[1]
5
TwTinH
Timer Input
4.0V
3TpC
[1]
High Width
5.5V
3TpC
[1]
6
TpTin
Timer Input Period
4.0V
8TpC
[1]
5.5V
8TpC
[1]
7
TrTin,TfTin
Timer Input Rise
4.0V
100
ns
[1]
and Fall Timers
5.5V
100
ns
[1]
8A
TwIL
Interrupt Request
4.0V
100
ns
[1, 2]
Low Time
5.5V
70
ns
[1, 2]
8B
TwIL
Int. Request
4.0V
3TpC
[1, 3]
Low Time
5.5V
3TpC
[1, 3]
9
TwIH
Interrupt Request
4.0V
3TpC
[1, 2]
Input High Time
5.5V
3TpC
[1, 2]
10
Twsm
Stop-Mode Recovery
4.0V
12
ns
[8]
Width Spec
5.5V
12
ns
[8]
4.0V
5TpC
[7]
5.5V
5TpC
[7]
11
Tost
Oscillator
4.0V
5TpC
[4]
Start-up Time
5.5V
5TpC
[4]
12
Twdt
Watch-Dog Timer
(5 ms)
4.0V
12
75
ms
D0 = 0 [5]
Delay Time
5.5V
5
20
ms
D1 = 0 [5]
(10 ms)
4.0V
25
150
ms
D0 = 1 [5]
5.5V
10
40
ms
D1 = 0 [5]
(20 ms)
4.0V
50
300
ms
D0 = 0 [5]
5.5V
20
80
ms
D1 = 1 [5]
(80 ms)
4.0V
225
1200
ms
D0 = 1 [5]
5.5V
80
320
ms
D1 = 1 [5]
Notes:
[1]
Timing Reference uses 0.9 V
CC
for a logic 1 and 0.1 V
CC
for a logic 0.
[2]
Interrupt request through Port 3 (P33-P31).
[3]
Interrupt request through Port 3 (P30).
[4]
SMR D5 = 0.
[5]
Reg. WDTMR.
[6]
4.0V to 5.5V.
[7]
Reg. SMR D5 = 0.
[8]
Reg. SMR D5 = 1.
16
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS (Z86L73/L74)
Additional Timing Table
T
A
= 0
C to +70
C
V
CC
8.0 MHz
No
Symbol
Parameter
Note [3]
Min
Max
Units
Notes
1
TpC
Input Clock Period
2.0V
121
DC
ns
[1]
3.9V
121
DC
ns
[1]
2
TrC,TfC
Clock Input Rise
2.0V
25
ns
[1]
and Fall Times
3.9V
25
ns
[1]
3
TwC
Input Clock Width
2.0V
37
ns
[1]
3.9V
37
ns
[1]
4
TwTinL
Timer Input
2.0V
100
ns
[1]
Low Width
3.9V
70
ns
[1]
5
TwTinH
Timer Input
2.0V
3TpC
[1]
High Width
3.9V
3TpC
[1]
6
TpTin
Timer Input Period
2.0V
8TpC
[1]
3.9V
8TpC
[1]
7
TrTin,TfTin
Timer Input Rise
2.0V
100
ns
[1]
and Fall Timers
3.9V
100
ns
[1]
8A
TwIL
Interrupt Request
2.0V
100
ns
[1, 2]
Low Time
3.9V
70
ns
[1, 2]
8B
TwIL
Int. Request
2.0V
3TpC
[1, 3]
Low Time
3.9V
3TpC
[1, 3]
9
TwIH
Interrupt Request
2.0V
3TpC
[1, 2]
Input High Time
3.9V
3TpC
[1, 2]
10
Twsm
Stop-Mode Recovery
2.0V
12
ns
[8]
Width Spec
3.9V
12
ns
[8]
2.0V
5TpC
[7]
3.9V
5TpC
[7]
11
Tost
Oscillator
2.0V
5TpC
[4]
Start-up Time
3.9V
5TpC
[4]
12
Twdt
Watch-Dog Timer
(5 ms)
2.0V
12
75
ms
D0 = 0 [5]
Delay Time
3.9V
5
20
ms
D1 = 0 [5]
(10 ms)
2.0V
25
150
ms
D0 = 1 [5]
3.9V
10
40
ms
D1 = 0 [5]
(20 ms)
2.0V
50
300
ms
D0 = 0 [5]
3.9V
20
80
ms
D1 = 1 [5]
(80 ms)
2.0V
225
1200
ms
D0 = 1 [5]
3.9V
80
320
ms
D1 = 1 [5]
Notes:
[1]
Timing Reference uses 0.9 V
CC
for a logic 1 and 0.1 V
CC
for a logic 0.
[2]
Interrupt request through Port 3 (P33-P31).
[3]
Interrupt request through Port 3 (P30).
[4]
SMR D5 = 0.
[5]
Reg. WDTMR.
[6]
2.0V to 3.9V.
[7]
Reg. SMR D5 = 0.
[8]
Reg. SMR D5 = 1.
17
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS
Handshake Timing Diagrams
Data In
1
2
3
4
5
6
/DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
Input Handshake Timing
Data Out
/DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8
9
10
11
Output Handshake Timing
18
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS (Z86E73/E74)
Handshake Timing Table
T
A
= 0
C to +70
C
V
CC
8.0 MHz
Data
No
Symbol
Parameter
Note [3]
Min
Max
Direction
1
TsDI(DAV)
Data In Setup Time
4.0V
0
IN
5.5V
0
IN
2
ThDI(DAV)
Data In Hold Time
4.0V
160
IN
5.5V
115
IN
3
TwDAV
Data Available Width
4.0V
155
IN
5.5V
110
IN
4
TdDAVI(RDY)
DAV Falling to RDY
4.0V
160
IN
Falling Delay
5.5V
115
IN
5
TdDAVId(RDY)
DAV Rising to RDY
4.0V
120
IN
Falling Delay
5.5V
80
IN
6
TdRDYO(DAV)
RDY Rising to DAV
4.0V
0
IN
Falling Delay
5.5V
0
IN
7
TdDO(DAV)
Data Out to DAV
4.0V
63
OUT
Falling Delay
5.5V
63
OUT
8
TdDAV0(RDY)
DAV Falling to RDY
4.0V
0
OUT
Falling Delay
5.5V
0
OUT
9
TdRDY0(DAV)
RDY Falling to DAV
4.0V
160
OUT
Rising Delay
5.5V
115
OUT
10
TwRDY
RDY Width
4.0V
110
OUT
5.5V
80
OUT
11
TdRDY0d(DAV)
RDY Rising to DAV
4.0V
110
OUT
Falling Delay
5.5V
80
OUT
Note:
[3] 4.0V to 5.5V.
19
P R E L I M I N A R Y
Z86E73/E74/L73/L74
CP95LVO0801
AC CHARACTERISTICS (Z86L73/L74)
Handshake Timing Table
T
A
= 0
C to +70
C
V
CC
8.0 MHz
Data
No
Symbol
Parameter
Note [3]
Min
Max
Direction
1
TsDI(DAV)
Data In Setup Time
2.0V
0
IN
3.9V
0
IN
2
ThDI(DAV)
Data In Hold Time
2.0V
160
IN
3.9V
115
IN
3
TwDAV
Data Available Width
2.0V
155
IN
3.9V
110
IN
4
TdDAVI(RDY)
DAV Falling to RDY
2.0V
160
IN
Falling Delay
3.9V
115
IN
5
TdDAVId(RDY)
DAV Rising to RDY
2.0V
120
IN
Falling Delay
3.9V
80
IN
6
TdRDYO(DAV)
RDY Rising to DAV
2.0V
0
IN
Falling Delay
3.9V
0
IN
7
TdDO(DAV)
Data Out to DAV
2.0V
63
OUT
Falling Delay
3.9V
63
OUT
8
TdDAV0(RDY)
DAV Falling to RDY
2.0V
0
OUT
Falling Delay
3.9V
0
OUT
9
TdRDY0(DAV)
RDY Falling to DAV
2.0V
160
OUT
Rising Delay
3.9V
115
OUT
10
TwRDY
RDY Width
2.0V
110
OUT
3.9V
80
OUT
11
TdRDY0d(DAV)
RDY Rising to DAV
2.0V
110
OUT
Falling Delay
3.9V
80
OUT
Note:
[3] 2.0V to 3.9V.