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Электронный компонент: Z86E8316SSC

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DS97DZ80700
P R E L I M I N A R Y
8-1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86C83/C84/E83
1
CMOS Z8
MCU
FEATURES
s
28-Pin DIP, SOIC, and PLCC Packages
s
Clock Speed: 16 MHz
s
Three Expanded Register Groups
s
8-Channel, 8-Bit A/D Converter with Track and Hold,
and Unique R-Ladder A
GND
Offset Control
s
Z86C84 has two 8-Bit D/A Converters with
Programmable Gain Stages, 3 s Settling Time
s
Six Vectored, Prioritized Interrupts from Six Different
Sources
s
Two Analog Comparator Inputs with Programmable
Interrupt Polarity
s
Two Programmable 8-Bit Timers, each with a 6-Bit
Programmable Prescaler
s
Power-On Reset (POR) Timer
s
Permanent Watch-Dog Timer (WDT) Option
s
Software-Programmable Pull-Up Resistors (Port 2 Only)
s
On-Chip Oscillator for Crystal, Resonator or LC
s
ROM Protect
GENERAL DESCRIPTION
The Z86C83/C84/E83 are full-featured members of the
Z8
MCU family offering a unique register-to-register ar-
chitecture that avoids accumulator bottlenecks for higher
code efficiency than RISC processors.
The Z86C83/C84/E83 are designed to be used in a wide
variety of embedded control applications, such as appli-
ances, process controls, keyboards, security systems, bat-
tery chargers, and automotive modules.
For applications requiring powerful I/O capabilities, the
Z86C83/C84/E83 devices can have up to 21/17 (83/84 re-
spectively) pins dedicated to input and output. These lines
are grouped into three ports, and are configured by soft-
ware to provide digital/analog I/O timing and status signals.
An on-chip, half-flash 8-bit 1/2 Least Significant Bit (LSB)
A/D converter can multiplex up to eight analog inputs. Un-
used analog inputs revert to standard digital I/O use.
Unique, programmable A
GND
offset control of the A/D re-
sistor ladder compresses the converter's dynamic range
for maximum effective 9-bit A/D resolution.
The Z86C84 has two 8-bit 1/2 LSB D/A converters. High
and low reference voltages provide precise control of the
output voltage range. Programmable gain for each D/A
converter provides a maximum effective 10-bit resolution
for many tasks.
On-chip 8-bit counter/timers with many user-selectable
modes simplify real-time tasks, such as counting, timing,
and generation of PWM signals.
The designer can prioritize six different maskable, vec-
tored, internal or external interrupts for efficient interrupt
handling and multitasking functions.
Device
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Voltage
Range
Z86C83
4
237
21
3.0V to 5.5V
Z86E83
4 (OTP)
237
21
3.5V to 5.5V
Z86C84
4
237
17
3.0V to 5.5V
Note: * General-Purpose
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-2
P R E L I M I N A R Y
DS97DZ80700
GENERAL DESCRIPTION (Continued)
By means of an expanded register file, the designer has
access to additional control registers for configuring pe-
ripheral functions including the A/D and D/A converters,
counter/timers, and I/O port functions (Figure 1).
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Circuit
Device
Power
V
CC
V
CC
Ground
GND
V
SS
Figure 1. Z86C83/C84/E83 Functional Block Diagram
Notes:
** Not available on Z86C83/E83
Not available on Z86C84
Port 0
P00
P01
P02
P03
P04
P05
P06
P31
P32
P33
Port 3
Register File
Program
4K x 8
Z8 Core
Register Bus
Internal
Address Bus
Internal Data Bus
Expanded
Register File
Expanded
Register Bus
Counter/Timer
8-Bit (2)
Machine
Timing
and
Instruction
Control
Power
XTAL 1/2
VCC
P34
P35
P36
AC0/P20
AC1/P21
AC2/P22
AC3/P23
AC4/P24
AC5/P25
AC6/P26
AC7/P27
Port 2
Comparators
(2)
/RESET
GND
8-Channel
8-Bit A/D
**Dual
8-Bit
DAC
AVCC
AGND
VDHI **
VDL0 **
DAC1 **
DAC2 **
Memory
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-3
1
PIN DESCRIPTION
Figure 2. Z86C83 and Standard Mode Z86E83 28-Pin DIP
and SOIC Pin Configuration*
P21/AC1
P22/AC2
P23/AC3
P24/AC4
P25/AC5
P26/AC6
P27/AC7
/RESET
XTAL1
XTAL2
GND
VCC
P31
P32
P20/AC0
AVCC
AGND
P06
P05
P04
P03
P02
P01
P00
P35
P36
P34
P33
28
Z86C83/
Z86E83
DIP/ SOIC
28 - Pin
1
14
15
Table 1. Z86C83 and Standard Mode Z86E83 28-Pin DIP, SOIC, PLCC Pin Identification*
No
Symbol
Function
Direction
1-7
P21-P27
or AC1-AC7
Port 2, Bit 1-7
Analog In 1-7
Input/Output
8
/RESET
Reset
Input
9
XTAL1
Oscillator Clock
Input
10
XTAL2
Oscillator Clock
Output
11
GND
Ground
12
V
CC
Power
13-15
P31-P33
Port 3, Bits 1-3
Input
16
P34
Port 3, Bit 4
Output
17
P36
Port 3, Bit 6
Output
18
P35
Port 3, Bit 5
Output
19-25
P00-P06
Port 0, Bits 0-6
Input/Output
26
A
GND
Analog Ground
27
AV
CC
Analog Power
28
P20
or AC0
Port 2, Bit 0
Analog In 0
Input/Output
Note: * DIP and SOIC Pin Description and Configuration are identical.
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-4
P R E L I M I N A R Y
DS97DZ80700
PIN DESCRIPTION (Continued)
Figure 3. Z86C84 28-Pin DIP and SOIC Pin Configuration
P21/AC1
P22/AC2
P23/AC3
P24/AC4
P25/AC5
P26/AC6
P27/AC7
/RESET
XTAL1
XTAL2
GND
VCC
P31
P32
P20/AC0
AVCC
AGND
DAC1
DAC2
VDHI
VDLO
P02
P01
P00
P35
P36
P34
P33
28
Z86C84
DIP/SOIC
28 - Pin
1
14
15
Table 2. Z86C84 28-Pin DIP, SOIC, PLCC Pin Identification*
No
Symbol
Function
Direction
1-7
P21-P27
or AC1-AC7
Port 2, Bit 1-7
Analog In 1-7
Input/Output
8
/RESET
Reset
Input
9
XTAL1
Oscillator Clock
Input
10
XTAL2
Oscillator Clock
Output
11
GND
Ground
12
V
CC
Power
13-15
P31-P33
Port 3, Bits 1-3
Input
16
P34
Port 3, Bit 4
Output
17
P36
Port 3, Bit 6
Output
18
P35
Port 3, Bit 5
Output
19-21
P00-P02
Port 0, Bits 0-3
Input/Output
22
VDLO
D/A Ref. Volt.,Low
Input
23
VDHI
D/A Ref. Volt.,High
Input
24-25
DAC2-1
D/A Converter
Output
26
A
GND
Analog Ground
27
AV
CC
Analog Power
28
P20
or AC0
Port 2, Bit 0
Analog In 0
Input/Output
Note: * DIP, PLCC and SOIC Pin Description and Configuration are identical
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-5
1
Figure 4. Z86E83 EPROM Programing Mode 28-Pin DIP and SOIC Pin Configuration
D1
D2
D3
D4
D5
D6
D7
NC
/CE
NC
GND
VCC
/OE
EPM
D0
NC
NC
NC
NC
NC
NC
/PGM
CLK
CLR
NC
NC
NC
VPP
28
Z86E83
(EPROM Mode)
DIP/SOIC
28 - Pin
1
14
15
Table 3. Z86E83 EPROM Programming Mode 28-Pin DIP, PLCC and SOIC Pin Identification
No
Symbol
Function
Direction
1-7
D1-D7
Data 1,2,3,4,5,6,7
Input/Output
8
NC
No Connection
9
/CE
Chip Enable
Input
10
NC
No Connection
11
GND
Ground
12
V
CC
Power
13
/OE
Output Enable
Input
14
EPM
EPROM Program Mode
Input
15
V
PP
Program Voltage
Input
16-18
NC
No Connection
19
CLR
Clear CLock
Input
20
CLK
Address
Input
21
/PGM
Program Mode
Input
22-27
NC
No Connection
28
D0
Data 0
Input/Output
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-6
P R E L I M I N A R Y
DS97DZ80700
Figure 5. Z86C83 and Standard Mode Z86E83 28-Pin PLCC Pin Configuration
25
19
5
11
18
12
26
4
Z86C83/E83
PLCC 28 - Pin
1
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
P06
P05
P04
P03
P02
P01
P00
P25/AC5
P26/AC6
P27/AC7
/RESET
XTAL1
XTAL2
GND
Figure 6. Z86C84 28-Pin PLCC Pin Configuration
25
19
5
11
18
12
26
4
Z86C84
PLCC 28 - Pin
1
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
DAC1
DAC2
VDHI
VDLO
P02
P01
P00
P25/AC5
P26/AC6
P27/AC7
/RESET
XTAL1
XTAL2
GND
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-7
1
Figure 7. Z86E83 EPROM Programming Mode 28-Pin
PLCC Pin Configuration
25
19
5
11
18
12
26
4
Z86E83
PLCC 28 - Pin
1
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
NC
NC
NC
NC
/PGM
CLK
CLR
D5
D6
D7
NC
/CE
NC
GND
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-8
P R E L I M I N A R Y
DS97DZ80700
ABSOLUTE MAXIMUM RATING
Notice:
Stresses greater than those listed under Absolute Maximum Rat-
ings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at any condition
above those indicated in the operational sections of these speci-
fications is not implied. Exposure to absolute maximum rating
conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 770 mW for the pack-
age.
Power dissipation is calculated as follows:
Parameter
Min
Max
Units
Notes
Ambient Temperature under Bias
40
+105
C
Storage Temperature
65
+150
C
Voltage on any Pin with Respect to V
SS
0.6
+7
V
1
Voltage on V
CC
Pin with Respect to V
SS
0.3
+7
V
Voltage on /RESET Pin with Respect to V
SS
0.6
V
CC
+1
V
2
Voltage on P32, P33 and /Reset Pin with Respect to V
SS
-0.6
V
CC
+1
V
2,5
Total Power Dissipation
770
mW
Maximum Current out of V
SS
140
mA
Maximum Current into V
CC
125
mA
Maximum Current into an Input Pin
600
+600
A
3
Maximum Current into an Open-Drain Pin
600
+600
A
4
Maximum Output Current Sinked by Any I/O Pin
25
mA
Maximum Output Current Sourced by Any I/O Pin
25
mA
Notes:
1. This applies to all pins except /RESET pin and where otherwise noted.
2. There is no input protection diode from pin to V
CC
.
3. This excludes XTAL pins.
4. Device pin is not at an output Low state.
5. For Z86E83 only
Total Power Dissipation =
V
CC
x [I
CC
(sum of I
OH
)]
+ sum of [(V
CC
V
OH
) x I
OH
]
+ sum of (V
0L
x I
0L
)
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-9
1
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 8).
V
DD
SPECIFICATION
V
DD
= 3.5V to 5.5V (Z86E83 only at 0 C to 70 C)
V
DD
= 3.0V to 5.5V (Z86C83/C84)
V
DD
= 4.5V to 5.5V (Z86E83 only at -40 C to 105 C)
CAPACITANCE
T
A
= 25C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Figure 8. Test Load Diagram
From Output
Under Test
150 pF
I
Parameter
Min
Max
Input capacitance
0
15 pF
Output capacitance
0
15 pF
I/O capacitance
0
15 pF
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-10
P R E L I M I N A R Y
DS97DZ80700
DC ELECTRICAL CHARACTERISTICS
For Z86C83/C84 Only
Sym
Parameter
V
CC
Note 3
T
A
= 0 C
to +70C
T
A
= 40C
to +105C
Typical
[13]
@ 25C Units Conditions
Notes
Min
Max
Min
Max
V
CH
Clock Input High
Voltage
3.0V
0.7 V
CC
V
CC
+0.3 0.7 V
CC
V
CC
+0.3
1.3
V
Driven by External
Clock Generator
5.5V
0.7 V
CC
V
CC
+0.3 0.7 V
CC
V
CC
+0.3
2.5
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
3.0V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
0.7
V
Driven by External
Clock Generator
5.5V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
1.5
V
Driven by External
Clock Generator
V
IH
Input High
Voltage
3.0V
0.7 V
CC
V
CC
+0.3 0.7 V
CC
V
CC
+0.3
1.3
V
5.5V
0.7 V
CC
V
CC
+0.3 0.7 V
CC
V
CC
+0.3
2.5
V
V
IL
Input Low Voltage 3.0V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
0.7
V
5.5V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
1.5
V
V
OH1
Output High
Voltage
3.0V
V
CC
-0.4
V
CC
-0.4
3.1
V
I
OH
= -2.0 mA
8
5.5V
V
CC
-0.4
V
CC
-0.4
4.8
V
I
OH
= -2.0 mA
8
V
OL1
Output Low
Voltage
3.0V
0.6
0.6
0.2
V
I
OL
= +4.0 mA
8
5.5V
0.4
0.4
0.1
V
I
OL
= +4.0 mA
8
V
OL2
Output Low
Voltage
3.0V
1.2
1.2
0.3
V
I
OL
= +6 mA
8
5.5V
1.2
1.2
0.3
V
I
OL
= +10 mA
8
V
RH
Reset Input High
Voltage
3.0V
.8 V
CC
V
CC
.8 V
CC
V
CC
1.5
V
5.5V
.8 V
CC
V
CC
.8 V
CC
V
CC
2.1
V
V
Rl
Reset Input Low
Voltage
3.0V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
1.1
V
5.5V GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
1.7
V
V
OFFSET
Comparator Input
Offset Voltage
3.0V
25
25
10
mV
10
5.5V
25
25
10
mV
10
I
IL
Input Leakage
3.0V
-1
1
-1
2
<1
A V
IN
= 0V, V
CC
5.5V
-1
1
-1
2
<1
A V
IN
= 0V, V
CC
I
OL
Output Leakage
3.0V
-1
1
-1
2
<1
A V
IN
= 0V, V
CC
5.5V
-1
1
-1
2
<1
A V
IN
= 0V, V
CC
I
IR
Reset Input
Current
3.0V
-130
-130
-25
A
5.5V
-180
-180
-40
A
I
CC
Supply Current
3.0V
20
20
7
mA @ 16 MHz
1,4
5.5V
25
25
20
mA @ 16 MHz
1,4
5.0V
7
7
3
mA @ 3.58 MHz
1,4,15
5.5V
10
10
5
mA @ 8 MHz
1,4,15
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-11
1
I
CC1
Standby Current
(HALT Mode)
3.0V
4.5
4.5
2.0
mA V
IN
= 0V, V
CC
@ 16
MHz
4
5.5V
8
8
3.7
mA V
IN
= 0V, V
CC
@
16 MHz
4
3.0V
3.4
3.4
1.5
mA Clock Divide-by-16
@ 16 MHz
4
5.5V
7.0
7.0
2.9
mA Clock Divide-by-16
@ 16 MHz
4
I
CC2
Standby Current
(STOP Mode)
3.0V
8
15
1
A V
IN
= 0V,V
CC
Vcc WDT is not
Running
1,6,11
5.5V
10
20
2
A V
IN
= 0V, V
CC
WDT is not
Running
1,6,11
3.0V
500
600
310
A V
IN
= 0V, V
CC
WDT is Running
1,6,11,14
5.5V
800
1000
600
A V
IN
= 0V, V
CC
WDT is not
Running
1,6,11,14
V
ICR
Input Common
Mode
3.0
0
V
CC
-
1.0V
0
V
CC
-
1.5V
V
10
Voltage Range
5.5
0
V
CC
-
1.0V
0
V
CC
-
1.5V
V
10
I
ALL
Auto Latch Low
Current
3.0V
8
10
5
A 0V < V
IN
< V
CC
9
5.5V
15
20
11
A 0V < V
IN
< V
CC
9
I
ALH
Auto Latch High
Current
3.0V
-5
-7
-3
A 0V < V
IN
< V
CC
9
5.5V
-8
-10
-6
A 0V < V
IN
< V
CC
9
V
LV
V
CC
Low-Voltage
Protection Voltage
2.0
3.3
2.2
3.5
3.0
V
2 MHz max Int.
CLK Freq.
7
Notes:
1. Combined digital V
CC
and Analog AV
CC
supply currents.
2. GND = 0V.
3. V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
4. All outputs unloaded, I/O pins floating, inputs at rail.
5. CL1 = CL2 = 22 pF.
6.
Same as note [4] except inputs at V
CC
.
7. The V
LV
increases as the temperature decreases.
8. Standard Mode (not Low EMI).
9. Auto Latch (mask option) selected.
10. For analog comparator, inputs when analog comparators are enabled.
11. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
12. Excludes clock pins.
13. Typicals are at V
CC
= 5.0V and 3.3V.
14. Internal RC selected
15. For Z86C83 only
Sym
Parameter
V
CC
Note 3
T
A
= 0 C
to +70C
T
A
= 40C
to +105C
Typical
[13]
@ 25C Units Conditions
Notes
Min
Max
Min
Max
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-12
P R E L I M I N A R Y
DS97DZ80700
AC ELECTRICAL CHARACTERISTICS
For Z86C83/C84 Only. Low EMI Mode Only.
T
A
= 0C to +70C
T
A
= -40 to +105C
4 MHz
4 MHz
No
Symbol
Parameter
V
CC
[6]
Min
Max
Min
Max
Units Notes
1
TpC
Input Clock Period
3.0V
250
DC
250
DC
ns
1,7,8
5.5V
250
DC
250
DC
ns
1,7,8
2
TrC, TfC
Clock Input Rise & Fall Times
3.0V
25
25
ns
1,7,8
5.5V
25
25
ns
1,7,8
3
TwC
Input Clock Width
3.0V
125
125
ns
1,7,8
5.5V
125
125
ns
1,7,8
4
TwTinL
Timer Input Low Width
3.0V
100
100
ns
1,7,8
5.5V
100
100
ns
1,7,8
5
TwTinH
Timer Input High Width
3.0V
3TpC
3TpC
ns
1,7,8
5.5V
3TpC
3TpC
ns
1,7,8
6
TpTin
Timer Input Period
3.0V
4TpC
4TpC
1,7,8
5.5V
4TpC
4TpC
1,7,8
7
TrTin,
TfTin
Timer Input Rise & Fall Timer
3.0V
100
100
ns
1,7,8
5.5V
100
100
ns
1,7,8
8A
TwIL
Int. Request Low Time
3.0V
100
100
ns
1,7,8
5.5V
70
70
ns
1,7,8
8B
TwIL
Int. Request Low Time
3.0V
3TpC
3TpC
ns
1,3,7,8
5.5V
3TpC
3TpC
ns
1,3,7,8
9
TwIH
Int. Request Input High Time
3.0V
3TpC
3TpC
ns
1,2,7,8
5.5V
3TpC
3TpC
ns
1,2,7,8
10
Twsm
Stop-Mode Recovery Width
Spec
3.0V
12
12
ns
4,8
5.5V
12
12
ns
4,8
11
Tost
Oscillator Start-up Time
3.0V
5TpC
5TpC
4,8,9
5.5V
5TpC
5TpC
4,8,9
Notes:
1. Timing Reference uses 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request via Port 3 (P33-P31)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode delay is on.
5. Reg. WDTMR
6. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode
9. For LC oscillator and for oscillator driven by clock driver
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-13
1
For Z86E83 Only
T
A
= 0 C
T
A
= -40 C
Typical
to +70 C
to +105 C
[13]
Sym
Parameter
V
CC
[3]
Min
Max
Min
Max
@25C Units Conditions
Notes
V
CH
Clock Input High
Voltage
3.5V
0.7 V
CC
V
CC
+0.3
1.3
V
Driven by External
Clock Generator
5.5V
0.7 V
CC
V
CC
+0.3 0.7 V
CC
V
CC
+0.3
2.5
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
3.5V
GND-0.3 0.2 V
CC
0.7
V
Driven by External
Clock Generator
5.5V
GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
1.5
V
Driven by External
Clock Generator
V
IH
Input High Voltage
3.5V
0.7 V
CC
V
CC
+0.3
1.3
V
5.5V
0.7 V
CC
V
CC
+0.3 0.7 V
CC
V
CC
+0.3
2.5
V
V
IL
Input Low Voltage
3.5V
GND-0.3 0.2 V
CC
0.7
V
5.5V
GND-0.3 0.2 V
CC
GND-0.3 0.2 V
CC
1.5
V
V
OH1
Ouput High Voltage
3.5V
V
CC
-0.4
3.1
V
I
OH
= -2.0 mA
8
5.5V
V
CC
-0.4
V
CC
-0.4
4.8
V
I
OH
= -2.0 mA
8
V
OL1
Output Low Voltage
3.5V
0.6
0.2
V
I
OH
= +4.0 mA
8
5.5V
0.4
0.4
0.1
V
I
OH
= +4.0 mA
8
V
OL2
Output Low Voltage
3.5V
1.2
0.3
V
I
OH
= +6.0 mA
8
5.5V
1.2
1.2
0.3
V
I
OH
= +10.0 mA
8
V
RH
Reset Input High
Voltage
3.5V
0.8V
CC
V
CC
1.5
V
5.5V
0.8V
CC
V
CC
0.8V
CC
V
CC
2.1
V
3.5V
GND-0.3 0.2V
CC
1.1
V
5.5V
GND-0.3 0.2V
CC
GND-0.3 0.2V
CC
1.7
V
V
OFFS
ET
Comparator Input
Offset Voltage
3.5V
25
10
mV
10
5.5V
25
25
10
mV
10
I
IL
Input Leakage
3.5V
-1
1
<1
A V
IN
= 0V, V
CC
5.5V
-1
1
-1
2
<1
A V
IN
= 0V, V
CC
I
OL
Output Leakage
3.5V
-1
1
<1
A V
IN
= 0V, V
CC
5.5V
-1
1
-1
2
<1
A V
IN
= 0V, V
CC
I
IR
Reset Input Current
3.5V
-130
-25
A
5.5V
-180
-180
-40
A
I
CC
Supply Current
3.5V
20
7
mA @16 MHz
1,4
5.5V
25
25
20
mA @16 MHz
1,4
I
CC1
Standby Current
(HALT Mode)
3.5V
4.5
2.0
mA V
IN
= 0V, V
CC
@ 16
MHz
1,4
5.5V
8
8
3.7
mA V
IN
= 0V, V
CC
@ 16
MHz
1,4
3.5V
3.4
1.5
mA Clock divide by 16 @
16 MHz
1,4
5.5V
7.0
7.0
2.9
mA Clock divide by 16 @
16 MHz
1,4
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-14
P R E L I M I N A R Y
DS97DZ80700
I
CC2
Standby Current
(STOP Mode)
3.5V
8
1
A V
IN
= 0V, V
CC
WDT is not Running
1,6,11
5.5V
10
20
2
A V
IN
= 0V, V
CC
WDT is not Running
1,6,11
3.5V
500
310
A V
IN
= 0V, V
CC
WDT is Running
1,6,11,
14
5.5V
800
1000
600
A V
IN
= 0V, V
CC
WDT is Running
1,6,11,
14
V
ICR
Input Common
Mode
3.5V
0
V
CC
-
1.0V
0
V
10
5.5V
0
V
CC
-
1.0V
0
V
CC
-1.5V
V
10
I
ALL
Auto Latch Low
Current
3.5V
8
5
A 0V<V
IN
<V
CC
9
5.5V
15
20
11
A 0V<V
IN
<V
CC
9
I
ALH
Auto Latch High
Current
3.5V
-5
-3
A 0V<V
IN
<V
CC
9
5.5V
-8
-10
-6
A 0V<V
IN
<V
CC
9
V
LV
V
CC
Low-Voltage
Protection Voltage
2.0
3.3
2.2
3.5
3.0
V
2 MHz max. Int. CLK
Frequency
7
Notes:
1. Combined digital V
CC
and analog AV
CC
supply currents
2. GND = 0V
3. V
CC
voltage specification of 3.5V guarantees 3.5V, and V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V
4. All outputs unloaded, I/O pins floating, inputs at rail
5. CL1 = CL2 = 100 pF
6. Same as note [4] except inputs at V
CC
7. The V
LV
increases as the temperature decreases
8. Standard Mode (not Low EMI)
9. Auto Latch (mask option) selected
10. For analog comparator, inputs when analog comparators are enabled
11. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating
12. Excludes clock pins
13. Typicals are at V
CC
= 3.5V and 5.0V
14. Internal RC selected
T
A
= 0 C
T
A
= -40 C
Typical
to +70 C
to +105 C
[13]
Sym
Parameter
V
CC
[3]
Min
Max
Min
Max
@25C Units Conditions
Notes
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-15
1
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
Figure 9. Additional Timing
Clock
1
3
4
8
2
2
3
TIN
IRQN
6
5
7
7
11
Clock
Setup
10
9
Stop-Mode
Recovery
Source
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-16
P R E L I M I N A R Y
DS97DZ80700
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (SCLK/TCLK = XTAL/2) For Z86E83 Only
No
Symbol Parameter
V
CC
Note 6
T
A
= 0C to +70C
Units
Notes
12 MHz
16 MHz
Min
Max
Min
Max
1
TpC
Input Clock Period
3.5V
83
DC
62.5
DC
ns
1
5.5V
83
DC
62.5
DC
ns
1
2
TrC,TfC
Clock Input Rise & Fall Times
3.5V
15
15
ns
1
5.5V
15
15
ns
1
3
TwC
Input Clock Width
3.5V
41
31
ms
1
5.5V
41
31
ns
1
4
TwTinL
Timer Input Low Width
3.5V
100
100
ms
1
5.5V
70
70
ns
1
5
TwTinH
Timer Input High Width
3.5V
5TpC
5TpC
1
5.5V
5TpC
5TpC
1
6
TpTin
Timer Input Period
3.5V
8TpC
8TpC
1
5.5V
8TpC
8TpC
1
7
TrTin,
Timer Input Rise & Fall Timer
3.5V
100
100
ns
1
TfTin
5.5V
100
100
ns
1
8A
TwIL
Int. Request Low Time
3.5V
100
100
ns
1,2
5.5V
70
70
ns
1,2
8B
TwIL
Int. Request Low Time
3.5V
5TpC
5TpC
1,3
5.5V
5TpC
5TpC
1,3
9
TwIH
Int. Request Input High Time
3.5V
5TpC
5TpC
1,2
5.5V
5TpC
5TpC
1,2
10
Twsm
Stop-Mode Recovery Width Spec
3.5V
12
12
ns
5.5V
12
12
ns
11
Tost
Oscillator Start-up Time
3.5V
5TpC
5TpC
4
5.5V
5TpC
5TpC
4
12
Twdt
Watch-Dog Timer Delay Time
WDTMR
Reg
D1,D0
5.5V
6.25
6.25
ms
0,0,[7]
5.5V
12.5
12.5
ms
0,1,[7]
5.5V
25
25
ms
1,0,[7]
5.5V
100
100
ms
1,1,[7]
13
T
POR
Power On Reset Delay
3.5V
7
24
7
25
ms
7
5.5V
3
13
3
14
ms
7
Notes:
1. Timing Reference uses 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request via Port 3 (P31-P33).
3. Interrupt request via Port 3 (P30).
4. SMR-D5 = 0.
5. Reg. WDTMR.
6. The V
CC
voltage specification of 3.5V guarantees 3.5V, and the V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
7. Using internal on-board RC oscillator.
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-17
1
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (Low EMI Mode Only) For Z86E83 Only
No
Symbol
Parameter
V
CC
[Note 6]
T
A
= 0C to +70C
T
A
= -40C to +105C
Units
Notes
4 MHz
4 MHz
Min
Max
Min
Max
1
TpC
Input Clock Period
3.5V
250
DC
ns
1,7,8
5.5V
250
DC
250
DC
ns
1,7,8
2
TrC,TfC
Clock Input Rise & Fall Times
3.5V
25
ns
1,7,8
5.5V
25
25
ns
1,7,8
3
TwC
Input Clock Width
3.5V
125
ns
1,7,8
5.5V
125
125
ns
1,7,8
4
TwTinL
Timer Input Low Width
3.5V
100
ns
1,7,8
5.5V
70
70
ns
1,7,8
5
TwTinH
Timer Input High Width
3.5V
3TpC
1,7,8
5.5V
3TpC
3TpC
1,7,8
6
TpTin
Timer Input Period
3.5V
4TpC
1,7,8
5.5V
4TpC
4TpC
1,7,8
7
TrTin,
Timer Input Rise & Fall Timer
3.5V
100
ns
1,7,8
TfTin
5.5V
100
100
ns
1,7,8
8A
TwIL
Int. Request Low Time
3.5V
100
ns
1,2,7,8
5.5V
70
70
ns
1,2,7,8
8B
TwIL
Int. Request Low Time
3.5V
3TpC
1,3,7,8
5.5V
3TpC
3TpC
1,3,7,8
9
TwIH
Int. Request Input High Time
3.5V
3TpC
1,2,7,8
5.5V
3TpC
2TpC
1,2,7,8
10
Twsm
Stop-Mode Recovery Width
Spec
3.5V
12
ns
4,8
5.5V
12
12
ns
4,8
11
Tost
Oscillator Start-up Time
3.5V
5TpC
4,8,9
5.5V
5TpC
5TpC
4,8,9
Notes:
1. Timing Reference uses 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode delay is on.
5. Reg. WDTMR
6. The V
CC
voltage specification of 3.5V guarantees 3.5V,
and the V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode.
9. For LC oscillator and for oscillator driven by clock driver
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-18
P R E L I M I N A R Y
DS97DZ80700
CAPACITANCE (Continued)
Additional Timing Table (SKLK/TCLK = XTAL/2) For Z86C83/C84 Only
T
A
= 0C to +70C
T
A
= -40C to +150C
VCC
12 MHz
16MHz
12 MHz
16 MHz
No Sym
Parameter
[6]
Min
Max
Min
Max
Min
Max
Min
Max
Units Notes
1
TpC
Input Clock Period
3.0V
83
DC
62.5
DC
83
DC
62.5
DC
ns
1
5.5V
83
DC
62.5
DC
83
DC
62.5
DC
ns
1
2
TrC,
TfC
Clock Input Rise &
Fall Times
3.0V
15
15
15
15
ns
1
5.5V
15
15
15
15
ns
1
3
TwC
Input Clock Width
3.0V
41
31
41
31
ns
1
5.5V
41
31
41
31
ns
1
4
TwTinL Timer Input Low
Width
3.0V
100
100
100
100
ns
1
5.5V
70
70
70
70
ns
1
5
TwTinH Timer Input High
Width
3.0V
5TpC
5TpC
5TpC
5TpC
1
5.5V
5TpC
5TpC
5TpC
5TpC
1
6
TpTin
Timer Input Period
3.0V
8TpC
8TpC
8TpC
8TpC
1
5.5V
8TpC
8TpC
8TpC
8TpC
1
7
TrTin,
TfTin
Timer Input Rise &
Fall Timer
3.0V
100
100
100
100
ns
1
5.5V
100
100
100
100
ns
1
8A
TwIL
Int. Request Low
Time
3.0V
100
100
100
100
ns
1,2
5.5V
70
70
70
70
ns
1,2
8B
TwIL
Int. Request Low
Time
3.0V
5TpC
5TpC
5TpC
5TpC
1,3
5.5V
5TpC
5TpC
5TpC
5TpC
1,3
9
TwIH
Int. Request High
Time
3.0V
5TpC
5TpC
5TpC
5TpC
1,2
5.5V
5TpC
5TpC
5TpC
5TpC
1,2
10
Twsm
Stop-Mode Recovery
Width Spec
3.0V
12
12
12
12
ns
5.5V
12
12
12
12
ns
11
Tost
Oscillator Start-up
Time
3.0V
5TpC
5TpC
5TpC
5TpC
5.5V
5TpC
5TpC
5TpC
5TpC
12
Twdt
Watch-Dog Timer
Delay Time
WDTMR
Reg
D1,D0
5.5V
6.25
6.25
6.25
6.25
ms
0,0 [6]
5.5V
12.5
12.5
12.5
12.5
ms
0,1 [6]
5.5V
25
25
25
25
ms
1,0 [6]
5.5V
100
100
100
100
ms
1,1 [6]
13
T
POR
Power On Reset
Delay
3.0V
7
24
7
25
7
24
7
25
ms
6
5.5V
3
13
3
14
3
13
3
14
ms
6
Notes:
1. Timing References used 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 0
5. The V
CC
voltage specification of 3.0V guarantees 3.3V 0.3V, and the V
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
6. Using internal on-board RC oscillator
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-19
1
For Z86C84 Only
For Z86C84 Only
Table 4. D/A Converter Electrical Characteristics
V
CC
= 3.3V 10%
Parameter
Minimum
Typical
Maximum
Units
Resolution
8
Bits
Integral non-linearity
0.25
1
LSB
Differential non-linearity
0.25
0.5
LSB
Setting time, 1/2 LSB
1.5
3.0
sec
Zero Error at 25C
10
20
mV
Full Scale error at 25C
0.25
0.5
LSB
Supply Range
3.0
3.3
3.6
Volts
Power dissipation, no load
10
mW
Ref Input resistance
2K
4K
10K
Ohms
Output noise voltage
50
Vp-p
VDHI
range at 3 volts
1.5
1.8
2.1
Volts
VDLO range at 3 volts
0.2
0.5
0.8
Volts
VDHIVDLO, at 3 volts
1.3
1.6
1.9
Volts
Capacitive output load, CL
20
pF
Resistive output load, RL
50K
Ohms
Output slew rate
1.0
3.0
V/sec
Notes:
Voltage: 3.0V 3.6V
Temp: 070C
Table 5. D/A Converter Electrical Characteristics
V
CC
= 5.0V 10%
Parameter
Minimum
Typical
Maximum
Units
Resolution
8
Bits
Integral non-linearity
0.25
1
LSB
Differential non-linearity
0.25
0.5
LSB
Setting time, 1/2 LSB
1.5
3.0
sec
Zero Error at 25C
10
20
mV
Full Scale error at 25C
1
2
% FSR
Supply Range
4.5
5.0
5.5
Volts
Power dissipation, no load
50
85
mW
Ref Input resistance
2K
4K
10K
Ohms
Output noise voltage
50
Vp-p
VDHI
range at 5 volts
2.6
3.5
Volts
VDLO range at 5V volts
0.8
1.7
Volts
VDHIVDLO, at 5V volts
0.9
2.7
Volts
Capacitive output load, CL
30
pF
Resistive output load, RL
20K
Ohms
Output slew rate
1.0
3.0
V/sec
Notes:
Voltage: 4.5V - 5.5V
Temp: 0-70C
The C86C84 Emulator has maximum setting time of 20 sec. (10 sec. typical).
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-20
P R E L I M I N A R Y
DS97DZ80700
CAPACITANCE (Continued)
For Z86C83/C84
For Z86C83/C84
Table 6. A/D Converter Electrical Characteristics
V
CC
= 3.3V 10%
Parameter
Minimum
Typical
Maximum
Units
Resolution
8
Bits
Integral non-linearity
0.5
1
LSB
Differential non-linearity
0.5
1
LSB
Zero Error at 25C
5.0
mV
Supply Range
2.7
3.0
3.3
Volts
Power dissipation, no load
20
40
mW
Clock frequency
16
MHz
Input voltage range
VA
LO
VA
HI
Volts
Conversion time
35 x SCLK
sec
Input capacitance on ANA
25
40
pF
VA
HI
range
VA
LO
+2.5
AV
CC
Volts
VA
LO
range
AN
GND
AV
CC
2.5
Volts
VA
HI
-VA
LO
2.5
AV
CC
Volts
Notes:
Voltage: 3.0V 3.6V
Temp: 0-70C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
Table 7. A/D Converter Electrical Characteristics
V
CC
= 5.0V 10%
Parameter
Minimum
Typical
Maximum
Units
Resolution
8
Bits
Integral non-linearity
0.5
1
LSB
Differential non-linearity
0.5
1
LSB
Zero Error at 25C
45
mV
Supply Range
4.5
5.0
5.5
Volts
Power dissipation, no load
50
85
mW
Clock frequency
16
MHz
Input voltage range
VA
LO
VA
HI
Volts
Conversion time
35 x SCLK
sec
Input capacitance on ANA
25
40
pF
VA
HI
range
VA
LO
+2.5
AV
CC
Volts
VA
LO
range
AN
GND
AV
CC
2.5
Volts
VA
HI
-VA
LO
2.5
AV
CC
Volts
Notes:
Voltage: 4.5V 5.5V
Temp: 0-70C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-21
1
For Z86E83
For Z86E83
Table 8. A/D Converter Electrical Characteristics
V
CC
= 3.5V
Parameter
Minimum
Typical
Maximum
Units
Resolution
8
Bits
Integral non-linearity
0.5
1
LSB
Differential non-linearity
0.5
1
LSB
Zero Error at 25C
5.0
mV
Supply Range
3.5
Volts
Power dissipation, no load
20
40
mW
Clock frequency
16
MHz
Input voltage range
VA
LO
VA
HI
Volts
Conversion time
35 x SCLK
sec
Input capacitance on ANA
25
40
pF
VA
HI
range
VA
LO
+2.5
AV
CC
Volts
VA
LO
range
AN
GND
AV
CC
2.5
Volts
VA
HI
-VA
LO
2.5
AV
CC
Volts
Notes:
Voltage: 3.5V
Temp: 0-70C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
Table 9. A/D Converter Electrical Characteristics
V
CC
= 5.0V 10%
Parameter
Minimum
Typical
Maximum
Units
Resolution
8
Bits
Integral non-linearity
0.5
1
LSB
Differential non-linearity
0.5
1
LSB
Zero Error at 25C
45
mV
Supply Range
4.5
5.0
5.5
Volts
Power dissipation, no load
50
85
mW
Clock frequency
16
MHz
Input voltage range
VA
LO
VA
HI
Volts
Conversion time
4.3
35 x SCLK
sec
Input capacitance on ANA
25
40
pF
VA
HI
range
VA
LO
+2.5
AV
CC
Volts
VA
LO
range
AN
GND
AV
CC
2.5
Volts
VA
HI
-VA
LO
2.5
AV
CC
Volts
Notes:
Voltage: 4.5V 5.5V
Temp: 0-70C
Conversion time is defined as the time from initiation of A-D conversion to storage of the digital result in the ADR register.
SCLK = Internal Z8 System Clock (Bus Speed)
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-22
P R E L I M I N A R Y
DS97DZ80700
PIN FUNCTIONS
EPROM Programming Mode (E83 Only)
D7-D0. Data Bus. The data can be read from or written to
the EPROM through the data bus.
Clock. Address Clock. This pin is a clock input. The inter-
nal address counter increases by one with one clock sig-
nal.
Clear. Clear. (active High). This pin resets the internal ad-
dress counter at the High Level.
V
CC.
Power Supply. This pin must supply 5V during the
EPROM Read Mode and 6V during other modes.
/CE. Chip Enable (active Low). This pin is active during
EPROM Read, Program, and Program Verify Modes.
/OE. Output Enable (active Low). This pin drives the direc-
tion of the Data Bus. When this pin is Low, the Data Bus is
output, when High, the Data Bus is input.
EPM. EPROM Program Mode. This pin controls the differ-
ent EPROM Program Mode by applying different voltages.
V
PP.
Program Voltage. This pin supplies the program volt-
age.
/PGM. Program Mode (active Low). When this pin is Low,
the data is programmed to the EPROM through the Data
Bus.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
surges above V
cc
occur on the /RESET pin.
Processor operation of Z8
OTP devices may be affected
by excessive noise surges on the VPP, /EPM, /OE pins
while the microcontroller is in Standard Mode.
Recommendations for dampening voltage surges in both
test and OTP mode include the following:
s
Using a clamping diode to /RESET, VPP, /EPM, /OE
s
Adding a capacitor to the affected pin
Z86C83, Z86C84, and Standard Mode Z86E83
XTAL1. Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC network
or an external single-phase clock to the on-chip oscillator
input.
XTAL2. Crystal 2 (time-based output). This pin connects a
parallel-resonant crystal, ceramic resonator, LC network to
the on-chip oscillator output.
Port 0 P00-P06 (P03-P06 is not available on the Z86C84).
Port 0 is a 7-bit, bidirectional, CMOS-compatible I/O port.
These seven I/O lines can be nibble programmable as
P00-P03 input/output and P04-P06 input/output, separate-
ly (Figure 10). All input buffers are Schmitt-triggered and
output drivers are push-pull.
Port 0 Auto Latch. (P03-P06 has the Auto Latches per-
manently enabled). The Auto Latch provides valid CMOS
Levels when P03-P06 are selected as inputs and not ex-
ternally driven. It is impossible to determine if a non-driven
input is 1 or 0, however; the Auto Latch will sense the input
condition and drive a valid CMOS level, thereby eliminat-
ing a floating mode that could cause excessive current.
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-23
1
Figure 10. Port 0 Configuration
R 500 k
/OEN
Out
In
1.5 2.3 Hysteresis
Pad
Port 0 (I/O)
Notes:
Auto Latch
C83/E83:
P03-P06 Permanent
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-24
P R E L I M I N A R Y
DS97DZ80700
PIN FUNCTIONS (Continued)
Port 2 (P27-P20) Port 2 is an 8-bit, bidirectional, CMOS-
compatible I/O port and an 8-channel muxed input to the
8-bit ADC. When configured as a digital input, by program-
ming the Port2 Mode register, the Port 2 register can be
evaluated to read digital data applied to Port 2, or the ADC
result register can be read to evaluate the analog signals
applied to Port 2 after configuring the ADC Control Regis-
ters. The direction of each of the eight Port 2 I/O lines can
be configured individually (Figure 11).
In addition, all four versions of the device provide the ca-
pability of connecting 10K (20%) pull-up resistors to each
of the Port 2 I/O lines individually. The pull-ups are con-
nected when activated through software control of P2RES
register (Figure 67) when the corresponding Port 2 pin is
configured to be an input. The pull-up resistor of a Port 2
I/O line is automatically disabled when the corresponding
I/O is an output, regardless of the state of the correspond-
ing P2RES bit value.
Note: The Z86C83/C84 Emulator does not emulate the
P2RES Register. Selection of the pull-ups are done via
jumper settings on the emulator.
Figure 11. Port 2 Configuration
Port 2 (I/O)
P27
P26
P25
P24
P23
P22
P21
P20
P2
Analog Mux
Select from
P2RES
ADC0 (Bits 7, 6, 5)
Input_en
/OEN
Data
ADC
10K
Pad
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-25
1
Port 3 (P36-P31) Port 3 is a 6-bit, CMOS-compatible port,
with three fixed inputs (P33-P31) and three fixed outputs
(P34-P36), configured under software control for In-
put/Output, Counter/Timers, interrupt, and port hand-
shake. P31, P32, and P33 are standard CMOS inputs (no
Auto Latches). Pins P34, P35, and P36 are push-pull out-
put lines (Figure 11). Low EMI output buffers can be glo-
bally programmed by the software.
Two on-board comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The an-
alog function is enabled by programming Port 3 Mode
Register (P3M bit 1). For Interrupt functions, Port 3, pin 3
is falling-edge interrupt input. P31 and P32 are program-
mable as rising, falling, or both edge triggered interrupts
(IRQ register bits 6 and bit 7). P33 is the comparator refer-
ence voltage input when in Analog Mode. Access to
Counter/Timers 1 is made through P31 (T
IN
) and P36
(T
OUT
). Handshake lines for Ports 0 and 2 are available on
P31/P36 and P32/P35 (Table 10).
Port 3 also provides the following control functions: hand-
shake for Ports 0 and 2 (/DAV and RDY); three external in-
terrupt request signals (IRQ2-IRQ0); timer input and out-
put signals (T
IN
and T
OUT
).
Auto Latch. The Auto-Latch instruction puts valid CMOS
levels on CMOS inputs that are not externally driven.
Whether this level is 0 or 1, cannot be determined. A valid
CMOS level, rather than a floating node, reduces exces-
sive supply current flow in the input buffer.
Note: Pins 03, 04, 05, 06 have permanently enabled Auto
Latches.
Comparator Inputs. Port 3, P31 and P32, each have a
comparator front end. The comparator reference voltage,
P33, is common to both comparators. In analog mode, the
P33 input functions as a reference voltage to the compar-
ators. In Analog Mode, the internal P33 register and its cor-
responding IRQ1 is connected to the Stop-Mode Recovery
source selected by the SMR register. In this mode, any of
the Stop-Mode Recovery sources are used to toggle the
P33 bit or generate IRQ1. In Digital Mode, P33 can be
used as a Port 3 register input or IRQ1 source. P34 out-
puts the comparator outputs by software programming the
PCON Register bit D0 to 1.
Note: When enabling/or disabling the analog mode, the
following is recommended:
1.
allow two NOP delays before reading the comparator
output
2.
disable interrupts, switch to analog mode, clear
interrupts, and then re-enable interrupts.
Table 10. Port 3 Pin Assignments
Pin
I/O
CTC1
Analog
Int.
P0 HS P2 HS
P31 IN
T
IN
AN1
IRQ2
D/R
P32 IN
AN2
IRQ0 D/R
P33 IN
REF
IRQ1
P34 OUT
AN1-OUT
P35 OUT
R/D
P36 OUT
T
OUT
R/D
Notes:
HS = Handshake Signals
D = /DAV
R = RDY
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-26
P R E L I M I N A R Y
DS97DZ80700
PIN FUNCTIONS (Continued)
Figure 12. Port 3 Input Configuration
Port 3 (I/O)
Port 3
P36
P35
P34
P33
P32
P31
D1
R247 = P3M
P31 (AN1)
P32 (AN2)
P33 (REF)
From Stop-Mode Recovery
Source
1 = Analog
0 = Digital
IRQ2, T
IN
, P31 Data Latch
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
DIG.
AN
+
-
+
-
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-27
1
Port Configuration Register (PCON). The PCON config-
ures the ports individually for comparator output on Port 3.
The PCON Register is located in the Expanded Register
File at Bank F, location 00 (Figure 13).
Bit 0 multiplexes comparator AN1 Output at P34. A "1" in
this location brings the comparator output to P34
(Figure 14), and a "0" puts P34 into its standard I/O config-
uration.
Note: Only comparator output AN1 is multiplexed to a
Port 3 output. Comparator AN2 output is not connected to
any pins. Note that the PCON Register is reset upon the
occurrence of a WDT RESET (not in STOP Mode), and
Power-On Reset (POR).
Figure 13. Port Configuration Register (PCON) (Write-Only)
Figure 14. Port 3 P34 Output Configuration
D7
D6
D5
D4
D3
D2
D1
D0
Comparator
Output Port 3
0 P34 Standard Output
*
1 P34 Comparator Output
Reserved (Must be 1)
PCON (F) 00
* Default setting from Stop-Mode Recovery,
Power-On Reset, and any WDT Reset.
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
Reserved (Must be 1)
P34 OUT
P31
+
-
REF (P33)
P34
PAD
PCON
D0
*
Reset Condition
Normal
0 P34 Standard Output
1 P34 Comparator Output
*
AN1
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-28
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION
RESET. (Input, Active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) Reset, or external reset.
During POR, and WDT Reset, the internally generated re-
set is driving the reset pin Low for the POR time. Any de-
vices driving the reset line must be open-drain to
avoid damage from a possible conflict during reset
conditions.
Pull-up is provided internally.
After the POR time, /RESET is a Schmitt-triggered input.
After the reset is detected, an internal RST signal is
latched and held for an internal register count of 18 exter-
nal clocks, or for the duration of the external reset, which-
ever is longer. Program execution begins at location 000C
(hex), 5-10 TpC cycles after the RST is released. For POR,
the reset output time is T
POR
.
Program Memory. C83/C84/E83/E84 can address up to
4 KB of internal Program Memory (Figure 15). The first 12
bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that cor-
respond to the six available interrupts. Bytes 13 to 4095
consist of on-chip, mask-programmed ROM.
ROM Protect. The 4 KB of Program Memory is mask pro-
grammable. A ROM protect feature will prevent dumping
of the ROM contents from an external program outside the
ROM.
Expanded Register File. The register file has been ex-
panded to allow for additional system control registers and
for mapping of additional peripheral devices and input/out-
put ports into the register address area. The Z8 register
address space R0 through R15 is implemented as 16
groups of 16 registers per group (Figure 16). These regis-
ter banks are known as the Expanded Register File (ERF).
Bits 3-0 of the Register Pointer (RP) select the active ERF
bank. Bits 7-4 of register RP select the working register
group (Figure 16). Four system configuration registers re-
side in the ERF address space in Bank F and eight regis-
ters reside in Bank C. The rest of the ERF addressing
space is not physically implemented, and is open for future
expansion.
Note: When using Zilog's Cross Assembler version 2.1 or
earlier, use the LD RP, #0X instruction rather than the SRP
#0X instruction to access the ERF.
Figure 15. Program Memory Map
12
11
10
9
8
7
6
5
4
3
2
1
0
On-Chip
ROM
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IRQ5
2048/4096
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-29
1
Figure 16. Expanded Register File Architecture
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-30
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION (Continued)
Register File. The Register File consists of three I/O port
registers, 237 general-purpose registers, 15 control and
status registers, and four system configuration registers in
the Expanded Register Group (Figure 16). The instruc-
tions can access registers directly or indirectly through an
8-bit address field. This allows a short 4-bit register ad-
dress using the Register Pointer (Figure 18). In the 4-bit
mode, the Register File is divided into 16 working register
groups, each occupying 16 continuous locations. The
Register Pointer (Figure 17) addresses the starting loca-
tion of the active working-register group.
Note: Register Bank E0-EF is only accessed either as
working registers or through indirect addressing modes.
CAUTION: D4 of Control Register P01M (R251) must
be 0.
R254. The C83/C84/E83 has one extra general-purpose
register located at FEH (R254).
Stack. The C83/C84/E83 has an 8-bit Stack Pointer
(R255) used for the internal stack that resides within the
236 general-purpose registers. Register R254 cannot be
used for stack.
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V
CC
voltage-specified operating range. It will
not keep its last state from a V
LV
reset if the V
CC
drops be-
low 1.8V. This includes Register R254.
Note: Register Bank E0-EF is only accessed either as
working register or through indirect addressing modes.
RAM Protect. The upper portion of the RAM's address
spaces %80F to %EF (excluding the control registers) are
protected from writing. The user activates this feature from
the internal ROM code to turn off/on the RAM Protect by
loading either a 0 or 1 into the Interrupt Mask (IMR) regis-
ter, bit D6. A 1 in D6 enables RAM Protect.
Figure 17. Register Pointer Register
D7
D6
D5
D4
D3
D2
D1
D0
Expanded Register Group
Working Register Group
RP
R253
Note: Default Setting After Reset = 00000000
Figure 18. Register Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7
r6
r5
r4
R253
(Register Pointer)
I/O Ports*
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
r3
r2
r1
r0
Register Group 1
Register Group 0*
R15 to R0
R15 to R4*
R3 to R0*
R15 to R0
FF
F0
0F
00
1F
10
2F
20
3F
30
4F
40
5F
50
6F
60
7F
70
* Expanded Register File Bank (0) is selected
in this figure by handling bits D3 to D0 as "0"
in Register R253 (RP).
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-31
1
Counter/Timers. There are two 8-bit programmable
counter/timers (T0-T1), each driven by its own 6-bit pro-
grammable prescaler. The T1 prescaler is driven by inter-
nal or external clock sources; however, the T0 prescaler is
driven by the internal clock only (Figure 19).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When the
counter reaches the end of the count, a timer interrupt re-
quest, IRQ4 (T0) or IRQ5 (T1), is generated.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counters, but not the prescalers, are read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and is either the inter-
nal microprocessor clock divide-by-four, or an external sig-
nal input through Port 3. The Timer Mode register config-
ures the external timer input (P31) as an external clock, a
trigger input that can be retriggerable or non-retriggerable,
or as a gate input for the internal clock. The counter/timers
can be cascaded by connecting the T0 output to the input
of T1. T
IN
Mode is enabled by setting R243 PRE1 Bit D1
to 0.
Figure 19. Counter/Timer Block Diagram
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
16
4
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
2
Clock
Logic
IRQ4
TOUT
P36
IRQ5
Internal Data Bus
Write
Write
Read
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
Write
Read
Internal Data Bus
External Clock
Internal
Clock
D0 (SMR)
4
2
OSC
D1 (SMR)
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-32
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has six different interrupts from six dif-
ferent sources. These interrupts are maskable, prioritized
(Figure 20) and the six sources are divided as follows: four
sources are claimed by Port 3 lines P33-P30, and two in
counter/timers (Table 11). The Interrupt Mask Register
globally or individually enables or disables the six interrupt
requests.
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. An interrupt ma-
chine cycle is activated when an interrupt request is
granted. This action disables all subsequent interrupts,
saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved
for that interrupt.
Figure 20. Interrupt Block Diagram
Table 11. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
Comments
IRQ0
/DAV0, IRQ0
0, 1
External (P32), Rise Fall Edge Triggered
IRQ1,
IRQ1
2, 3
External (P33), Fall Edge Triggered
IRQ2
/DAV2, IRQ2, T
IN
4, 5
External (P31), Rise Fall Edge Triggered
IRQ3
IRQ3
6, 7
By User Software
IRQ4
T0
8, 9
Internal
IRQ5
T1
10, 11
Internal
Interrupt
Edge
Select
IRQ (D6, D7)
IRQ1, 3, 4, 5
IRQ
IMR
IPR
PRIORITY
LOGIC
6
Global
Interrupt
Enable
Vector Select
Interrupt
Request
IRQ0 IRQ2
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-33
1
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge trig-
gered, and are programmable by the user. The software
may poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select is located
in the IRQ Register (R250), bits D7 and D6. The configu-
ration is shown in Table 12.
Clock. The Z8 on-chip oscillator has a high-gain, parallel-
resonant amplifier for connection to a crystal, LC, ceramic
resonator, or any suitable external clock source (XTAL1 =
Input, XTAL2 = Output). The crystal should be AT cut, 16
MHz max., with a series resistance (RS) of less than or
equal to 100 Ohms when clocking from 1 MHz to 16 MHz.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor's recommended capacitor values
from each pin directly to the device Ground pin to reduce
Ground noise injection into the oscillator (Figure 21).
Note: For better noise immunity, the capacitors should be
tied directly to the device Ground pin (V
SS
).
Table 12. IRQ Register
IRQ
Interrupt Edge
D7
D6
P31
P32
0
0
F
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Figure 21. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator or
Crystal
C1, C2 = 22 pF TYP *
f = 8 MHz
LC
External Clock
L
* Preliminary value including pin parasitics
* * Device ground pin
VSS* *
VSS* *
VSS* *
VSS* *
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-34
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION (Continued)
Analog-to-Digital Converter
The Analog-to-Digital (ADC) is an 8-bit half flash converter
that uses two reference resistor ladders for its upper 4 bits
(MSBs) and lower 4 bits (LSBs) conversion. Two reference
voltage pins, AV
CC
and A
GND
, are provided for external
reference voltage supplies. During the sampling period
from one of the eight channel inputs, the converter is also
being auto-zeroed before starting the conversion. The
conversion time is dependent on the internal clock fre-
quency. The minimum conversion time is 35 x SCLK (see
Figure 22).
The ADC is controlled by the Z8 and its three registers (two
Control and one Result) are mapped into the Extended
Register File. A conversion can be initiated by writing to
the ADC Control Register 0 after the ADC Control Register
1 is configured.
The start command is implemented in such a way as to be-
gin a conversion at any time, if a conversion is in progress
and a new start command is received, then the conversion
in progress will be aborted and a new conversion will be
initiated. This allows the programmed values to be
changed without affecting a conversion-in-progress. The
new values will take effect only after a new start command
is received.
The ADC can be disabled (for low power) or enabled by a
Control Register bit.
Though the ADC will function for a smaller input voltage
and voltage reference, the noise and offsets remain con-
stant over the specified electrical range. The errors of the
converter will increase and the conversion time may also
take slightly longer due to smaller input signals.
ADC Calibration Offset
Specially matched resistors are program-enabled to allow
35 percent or 50 percent offset from A
GND
. They may se-
lectively enable these resistors to offset the A
GND
by 50
percent (2.5V to 5V) or 35 percent (1.75V to 5V) thereby
allowing the 8-bit ADC across a narrower voltage range.
This will allow significant resolution improvement within
the reduced voltage range.
Note: The AV
CC
must be the same value as V
CC
and
A
GND
must be the same value as GND.
Figure 22. ADC Architecture
Start
Converter
A/D
Control
Reg.
8
8
8
A/D
Result
Reg.
A/D
Converter
AV
CC
A
GND
A/D
Control
Reg.
8
Selected Channel
EXT
Sample
and Hold
ADC Register 9
D4, D5
4
Calibration Offset
ADC0
ADR1
ADC1
Vref + VCC
Vref- GND
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-35
1
Channel Select (bits 2, 1, 0)
* Default after reset
ADE (bit 7). A zero powers down and disables power and
any A/D conversions or accessing any ADC registers ex-
cept writing to ADE bit. A one Enables all ADC accesses.
ADC result register is shown in Figure 25.
Figure 23. ADC Control Register 0 (Read/Write)
SCAN
0
No action*
1
Convert channel then stop
CSEL2
CSEL1
CSEL0
Channel
0
0
0
0 (P20)*
0
0
1
1 (P21)
0
1
0
2 (P22)
0
1
1
3 (P23)
1
0
0
4 (P24)
1
0
1
5 (P25)
1
1
0
6 (P26)
1
1
1
7 (P27)
Note: ADCO D4 must equal 1 to allow Port bit as ADC input.
Figure 24. ADC Control Register 1 (Read/Write)
D7
D6
D5
D4
D3
D2
D1 D0
CSEL0
CSEL1
CSEL2
ADC0 (A) Bank C, Register 8
SCAN
0 = No action*.
1 = Convert, then stop.
A
IN
/Input/Output Control
0 = No action*
1 = Enable selected channel
(D
2
,D
1
,D
0
) as analog input
on associated Port 20-27
Must be D7 = 0
D6 = 0
D5 = 1
* Default after reset
D7
D6
D5
D4 D3
D2
D1
D0
ADC1 Bank C, Register 9
ADE
0 Disable*
1 Enable
Must be 0.
D5 D4
0 0 50 % AGND Offset
1 0 35% AGND Offset
0 1 Reserved
1 1 No Offset
Reserved (Must be 1)
* Default after reset
Figure 25. Result Register (Read-Only)
Figure 26. Bank C
Data
D7 D6
D5
D4
D3
D2
D1
D0
ADR Bank C, Register A
Reg F
Reg E
Reg D
Reg C
Reg B
Reg A
Reg 9
Reg 8
AD Control 0
Reg 7
Reg 6
Reg 5
Reg 4
Reg 3
Reg 2
Reg 1
Reg 0
AD Control 1
AD Result 1
These registers
can be accessed.
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-36
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION (Continued)
Figure 27 shows the input circuit of the ADC. When con-
version starts the analog input voltage is connected to the
MSB and LSB flash converter inputs as shown in the Input
Impedance CKT diagram. Effectively, shunting 31 parallel
internal resistance of the analog switches and simulta-
neously charging 31 parallel 0.5 pF capacitors, which is
equivalent to seeing a 400 Ohms input impedance in par-
allel with a 16 pF capacitor. Other input stray capacitance
adds about 10 pF to the input load. For input source resis-
tances up to 2 Kohms can be used under normal operating
condition without any degradation of the input settling time.
For larger input source resistance, increasing conversion
cycle time or adding a capacitor to the input may be re-
quired to compensate the input settling time problem.
Typical Z8 A/D Conversion Sequence
3.
Set the register pointer to Extended Bank (C), that is,
SRP #%0C instruction.
4.
Next, set ADE flag by loading ADC1 Control Register
Bank (C) Register 9, bit 7. Also, load bits 0-4 of this
same register to select a AV
CC
or A
GND
offset value. A
precision voltage divider connected to the A/D
resistive ladder can offset conversion dynamic range
to specified limits within the AV
CC
and A
GND
limits. By
loading Bank (C) Register 9, bits 0-4, with the
appropriate value it is possible to select from these
groups:
a.
No Offset. The Converter Dynamic range is from
0V to 5.0V for AV
CC
= 5.0V.
b.
35 Percent A
GND
Offset. The Converter Dynamic
range is 1.75V - 5.0V for AV
CC
= 5.0V.
c.
50 Percent A
GND
Offset. The Converter Dynamic
range is 2.5V - 5.0V for AV
CC
= 5.0V.
5.
Select one of the eight A/D inputs for conversion by
loading Bank (C) Register 8 with the desired attributes:
Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D
conversion (or digital port I/O).
6.
Set Bank (C) Register 8, bit 3 to enable A/D
conversion. (This flag can be set concurrently with
step 3.) This flag is automatically reset when the A/D
conversion is completed, so a bit test can be
performed to determine A/D readiness if necessary.
7.
Read the A/D result in Bank (C) Register A. Please
note that the A/D result is not valid (indeterminate)
unless ADE flag (Register 9, bit 7) was previously set,
otherwise A/D converter output is tri-stated.
Figure 27. Input Impedance of ADC
CMOS Switch
on Resistance
2 - 5 k
C Parasitic
R Source
C .5 pF
V Ref
C .5 pF
C .5 pF
31 CMOS Digital
Comparators
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-37
1
Digital-to-Analog Converters
The Z86C84 has two Digital-to-Analog Converters
(DACs). Each DAC is an 8-bit resistor string, with a pro-
grammable 0.25X, 0.5X, or 1X gain output buffer. The
DAC output voltage settles after the internal data is latched
into the DAC Data register. The top and bottom ends of the
resistor ladder are register-selected to be connected to ei-
ther the analog supply rails, AV
CC
and A
GND
, or two exter-
nally-provided reference voltages, VDHI and VDLO. Exter-
nal references are recommended to explicitly set the DAC
output limits. Since the gain stage cannot drive to the sup-
ply rails, VDHI and VDLO must be within ranges shown in
the specifications. If either reference approaches the ana-
log supply rails, the output will be unable to span the refer-
ence voltage range. The externally provided reference
voltages should not exceed the supply voltages. The DAC
outputs are latch-up protected and can drive output loads
(Figure 28).
Note: The AV
CC
must be the same value as V
CC
and
A
GND
must be the same value as GND
Figure 28. DAC Block Diagram
Programmable
Gain
Data
Bus
8-Bit
Resistor
Ladder
8
8
DACn
Data
Register
DACRn
Control
Register
8
Analog
+
-
AVCC
DAC1
or
DAC2
* Bits 0, 1
AGND
PAD
PAD
VDLO
High
PAD
VDHI
Note:
* DACRn Control Register Bits
Low
(n = 1 or 2)
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-38
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION (Continued)
The D/A conversion for DAC1 is driven by writing 8-bit data
to the DAC1 data register (Bank C, Register 06H). The
D/A conversion for DAC2 is controlled by the DAC2 data
register (Bank C, Register 07H). Each DAC data register
is initialized to midrange 80H on power-up.
There are two DAC control registers: DACR1 (Bank C,
Register 04H) for DAC1, and DACR2 (Bank C, Register
05H) for DAC2. Control register bits 0 and 1 set the DAC
gain. When DAC data is 80H, the DAC output is constant
for any gain setting (Figure 29 and Figure 31).
Figure 29. D/A 1 Control Register
Figure 30. D/A 1 Data Register
D7
D6
D5
D4
D3
D2
D1
D0
DAC1 Gain
0 0 1 X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DACR1 Bank C, Register 4
DAC1 Enable
0 Disable
1 Enable
Reserved (Must be 0)
D7
D6
D5
D4
D3
D2
D1
D0
DAC1 Bank C, Register 6
0 = Low Level
1 = High Level
Figure 31. D/A 2 Control Register
Figure 32. D/A 2 Data Register
D7
D6
D5
D4 D3
D2
D1
D0
DAC2 Gain
0 0 1 X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DACR2 Bank C, Register 5
DAC2 Enable
(Must be 0 for C83)
0 Disable
1 Enable
Reserved (Must be 0)
D7
D6
D5
D4
D3
D2
D1
D0
DAC2 Bank C, Register 7
0 = Low Level
1 = High Level
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-39
1
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator or by the XTAL oscillator is
used for the POR timer function. The POR time allows V
CC
and the oscillator circuit to stabilize before instruction exe-
cution begins. The POR timer circuit is a one-shot timer
triggered by one of three conditions:
s
Power Fail to Power OK Status
s
Stop-Mode Recovery (If D5 of SMR Register = 1)
s
WDT Time-Out (Including from STOP Mode)
The POR time is T
POR
minimum. Bit 5 of the STOP Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock and
LC oscillators with fast start up time).
HALT. Turns off the internal CPU clock but not the XTAL
oscillation. The counter/timers and external interrupts
IRQ0, IRQ1, and IRQ2 remain active. The device is recov-
ered by interrupts, either externally or internally generated
(a POR or a WDT time-out). An interrupt request must be
executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction
after the HALT. In case of a POR or a WDT time-out, pro-
gram execution will restart at address 000CH.
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 A (typical) or less. The STOP Mode is terminated by
a reset of either WDT time-out, POR, or Stop-Mode Re-
covery. This causes the processor to restart the applica-
tion program at address 000CH.
Figure 33. Gain Control on DAC
3.5
3.05
2.6
2.15
2% accuracy
1.7
1.26
.8
VDLO
0
80H
FFH
3.5V
VDHI
1/4X
1/2X
1X
DAC Output in Volts
2.15
DAC Data Register Value
Notes:
Vcc = 5.0V 10%
VDHI = 3.5V
VDLO = 0.8V
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-40
P R E L I M I N A R Y
DS97DZ80700
In order to enter STOP (or HALT) Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (Opcode = FFH) immediately before the appropri-
ate sleep instruction, that is,
Stop-Mode Recovery (SMR) Register. This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 34 and Figure 35). All bits
are Write-Only, except bit 7, which is Read-Only. Bit 7 is a
flag bit that is hardware set on the condition of STOP re-
covery and reset by a power-on cycle. Bit 6 controls wheth-
er a low level or a high level is required from the recovery
source. Bit 5 controls the reset delay after recovery. Bits 2,
3, and 4, or the SMR Register, specify the source of the
Stop-Mode Recovery signal. Bits 0 and 1 determine the
time-out period of the WDT. The SMR Register is located
in Bank F of the Expanded Register Group at address
0BH. When the Stop-Mode Recovery sources are selected
in this register, then SMR2 Register bits D0,D1 must be set
to 0.
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The con-
trol selectively reduces device power consumption during
normal processor execution (SCLK control) and/or HALT
mode (where TCLK sources counter/timers and interrupt
logic). This bit is reset to D0 = 0 after a Stop-Mode Recov-
ery, WDT Time-out, and POR.
External Clock Divide-by-Two (D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock HALT Mode frequency divided
by two. The SCLK/TCLK is equal to the external clock fre-
quency when this bit is set (D1=1). Using this bit together
with D7 of PCON further helps lower EMI (that is, D7
(PCON) = 0, D1 (SMR) = 1). The default setting is zero.
Maximum external clock frequency is 8 MHz when SMR
Bit D1 = 1 where SCLK/TCLK = XTAL.
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP Mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT Mode
Figure 34. Stop-Mode Recovery Register (Write-Only
Except Bit D7, Which Is Read-Only)
D7
D6 D5
D4
D3
D2
D1
D0
SMR (FH) 0B
SCLK/TCLK Divide-by-16
0 OFF* *
1 ON
Stop-Mode Recovery Source
000 POR Only and/or External Reset*
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON
Stop Recovery Level
0 Low *
1 High
Stop Flag (Read-Only)
0 POR
1 Stop Recovery
Note: Not used in conjunction with SMR2
Source
* Default Setting After RESET
** Default setting after RESET and
Stop-Mode Recovery
*
*
External Clock Divide-by-2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL
Figure 35. Stop-Mode Recovery Register 2
([0F] DH: Write-Only)
Figure 36. SCLK Circuit
D7
D6
D5
D4
D3
D2
D1
D0
SMR2 (0F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
SMR, D0
2
16
OSC
SCLK
TCLK
SMR, D1
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-41
1
Stop-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR register specify the wake-up source
of the STOP recovery (Figure 37 and Table 13). When the
Stop-Mode Recovery Sources are selected in this register
then SMR2 register bits D0,D1 must be set to zero. P33-
P31 and Port 2 cannot wake up from STOP Mode if the in-
put lines are configured as analog inputs to the Analog
comparator or Analog-to-Digital Converter.
Note: If the Port 2 pin is configured as an output, this
output level will be read by the SMR circuitry.
Stop-Mode Recovery Delay Select (D5). This bit, if High,
enables the T
POR
/RESET delay after Stop-Mode Recov-
ery. The default configuration of this bit is "1". A POR or
WDT reset will override the selection and cause the reset
delay to occur.
Stop-Mode Recovery Edge Select (D6). A "1" in this bit
position indicates that a high level on the output to the ex-
clusive Or-Gate input from the selected recovery source
wakes the Z86C83/C84/E83 from STOP Mode. A "0" indi-
cates low-level recovery. The default is 0 on POR. This bit
is used for either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT reset. A "1" in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note: A WDT reset out of STOP Mode will also set this bit
to a "1".
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register Bits D2, D3, and D4 must be 0.
Table 13. Stop-Mode Recovery Source
SMR:432
Operation
D4
D3
D2 Description of Action
0
0
0
POR and/or external reset recovery
0
0
1
Reserved
0
1
0
P31 transition (not in Analog Mode)
0
1
1
P32 transition (not in Analog Mode)
1
0
0
P33 transition (not in Analog Mode)
1
0
1
P27 transition
1
1
0
Logical NOR of P20 through P23
1
1
1
Logical NOR of P20 through P27
Table 14. Stop-Mode Recovery Source
SMR:10
Operation
D1
D0
Description of Action
0
0
POR and/or external reset recovery
0
1
Logical AND of P20 through P23
1
0
Logical AND of P20 through P27
Figure 37. Stop-Mode Recovery Source
P31
P32
P33
P27
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
/RESET
0 1 0
0 1 1
MUX
D4 D3 D2
1 1 0
D4 D3 D2
1 1 1
P20
P23
P20
P27
SMR2
SMR2
P20
P23
P20
P27
VDD
SMR2
VDD
SMR D4 D3 D2
0 0
D1 D0
1
0
D1 D0
D1 D0
1
0
0 0
SMR
SMR
D4 D3 D2
1 0 1
SMR D4 D3 D2
D4 D3 D2
SMR
1 0 0
0
SMR
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-42
P R E L I M I N A R Y
DS97DZ80700
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subse-
quent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 38).
WDT instruction affects the Z (Zero), S (Sign), and V
(Overflow) flags. The WDTMR must be written to within 64
internal system clocks. After that, the WDTMR is write pro-
tected.
Note: WDT time-out while in Stop-Mode will not reset
SMR, PCON, WDTMR, P2M, P3M, Ports 2 and 3 Data
Registers, but will cause the reset delay to occur.
The Power-On Reset (POR) clock source is selected with
bit 4 of the WDTMR. Bits 0 and 1 control a tap circuit that
determines the time-out period. Bit 2 determines whether
the WDT is active during HALT and bit 3 determines WDT
activity during STOP. If bits 3 and 4 of this register are both
set to "1," the WDT is only driven by the external clock dur-
ing STOP Mode. This feature makes it possible to wake up
from STOP Mode from an internal source. Bits 5 through 7
of the WDTMR are reserved (Figure 39). This register is
accessible only during the first 60 processor cycles (60
SCLKs) from the execution of the first instruction after
Power-On-Reset, Watch-Dog Reset or a Stop-Mode Re-
covery. After this point, the register cannot be modified by
any means, intentional or otherwise. The WDTMR cannot
be read and is located in Bank F of the Expanded Register
group at address location 0FH.
Figure 38. Resets and WDT
CLK
18 Clock RESET
Generator
RESET
/Clear
WDT TAP SELECT
On Board
RC OSC.
CK
/CLR
128 SCLK
POR
256
SCLK
512
SCLK
1024
SCLK
4096
SCLK
3.0V Operating
Voltage Det.
Internal
/RESET
WDT Select
(WDTMR)
CK Source
Select
(WDTMR)
XTAL
VCC
VLV
From Stop
Mode
Recovery
Source
/WDT
Stop Delay
Select (SMR D5)
12 ns Glitch Filter
+
-
WDT/POR Counter Chain
M
U
X
/RESET
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-43
1
WDT Time Select (D1, D0). Selects the WDT time-out pe-
riod. It is configured as shown in Table 15.
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT Mode. A "1" indicates
active during HALT. The default is "1".
Note: If WDT is permanently selected (always ON mode),
the WDT will continue to run even if set not to run in STOP
or HALT Mode.
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, unless as specified
below, the on-board RC has to be selected as the clock
source to the POR counter. A "1" indicates active during
STOP. The default is "1". If bits D3 and D4 are both set to
"1", the WDT only, is driven by the external clock during
STOP Mode.
Notes:
1.
If WDT is permanently selected (always ON mode)
using internal on-board RC oscillator, the WDT will
continue to run even if set not to run in STOP or HALT
Mode.
2.
WDT instructions affect the Z (Zero), S (Sign), and V
(Overflow) flags.
On-Board, Power-On-Reset RC or External XTAL1
Oscillator Select (D4).
This bit determines which oscilla-
tor source is used to clock the internal POR and WDT
counter chain. If the bit is a "1", the internal RC oscillator is
bypassed and the POR and WDT clock source is driven
from the external pin, XTAL1. The default configuration of
this bit is 0, which selects the RC oscillator. If the XTAL1
pin is selected as the oscillator source for the WDT, during
STOP Mode, the oscillator will be stopped and the WDT
will not run. This is true even if the WDT is selected to run
during STOP Mode.
V
CC
Voltage Comparator. An on-board Voltage Compar-
ator checks that V
CC
is at the required level to ensure cor-
rect operation of the device. RESET is globally driven if
V
CC
is below the specified voltage (typically 2.6V).
ROM Protect. ROM Protect is mask or OTP bit-program-
mable. It is selected by the customer at the time the ROM
code is submitted.
ROM Mask Selectable Options
There are two ROM mask options that must be selected at
the time the ROM mask is ordered (ROM code submitted)
for the Z86C83/C84 and three Z86E83 OTP bit options.
Figure 39. Watch-Dog Timer Mode Register
(Write Only)
Table 15. WDT Time Select (Min. @ 5.0V)
D1
D0
Time-Out of
Internal RC OSC
Time-Out of
SCLK Clock
0
0
6.25 ms min
256 SCLK
0
1
12.5 ms min
512 SCLK
1
0
25 ms min
1024 SCLK
1
1
100 ms min
4096 SCLK
Note: The minimum time shown is for V
CC
@ 5.0V.
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP
00 256 SCLK
01 512 SCLK
10 1024 SCLK
11 4096 SCLK
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
*
Default setting after RESET
XTAL=SCLK/TCLK shown
*
*
*
Table 16. Selectable Options
Option
Selection
Permanent WDT
Yes/No
ROM Protect
Yes/No
EPROM/TEST Mode Disable*
Yes/No
Note:
*For Z86E83 only
EPROM/TEST Mode Disable - On the Z86E83, the user can per-
manently disable entry into EPROM Mode and TEST Mode
by programming this bit.
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-44
P R E L I M I N A R Y
DS97DZ80700
EXPANDED REGISTER FILE CONTROL REGISTERS (0C)
Figure 40. ADC Control Register 0 (Read/Write)
Figure 41. ADC Control Register 1 (Read/Write)
Figure 42. AD Result Register (Read Only)
D7
D6 D5
D4
D3
D2
D1
D0
ADC0 Bank C, 8H
Scan 0 = No action*
1 = Convert channel then stop
A
IN
/Input/Output Control
0 = No Action (Digital Function)*
1 = Enable Selected Channel
(M
2
, M
1
, M
0
) as analog input on
associated Port P27-P20
Channel Select (bits 2,1,0)
CSEL2
0
0
0
0
1
1
1
1
CSEL1
0
0
1
1
0
0
1
1
CSEL0
0
1
0
1
0
1
0
1
Channel
0*
1
2
3
4
5
6
7
* Default setting after reset.
Must be 0 0 1
D7
D6
D5
D4
D3
D2
D1
D0
ADC1 Bank C, Register 9
ADE
0 Disable*
1 Enable
Must be 0.
D5 D4
0 0 50 % AGND Offset
1 0 35% AGND Offset
0 1 Reserved
1 1 No Offset
Reserved (Must be 1.)
D7 D6
D5
D4
D3 D2
D1
D0
ADR1 Bank C, AH
Data
Figure 43. D/A 1 Control Register
Figure 44. D/A 2 Control Register
Figure 45. D/A 1 Data Register
Figure 46. D/A 2 Data Register
D7
D6
D5
D4
D3
D2
D1
D0
DAC1 Gain
0 0 1 X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DACR1 Bank C, Register 4
DAC1 Enable
(Must be 0 for Z86C83)
0 Disable
1 Enable
Reserved (Must be 0)
D7
D6
D5
D4
D3
D2
D1
D0
DAC2 Gain
0 0 1 X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DACR2 Bank C, Register 5
DAC2 Enable
(Must be 0 for C83)
0 Disable
1 Enable
Reserved (Must be 0)
D7
D6
D5
D4
D3
D2
D1
D0
DAC1 Bank C, Register 6
0 = Low Level
1 = High Level
D7
D6
D5
D4
D3
D2
D1
D0
DAC2 Bank C, Register 7
0 = Low Level
1 = High Level
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-45
1
EXPANDED REGISTER FILE CONTROL REGISTERS
Figure 47. Stop-Mode Recovery Register
(Write-Only, except Bit 7 which is Read-Only)
Figure 48. Watch-Dog Timer Mode Register 2
D7
D6
D5 D4
D3
D2
D1 D0
SMR (F) 0B
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
ST OP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
*
Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
D7
D6
D5 D4
D3
D2
D1
D0
SMR2 (F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
11 Reserved
Figure 49. Watch-Dog Timer Mode Register
(Write-Only)
Figure 50. Port Configuration Register (PCON)
(Write-Only)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP
00 256 SCLK
01 512 SCLK
10 1024 SCLK
11 4096 SCLK
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
*
Default setting after RESET
XTAL=SCLK/TCLK shown
*
*
*
D7 D6
D5
D4
D3
D2 D1
D0
Comparator
Output Port 3
0 P34 Standard Output
*
1 P34 Comparator Output
Reserved (Must be 1)
PCON (F) 00
* Default setting from Stop-Mode Recovery
Power-On Reset, and any WDT Reset.
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
Reserved (Must be 1)
0 = Low EMI OSC
1 = Standard OSC
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-46
P R E L I M I N A R Y
DS97DZ80700
Z8
CONTROL REGISTERS
Figure 51. Reserved
Figure 52. Timer Mode Register (F1
H
: Read/Write)
Figure 53. Counter/Timer 1 Register (F2
H
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0)
R240
D7
D6
D5
D4
D3
D2
D1
D0
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T0
0 No Function
1 Load T1
0 Disable T1 Count
1 Enable T1 Count
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
R241 TMR
D7 D6
D5
D4
D3
D2
D1
D0
T Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T Current Value
(When Read)
1
1
R242 T1
Figure 54. Prescaler 1 Register (F3
H
: Write-Only)
Figure 55. Counter/Timer 0 Register (F4
H
: Read/Write)
Figure 56. Prescaler 0 Register (F5
H
: Write-Only)
Figure 57. Port 3 Mode Register (F7
H
: Write-Only)
D7 D6
D5
D4
D3
D2
D1
D0
Count Mode
0 T1 Single Pass
1 T1 Modulo N
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R243 PRE1
D7 D6 D5
D4 D3
D2 D1 D0
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
R244 T0
0 T0 Single Pass
1 T0 Modulo N
D7
D6 D5
D4 D3 D2
D1 D0
Count Mode
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R245 PRE0
D7 D6
D5 D4
D3 D2
D1
D0
0 Port 2 Open-Drain*
1 Port 2 Push-Pull
Port 3 Inputs
0 Digital*
1 Analog
Reserved (Must be 0)
R247 P3M
*Default Setting After Reset
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-47
1
Figure 58. Port 2 Mode Register (F6
H
: Write-Only)
Figure 59. Port 0 and 1 Mode Register
(F8
H
: Write-Only)
Figure 60. Interrupt Priority Register (F9
H
: Write-Only)
D7
D6
D5
D4
D3
D2
D1
D0
P27- P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
R246 P2M
*Default Setting After Reset
D7
D6 D5
D4
D3
D2
D1
D0
P00-P03 Mode
00 Output
01 Input
1X A11-A8
R248 P01M
Reserved (Must be 1)
Reserved (Must be 0)
P04-P06 Mode
00 Output
01 Input
1X A15-A12
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0)
R249 IPR
Figure 61. Interrupt Request Register
(F
AH
: Read/Write)
Figure 62. Interrupt Mask Register (F
BH
: Read/Write)
Figure 63. Flag Register (F
CH
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = Software Controlled
IRQ4 = T0
IRQ5 = T1
Inter Edge
00 P31
01 P31
10 P31
11 P31
R250 IRQ
Default Setting After Reset = 00H
P32
P32
P32
P32
D7 D6
D5
D4
D3
D2
D1 D0
1 RAM Protect Enabled
0 RAM Protect Disabled *
1 Enables IRQ5-IRQ0
(D0 = IRQ0)
1 Enables Interrupts
0 Disable interrupts
* (Default setting after RESET.)
R251 IMR
D7
D6
D5
D4
D3
D2
D1
D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
R252 Flags
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-48
P R E L I M I N A R Y
DS97DZ80700
Z8 CONTROL REGISTERS (Continued)
Figure 64. Register Pointer (F
DH
: Read/Write)
Figure 65. General-Purpose Register
(F
EH
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
Expanded Register File Pointer
Working Register Pointer
R253 RP
Default Setting After Reset = 00H
D7
D6
D5
D4
D3
D2
D1
D0
R254 GPR
0 = Low Level
1 = High Level
Figure 66. Stack Pointer (F
FH
: Read/Write)
Figure 67. Port 2 Pull-up Register
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Lower
Byte (SP7-SP0)
R255 SPL
0 = Low Level
1 = High Level
D7
D6 D5
D4
D3
D2
D1 D0
Port 2 (P27-P20) 10K Pull-up
0 = Disabled
1 = Enabled
P2RES Bank C, Register 3
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-49
1
PACKAGE INFORMATION
Figure 68. 28-Pin DIP Package Diagram
Figure 69. 28-Pin SOIC Package Diagram
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-50
P R E L I M I N A R Y
DS97DZ80700
PACKAGE INFORMATION (Continued)
Figure 70. 28-Pin PLCC Package Diagram
Z86C83/C84/E83
Zilog
CMOS Z8
MCU
DS97DZ80700
P R E L I M I N A R Y
8-51
1
ORDERING INFORMATION
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
CODES
Package
P = Plastic DIP
S = Plastic SOIC
Temperature
S = 0C to + 70C
E = -40C to +105C
Speed
16 = 16 MHz
Environmental
C = Plastic Standard
Z86C83
16 MHz
Z86E83
16 MHz
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C8316PSC
Z86C8316SSC
Z86C8316VSC
Z86E8316PSC
Z86E8316SSC
Z86E8316VSC
Z86C8316PEC
Z86C8316SEC
Z86C8316VEC
Z86E8316PEC
Z86E8316SEC
Z86E8316VEC
Z86C84
16 MHz
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86C8416PSC
Z86C8416SSC
Z86C8416VSC
Z86C8416PEC
Z86C8416SEC
Z86C8416VEC
Example:
Z 86C83 16 P S C
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
is a Z86C83, 16 MHz, DIP, 0C to +70C, Plastic Standard Flow
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-52
P R E L I M I N A R Y
DS97DZ80700
1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES FROM INTELLECTUAL PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog's products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056