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Электронный компонент: Z86L02E

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DS96DZ80301
P R E L I M I N A R Y
1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86C02/E02/L02
1
C
OST
E
FFECTIVE
, 512-B
YTE
ROM
CMOS Z8
M
ICROCONTROLLERS
FEATURES
s
18-Pin DIP and SOIC Packages
s
0
C to 70
C Standard Temperature
40
C to 105
C Extended Temperature
(Z86C02/E02 only)
s
3.0V to 5.5V Operating Range (Z86C02)
4.5V to 5.5V Operating Range (Z86E02)
2.0V to 3.9V Operating Range (Z86L02)
s
14 Input / Output Lines
s
Five Vectored, Prioritized Interrupts from Five Different
Sources
s
Two On-Board Comparators
s
Software Enabled Watch-Dog Timer (WDT)
s
Programmable Interrupt Polarity
s
Two Standby Modes: STOP and HALT
s
Low-Voltage Protection
s
ROM Mask/OTP Options:
Low-Noise (Z86C02/E02 only)
ROM Protect
Auto Latch
Permanent Watch-Dog Timer (WDT)
RC Oscillator (Z86C02/L02 Only)
32 KHz Operation (Z86C02/L02 Only)
s
One Programmable 8-Bit Counter/Timer with a 6-Bit
Programmable Prescaler
s
Power-On Reset (POR) Timer
s
On-Chip Oscillator that Accepts RC, Crystal, Ceramic
Resonator, LC, or External Clock Drive (C02/L02 only)
s
On-Chip Oscillator that Accepts RC or External Clock
Drive (Z86E02 SL1903 only)
s
On-Chip Oscillator that Accepts Crystal, Ceramic
Resonator, LC, or External Clock Drive (Z86E02 only)
s
Clock-Free WDT Reset
s
Low-Power Consumption (50mw)
s
Fast Instruction Pointer (1.5
s @ 8 MHz)
s
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
GENERAL DESCRIPTION
Zilog's Z86C02/E02/L02 microcontrollers (MCUs) are
members of the Z8
single-chip MCU family, which offer
easy software/hardware system expansion.
For applications demanding powerful I/O capabilities, the
MCU's dedicated input and output lines are grouped into
three ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.
One on-chip counter/timer, with a large number of user-se-
lectable modes, off-load the system of administering real-
time tasks such as counting/timing and I/O data communi-
Device
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Auto
Latch
Permanent
WDT
Z86C02
512
61
8
Optional Optional
Z86E02
512
61
8
Optional Optional
Z86L02
512
61
8
Optional Optional
Note:
*General-Purpose
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
Zilog
2
P R E L I M I N A R Y
DS96DZ80301
GENERAL DESCRIPTION
(Continued)
cations. Additionally, two on-board comparators process
analog signals with a common reference voltage (Figure
1).
Note:
All Signals with a preceding front slash, "/", are ac-
tive Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Figure 1. Z86C02/E02/L02 Functional Block Diagram
Port 3
Counter/
Timer
Interrupt
Control
Two Analog
Comparators
Port 2
I/O
(Bit Programmable)
FLAG
Register
Pointer
General-Purpose
Register File
Machine
Timing & Inst.
Control
Program
Memory
Program
Counter
Vcc
GND
XTAL
Port 0
I/O
Input
ALU
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
Zilog
3
P R E L I M I N A R Y
DS96DZ80301
GENERAL DESCRIPTION
(Continued)
PIN DESCRIPTIONS
Figure 2. EPROM Programming Mode Block Diagram
Z8 MCU
Address
Counter
Address MUX
Data MUX
Z8 POR
T2
Option Bits
EPROM
PGM
Mode Logic
D7-D0
D7-D0
D7-D0
A10-A0
A10-A0
A10-A0
3 Bits
Clear
P00
Clock
P01
EPM
P32
/CE
XT1
/PGM
P02
VPP
P33
/OE
P31
Figure 3. 18-Pin Standard Mode Configuration
1
2
9
3
4
5
6
7
8
18
17
16
15
14
13
12
11
10
P23
P22
P33
P21
P20
GND
P02
P01
P00
P24
P25
P32
P26
P27
Vcc
XTAL2
XTAL1
P31
Standard Mode
Table 1. 18-Pin Standard Mode Identification
Pin #
Symbol
Function
Direction
1-4
P24-P27
Port 2, Pins 4, 5, 6, 7
In/Output
5
V
CC
Power Supply
6
XTAL2
Crystal Oscillator
Clock
Output
7
XTAL1
Crystal Oscillator
Clock
Input
8
P31
Port 3, Pin 1, AN1
Input
9
P32
Port 3, Pin 2, AN2
Input
10
P33
Port 3, Pin 3, REF
Input
11-13
P00-P02
Port 0, Pins 0, 1, 2
In/Output
14
GND
Ground
15-18
P20-P23
Port 2, Pins 0, 1, 2, 3
In/Output
Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
4
1
Figure 4. 18-Pin EPROM Mode Configuration
Table 2. 18-Pin EPROM Mode Identification
Pin #
Symbol
Function
Direction
1-4
D4-D7
Data 4, 5, 6, 7
In/Output
5
Vcc
Power Supply
6
NC
No Connection
7
/CE
Chip Enable
Input
8
/OE
Output Enable
Input
9
EPM
EPROM Program
Mode
Input
10
VPP
Program Voltage
Input
11
Clear
Clear Clock
Input
12
Clock
Address
Input
13
/PGM
Program Mode
Input
14
GND
Ground
15-18
D0-D3
Data 0, 1, 2, 3
In/Output
1
2
9
3
4
5
6
7
8
18
17
16
15
14
13
12
11
10
D3
D2
VPP
D1
D0
GND
/PGM
CLOCK
CLEAR
D4
D5
EPM
D6
D7
Vcc
N/C
/CE
/OE
EPROM Mode
Figure 5. 18-Pin SOIC Configuration
Table 3. 18-Pin SOIC Pin Identification
Standard Mode
Pin #
Symbol
Function
Direction
1-4
P24-P27
Port 2, Pins
4,5,6,7
In/Output
5
Vcc
Power Supply
6
XTAL2
Crystal Osc. Clock
Output
7
XTAL1
Crystal Osc. Clock
Input
8
P31
Port 3, Pin 1, AN1
Input
9
P32
Port 3, Pin 2, AN2
Input
10
P33
Port 3, Pin 3, REF
Input
11-13
P00-P02
Port 0, Pins 0,1,2
In/Output
14
GND
Ground
15-18
P20-P23
Port 2, Pins
0,1,2,3
In/Output
1
18
P24
P27
VCC
XTAL2
XTAL1
P31
P32
P23
P22
P21
P20
GND
P02
P01
P00
P33
P25
P26
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
5
1
ABSOLUTE MAXIMUM RATINGS
Notes:
Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation of
the device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
Total power dissipation should not exceed 462 mW for the
package. Power dissipation is calculated as follows:
1.
This applies to all pins except where otherwise noted.
2.
Maximum current into pin must be
600
A.
There is no input protection diode from pin to V
DD
.
3.
This excludes Pin 6 and Pin 7.
4.
Device pin is not at an output Low state.
Total Power dissipation = V
DD
x [I
DD
(sum of I
OH
)] + sum of [(V
DD
V
OH
) x I
OH
] + sum of (V
0L
x I
0L
)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 6).
CAPACITANCE
T
A
= 25
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Min
Max
Units
Ambient Temperature under Bias
40
+105
C
Storage Temperature
65
+150
C
Voltage on any Pin with Respect to V
SS
[Note 1]
0.7
+12
V
Voltage on V
DD
Pin with Respect to V
SS
0.3
+7
V
Voltage on Pin 7 with Respect to V
SS
[Note 2] (Z86C02/L02)
0.7
V
DD
+1
V
Voltage on Pin 7,8,9,10 with Respect to V
SS
[Note 2] (Z86E02)
0.7
V
DD
+1
V
Total Power Dissipation
462
mW
Maximum Allowed Current out of V
SS
300
mA
Maximum Allowed Current into V
DD
270
mA
Maximum Allowed Current into an Input Pin [Note 3]
600
+600
A
Maximum Allowed Current into an Open-Drain Pin [Note 4]
600
+600
A
Maximum Allowed Output Current Sinked by Any I/O Pin
20
mA
Maximum Allowed Output Current Sourced by Any I/O Pin
20
mA
Maximum Allowed Output Current Sinked by Port 2, Port 0
80
mA
Maximum Allowed Output Current Sourced by Port 2, Port 0
80
mA
Figure 6. Test Load Diagram
From Output
Under Test
150 pF
Parameter
Min
Max
Input capacitance
0
15 pF
Output capacitance
0
20 pF
I/O capacitance
0
25 pF
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
Zilog
6
P R E L I M I N A R Y
DS96DZ80301
DC ELECTRICAL CHARACTERISTICS
Z86C02
T
A
= 40
C to +105
C
T
A
= 0
C to +70
C
Typical
Sym.
Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
V
CH
Clock Input High
Voltage
3.0V
0.8 V
CC
V
CC
+0.3
1.7
V
Driven by External
Clock Generator
5.5V
0.8 V
CC
V
CC
+0.3
2.8
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
3.0V
V
SS
0.3
0.2 V
CC
0.8
V
Driven by External
Clock Generator
5.5V
V
SS
0.3
0.2 V
CC
1.7
V
Driven by External
Clock Generator
V
IH
Input High Voltage
3.0V
0.7 V
CC
V
CC
+0.3
1.8
V
[1]
5.5V
0.7 V
CC
V
CC
+0.3
2.8
V
[1]
V
IL
Input Low Voltage
3.0V
V
SS
0.3
0.2 V
CC
0.8
V
[1]
5.5V
V
SS
0.3
0.2 V
CC
1.5
V
[1]
V
OH
Output High Voltage
3.0V
V
CC
0.4
3.0
V
I
OH
= 2.0 mA
[5]
5.5V
V
CC
0.4
4.8
V
I
OH
= 2.0 mA
[5]
3.0V
V
CC
0.4
3.0
V
Low Noise @
I
OH
= 0.5 mA
5.5V
V
CC
0.4
4.8
V
Low Noise @
I
OH
= 0.5 mA
V
OL1
Output Low Voltage
3.0V
0.8
0.2
V
I
OL
= +4.0 mA
[5]
5.5V
0.4
0.1
V
I
OL
= +4.0 mA
[5]
3.0V
0.8
0.2
V
Low Noise @
I
OL
= 1.0 mA
5.5V
0.4
0.1
V
Low Noise @
I
OL
= 1.0 mA
V
OL2
Output Low Voltage
3.0V
1.0
0.8
V
I
OL
= +12 mA
[5]
5.5V
0.8
0.3
V
I
OL
= +12 mA
[5]
V
OFFSET
Comparator Input
Offset Voltage
3.0V
25
10
mV
5.5V
25
10
mV
V
LV
V
CC
Low Voltage
Auto Reset
V
2.2
2.8
2.6
V
[9]
2.0
3.0
2.6
V
[10]
I
IL
Input Leakage
(Input Bias Current
of Comparator)
3.0V
1.0
1.0
A
V
IN
= 0V, V
CC
5.5V
1.0
1.0
A
V
IN
= 0V, V
CC
I
OL
Output Leakage
3.0V
1.0
1.0
A
V
IN
= 0V, V
CC
5.5V
1.0
1.0
A
V
IN
= 0V, V
CC
V
VICR
Comparator Input
Common Mode
Voltage Range
V
SS
0.3
V
CC
1.0
V
[9]
V
SS
0.3
V
CC
1.5
V
[10]
Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
7
1
DC CHARACTERISTICS
Z86C02
T
A
= 40
C to+105
C
T
A
= 0
C to +70
C
Typical
Sym. Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
I
CC
Supply Current
3.0V
3.5
1.5
mA
@ 2 MHz
[5,6,7]
5.5V
7.0
3.8
mA
@ 2 MHz
[5,6,7]
3.0V
8.0
3.0
mA
@ 8 MHz
[5,6,7]
5.5V
11.0
4.4
mA
@ 8 MHz
[5,6,7]
I
CC1
Standby Current (Halt Mode)
3.0V
2.5
0.7
mA
@ 2 MHz
[5,6,7]
5.5V
4.0
2.5
mA
@ 2 MHz
[5,6,7]
3.0V
4.0
1.0
mA
@ 8 MHz
[5,6,7]
5.5V
5.0
3.0
mA
@ 8 MHz
[5,6,7]
I
CC
Supply Current (Low Noise Mode)
3.0V
3.5
1.5
mA
@ 1 MHz
[5,6,7]
5.5V
7.0
3.8
mA
@ 1 MHz
[5,6,7]
3.0V
5.8
2.5
mA
@ 2 MHz
[5,6,7]
5.5V
9.0
4.0
mA
@ 2 MHz
[5,6,7]
3.0V
8.0
3.0
mA
@ 4 MHz
[5,6,7]
5.5V
11.0
4.4
mA
@ 4 MHz
[5,6,7]
I
CC1
Standby Current
(Low Noise Halt Mode)
3.0V
2.5
0.7
mA
@ 1 MHz
[6,7,8]
5.5V
4.0
2.5
mA
@ 1 MHz
[6,7,8]
3.0V
3.0
0.9
mA
@ 2 MHz
[6,7,8]
5.5V
4.5
2.8
mA
@ 2 MHz
[6,7,8]
3.0V
4.0
1.0
mA
@ 4 MHz
[6,7,8]
5.5V
5.0
3.0
mA
@ 4 MHz
[6,7,8]
I
CC2
Standby Current (Stop Mode)
3.0V
10
1.0
A
[6,7,8,9]
3.0V
20
1.0
A
[6,7,8,10]
5.5V
10
1.0
A
[6,7,8,9]
5.5V
20
1.0
A
[6,7,8,10]
I
ALL
Auto Latch Low Current
3.0V
12
3.0
A
0V < V
IN
< V
CC
5.5V
32
16
A
0V < V
IN
< V
CC
I
ALH
Auto Latch High Current
3.0V
8
-1.5
A
0V < V
IN
< V
CC
5.5V
16
-8.0
A
0V < V
IN
< V
CC
Notes:
1. ort 0, 2, and 3 only.
2. V
SS
= 0V = GND.
3. The device operates down to V
LV
The minimum operational V
CC
is determined on the value of the voltage
V
LV
at the ambient temperature.
4. V
CC
= 3.0V to 5.5V, typical values measured at V
CC
= 3.3V and V
CC
= 5.0V.
5. Standard mode (not Low EMI mode).
6. Inputs at V
CC
or V
SS
, outputs unloaded.
7. Halt mode and Low EMI mode.
8. WDT not running.
9. T
A
= 0C to 70C.
10. T
A
= 40C to 105C.
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
Zilog
8
P R E L I M I N A R Y
DS96DZ80301
DC CHARACTERISTICS
Z86L02
T
A
= 0
C to +70
C
Typical
Sym.
Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
V
CH
Clock Input High
Voltage
2.0V
0.9 V
CC
V
CC
+0.3
V
Driven by External
Clock Generator
3.9V
0.9 V
CC
V
CC
+0.3
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
2.0V
V
SS
0.3
0.1 V
CC
V
Driven by External
Clock Generator
3.9V
V
SS
0.3
0.1 V
CC
V
Driven by External
Clock Generator
V
IH
Input High Voltage
2.0V
0.9 V
CC
V
CC
+0.3
V
[1]
3.9V
0.9 V
CC
V
CC
+0.3
V
[1]
V
IL
Input Low Voltage
2.0V
V
SS
0.3
0.1 V
CC
V
[1]
3.9V
V
SS
0.3
0.1 V
CC
V
[1]
V
OH
Output High Voltage
2.0V
V
CC
0.4
3.0
V
I
OH
= 500
A
[5]
3.9V
V
CC
0.4
3.0
V
I
OH
= 500
A
[5]
V
OL1
Output Low Voltage
2.0V
0.8
0.2
V
I
OL
= +1.0 mA
[5]
3.9V
0.4
0.1
V
I
OL
= +1.0 mA
[5]
V
OL2
Output Low Voltage
2.0V
1.0
0.8
V
I
OL
= + 3.0 mA
[5]
3.9V
0.8
0.3
V
I
OL
= + 3.0 mA
[5]
V
OFFSET
Comparator Input
Offset Voltage
2.0V
25
10
mV
3.9V
25
10
mV
V
LV
V
CC
Low Voltage
Auto Reset
1.4
2.15
V
I
IL
Input Leakage
(Input Bias Current
of Comparator)
2.0V
1.0
1.0
A
V
IN
= 0V, V
CC
3.9V
1.0
1.0
A
V
IN
= 0V, V
CC
I
OL
Output Leakage
2.0V
1.0
1.0
A
V
IN
= 0V, V
CC
3.9V
1.0
1.0
A
V
IN
= 0V, V
CC
V
VICR
Comparator Input
Common Mode
Voltage Range
V
SS
0.3
V
CC
1.0
V
Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
9
1
T
A
= 0
C to +70
C
Typical
Sym Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
I
CC
Supply Current
2.0V
3.3
mA
@ 2 MHz
[5,6]
3.9V
6.8
mA
@ 2 MHz
[5,6]
2.0V
6.0
mA
@ 8 MHz
[5,6]
3.9V
9.0
mA
@ 8 MHz
[5,6]
I
CC1
Standby Current (Halt Mode)
2.0V
2.3
mA
@ 2 MHz
[5,6,7]
3.9V
3.8
mA
@ 2 MHz
[5,6,7]
2.0V
3.8
mA
@ 8 MHz
[5,6,7]
3.9V
4.8
mA
@ 8 MHz
[5,6,7]
I
CC2
Standby Current (Stop Mode)
2.0V
10
1.0
A
[6,7]
3.9V
10
1.0
A
[6,7]
I
ALL
Auto Latch Low Current
2.0V
12
3.0
A
0V < V
IN
< V
CC
3.9V
32
16
A
0V < V
IN
< V
CC
I
ALH
Auto Latch High Current
2.0V
8
-1.5
A
0V < V
IN
< V
CC
3.9V
16
-8.0
A
Notes:
1. Port 0, 2, and 3 only
2. V
SS
= 0V = GND.The device operates down to V
LV
. The minimum operational V
CC
is determined by the value of the voltage V
LV
at the ambient temperature.
3. V
CC
= 2.0V to 3.9V, typical values measured at V
CC
= 3.3 V.
4. Standard Mode (not Low EMI mode).
5. Inputs at V
CC
or V
SS
, outputs are unloaded.
6. WDT is not running.
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
DC CHARACTERISTICS
Z86E02
T
A
= 40
C to +105
C
T
A
= 0
C to +70
C
Typical
Sym.
Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
V
CH
Clock Input High
Voltage
4.5V
0.8 V
CC
V
CC
+0.3
2.8
V
Driven by External
Clock Generator
5.5V
0.8 V
CC
V
CC
+0.3
2.8
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
4.5V
V
SS
0.3
0.2 V
CC
1.7
V
Driven by External
Clock Generator
5.5V
V
SS
0.3
0.2 V
CC
1.7
V
Driven by External
Clock Generator
V
IH
Input High Voltage
4.5V
0.7 V
CC
V
CC
+0.3
2.8
V
5.5V
0.7 V
CC
V
CC
+0.3
2.8
V
V
IL
Input Low Voltage
4.5V
V
SS
0.3
0.2 V
CC
1.5
V
5.5V
V
SS
0.3
0.2 V
CC
1.5
V
V
OH
Output High Voltage
4.5V
V
CC
0.4
4.8
V
I
OH
= 2.0 mA
[5]
5.5V
V
CC
0.4
4.8
V
I
OH
= 2.0 mA
[5]
4.5V
V
CC
0.4
4.8
V
Low Noise @
I
OH
= 0.5 mA
5.5V
V
CC
0.4
4.8
V
V
OL1
Output Low Voltage
4.5V
0.4
0.1
V
I
OL
= +4.0 mA
[5]
5.5V
0.4
0.1
V
I
OL
= +4.0 mA
[5]
4.5V
0.4
0.1
V
Low Noise @
I
OL
= 1.0 mA
5.5V
0.4
0.1
V
Low Noise @
I
OL
= 1.0 mA
V
OL2
Output Low Voltage
4.5V
1.0
0.8
V
I
OL
= +12 mA
[5]
5.5V
1.0
0.8
V
I
OL
= +12 mA
[5]
V
OFFSET
Comparator Input
Offset Voltage
4.5V
25
10
mV
5.5V
25
10
mV
V
LV
V
CC
Low Voltage
Auto Reset
2.6
3.3
3.0
V
[9]
2.2
3.6
3.0
V
[10]
I
IL
Input Leakage (Input
Bias Current of
Comparator)
4.5V
1.0
1.0
A
V
IN
= 0V, V
CC
5.5V
1.0
1.0
A
V
IN
= 0V, V
CC
I
OL
Output Leakage
4.5V
1.0
1.0
A
V
IN
= 0V, V
CC
5.5V
1.0
1.0
A
V
IN
= 0V, V
CC
V
VICR
Comparator Input
Common Mode
Voltage Range
V
SS
0.3
V
CC
1.0
V
[9]
V
SS
0.3
V
CC
1.5
V
[10]
Z86C02/E02/L02
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11
1
T
A
= 40
C to +105
C
T
A
= 0
C to +70
C
Typical
Sym. Parameter
V
CC
[4]
Min
Max
@ 25
C
Units
Conditions
Notes
I
CC
Supply Current
4.5V
9.0
3.8
mA
@ 2 MHz
[5,6]
5.5V
9.0
3.8
mA
@ 2 MHz
[5,6]
4.5V
15.0
4.4
mA
@ 8 MHz
[5,6]
5.5V
15.0
4.4
mA
@ 1 MHz
[5,6]
I
CC1
Standby Current (HALT mode)
4.5V
4.0
2.5
mA
@ 2 MHz
[5,6]
5.5V
4.0
2.5
mA
@ 2 MHz
[5,6]
4.5V
5.0
3.0
mA
@ 4 MHz
[5,6]
5.5V
5.0
3.0
mA
@ 4 MHz
[5,6]
I
CC
Supply Current (Low Noise
Mode)
4.5V
9.0
3.8
mA
[6]
5.5V
9.0
3.8
mA
[6]
4.5V
11.0
4.0
mA
@ 2 MHz
[6]
5.5V
11.0
4.0
mA
@ 2 MHz
[6]
4.5V
15.0
4.4
mA
@ 4 MHz
[6]
5.5V
15.0
4.4
mA
@ 4 MHz
[6]
I
CC1
Standby Current (Low Noise
Halt Mode)
4.5V
4.0
2.5
mA
@ 1 MHz
[6,7,8]
5.5V
4.0
2.5
mA
@ 1 MHz
[6,7,8]
4.5V
4.5
2.7
mA
@ 2 MHz
[6,7,8]
5.5V
4.5
2.7
mA
@ 2 MHz
[6,7,8]
4.5V
5.0
3.0
mA
@ 4 MHz
[6,7,8]
5.5V
5.0
3.0
mA
@ 4 MHz
[6,7,8]
I
CC2
Standby Current (Stop Mode)
4.5V
10
1.0
A
[6,7,9]
4.5V
20
1.0
A
[6,7,10]
5.5V
10
1.0
A
[6,7,9]
5.5V
20
1.0
A
6,7,10]
I
ALL
Auto Latch Low Current
4.5V
32
16
A
0V <V
IN
<V
CC
5.5V
32
16
A
0V <V
IN
<V
CC
ALH
Auto Latch High
4.5V
16
-8.0
A
0V <V
IN
<V
CC
5.5V
16
8.0
A
0V <V
IN
<V
CC
Notes:
1. Port 0, 2, and 3 only.
2. V
SS
= 0V = GND.
3. The device operates down to V
LV
of the specified frequency for V
LV
. The minimum operational V
CC
is determined by the value of
the voltage V
LV
at the ambient temperature.
4. The V
LV
increases as the temperature decreases.
5. V
CC
= 4.5V to 5.5V, typical values measured at V
CC
= 5.0V.
6. Standard mode (not Low EMI mode).
7. Inputs at V
CC
or V
SS
, outputs unloaded.
8. WDT not running.
9. Halt mode and Low EMI mode.
10. T
A
= 0C to 70C.T
A
= 40C to 105C.
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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12
P R E L I M I N A R Y
DS96DZ80301
AC ELECTRICAL CHARACTERISTICS
Figure 7. AC Electrical Timing Diagram
PostScript error (invalidfont, findfont)
Z86C02/E02/L02
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1
AC ELECTRICAL CHARACTERISTICS
Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
T
A
= 40
C to +105
C
T
A
= 0
C to +70
C
8 MHz
No.
Symbol
Parameter
V
CC
Min
Max
Units
Notes
1
TpC
Input Clock Period
2.0V
125
DC
ns
[1]
5.5V
125
DC
ns
[1]
2
TrC,TfC
Clock Input Rise and Fall Times
2.0V
25
ns
[1]
5.5V
25
ns
[1]
3
TwC
Input Clock Width
2.0V
62
ns
[1]
5.5V
62
ns
[1]
4
TwTinL
Timer Input Low Width
2.0V
70
ns
[1]
5.5V
70
ns
[1]
5
TwTinH
Timer Input High Width
2.0V
5TpC
[1]
5.5V
5TpC
[1]
6
TpTin
Timer Input Period
2.0V
8TpC
[1]
5.5V
8TpC
[1]
7
TrTin,
TtTin
Timer Input Rise and Fall Time
2.0V
100
ns
[1]
5.5V
100
ns
[1]
8
TwIL
Int. Request Input Low Time
2.0V
70
ns
[1,2,3]
5.5V
70
ns
[1,2,3]
9
TwIH
Int. Request Input High Time
3.0V
5TpC
[1,2,3]
5.5V
5TpC
[1,2,3]
10
Twdt
Watch-Dog Timer Delay Time Before Time-Out
2.0V
25
ms
3.0V
10
ms
5.5V
5
ms
11
Tpor
Power-On Reset Time
2.0V
70
250
ms
[4]
3.0V
50
150
ms
[4]
5.5V
10
70
ms
[4]
2.0V
8
76
ms
[5]
3.0V
4
38
ms
[5]
5.5V
2
18
ms
[5]
Notes:
1. Timing Reference uses 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. IRQ 0,1,2 only.
4. Z86E02 only.
5. Z86C02/L02 only.
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
AC ELECTRICAL CHARACTERISTICS
Low Noise Mode (Z86C02/E02 Only)
T
A
= 40
C to +105
C
T
A
= 0
C to +70
C
1 MHz
4 MHz
No.
Symbol
Parameter
V
CC
Min
Max
Min
Max
Units
Notes
1
TPC
Input Clock Period
3.0V
1000
DC
250
DC
ns
[1]
5.5V
1000
DC
250
DC
ns
[1]
2
TrC
TfC
Clock Input Rise and Fall Times
3.0V
25
25
ns
[1]
5.5V
25
25
ns
[1]
3
TwC
Input Clock Width
3.0V
500
125
ns
[1]
5.5V
500
125
ns
[1]
4. TwTinL
Timer Input Low Width
3.0V
70
70
ns
[1]
5.5V
70
70
ns
[1]
5
TwTinH
Timer Input High Width
3.0V
2.5TpC
2.5TpC
[1]
5.5V
2.5TpC
2.5TpC
[1]
6
TpTin
Timer Input Period
3.0V
4TpC
4TpC
[1]
5.5V
4TpC
4TpC
[1]
7
TrTin,
TtTin
Timer Input Rise and Fall Time
3.0V
100
100
ns
[1]
5.5V
100
100
ns
[1]
8
TwIL
Int. Request Input Low Time
3.0V
70
70
ns
[1,2,3]
5.5V
70
70
ns
[1,2,3]
9
TwIH
Int. Request Input High Time
3.0V
2.5TpC
2.5TpC
[1,2,3]
5.5V
2.5TpC
2.5TpC
[1,2,3]
10 Tpor
Power-On Reset Time
3.0V
50
150
50
150
ms
[4]
5.5V
10
70
10
70
ms
[4]
2.0V
8
76
8
76
ms
[5]
3.0V
4
38
4
38
ms
[5]
5.5V
2
18
2
18
ms
[5]
11 Twdt
Watch-Dog Timer Delay
3.0V
10
10
ms
5.5V
5
5
ms
Notes:
1. Timing Reference uses 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. IRQ 0,1,2 only.
4. Z86E02 only.
5. Z86C02/L02 only.
Z86C02/E02/L02
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15
1
LOW NOISE VERSION
Low EMI Emission
The Z8
can be programmed to operate in a Low EMI emis-
sion mode by means of a mask ROM bit option (Z86C02)
or OTP bit option (Z86E02). Use of this feature results in:
s
All pre-driver slew rates reduced to 10 ns typical.
s
Internal SCLK/TCLK operation limited to a maximum of
4 MHz - 250 ns cycle time.
s
Output drivers have resistances of 200 ohms (typical).
s
Oscillator divide-by-two circuitry eliminated.
The Low EMI mode is mask-programmable to be selected
by the customer at the time the ROM Code is submitted
(for Z86C02 only).
PRECAUTION
Stack pointer register (SPL) at FFHex and general purpose register at FEHex are set to 00Hex after reset.
PIN FUNCTIONS
OTP Programming Mode
D7-D0 Data Bus. Data can be read from, or written to the
EPROM through this data bus.
V
CC
Power Supply. It is 5V during EPROM Read Mode
and 6.4V during the other modes (Program, Program Ver-
ify, etc.).
/CE Chip Enable (active Low). This pin is active during
EPROM Read Mode, Program Mode, and Program Verify
Mode.
/OE Output Enable (active Low). This pin drives the Data
Bus direction. When this pin is Low, the Data Bus is output.
When High, the Data Bus is input. This pin must toggle for
each data output read.
EPM EPROM Program Mode. This pin controls the differ-
ent EPROM Program Modes by applying different
voltages.
V
PP
Program Voltage. This pin supplies the program volt-
age.
Clear Clear (active High). This pin resets the internal ad-
dress counter at the High Level.
Clock Address Clock. This pin is a clock input. The internal
address counter increases by one with one clock cycle.
/PGM Program Mode (active Low). A Low level at this pin
programs the data to the EPROM through the Data Bus.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
surges above V
CC
occur on the XTAL1 pin.
In addition, processor operation of Z8 OTP devices may be
affected by excessive noise surges on the V
PP
, /CE,
/EPM, /OE pins while the microcontroller is in Standard
Mode.
Recommendations for dampening voltage surges in both
test and OTP mode include the following:
s
Using a clamping diode to V
CC.
s
Adding a capacitor to the affected pin.
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
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16
P R E L I M I N A R Y
DS96DZ80301
PIN FUNCTIONS (Continued)
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input
and output, respectively). These pins connect a parallel-
resonant crystal, LC, RC, or an external single-phase
clock (8 MHz max) to the on-chip clock oscillator and buff-
er.
Port 0, P02-P00. Port 0 is a 3-bit bi-directional, Schmitt-
triggered CMOS compatible I/O port. These three I/O lines
can be globally configured under software control to be in-
puts or outputs (Figure 8).
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs (except P33, P32, P31) that are not external-
ly driven. A valid CMOS level, rather than a floating node,
reduces excessive supply current flow in the input buffer.
On Power-up and Reset, the Auto Latch will set the ports
to an undetermined state of 0 or 1. Default condition is
Auto Latches enabled.
Figure 8. Port 0 Configuration
Open
Out
In
1.5 2.3 Hysteresis
PAD
Port 0 (I/O)
Z8
Auto Latch Option
R 500 k
VCC @ 5.0V
Z86C02/E02/L02
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17
1
Port 2, P27-P20. Port 2 is an 8-bit, bit programmable, bi-
directional, Schmitt-triggered CMOS compatible I/O port.
These eight I/O lines can be configured under software
control to be inputs or outputs, independently. Bits pro-
grammed as outputs can be globally programmed as ei-
ther push-pull or open-drain (Figure 9).
Figure 9. Port 2 Configuration
Open-Drain
Open
Out
In
1.5 2.3 Hysteresis
PAD
Port 2 (I/O)
Port 2
Z8
Auto Latch Option
R 500 k
VCC @ 5.0V
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
PIN FUNCTIONS (Continued)
Port 3, P33-P31. Port 3 is a 3-bit, CMOS compatible port
with three fixed input (P33-P31) lines. These three input
lines can be configured under software control as digital
Schmitt-trigger inputs or analog inputs.
These three input lines are also used as the interrupt
sources IRQ0-IRQ3 and as the timer input signal T
IN
(Fig-
ure 10).
Comparator Inputs. Two analog comparators are added
to input of Port 3, P31 and P32, for interface flexibility. The
comparators reference voltage P33 (REF) is common to
both comparators.
Typical applications for the on-board comparators; Zero
crossing detection, A/D conversion, voltage scaling, and
threshold detection. In analog mode, P33 input functions
serve as a reference voltage to the comparators.
The dual comparator (common inverting terminal) features
a single power supply which discontinues power in STOP
mode. The common voltage range is 0-4 V when the V
CC
is 5.0 V; the power supply and common mode rejection ra-
tios are 90 dB and 60 dB, respectively.
Interrupts are generated on either edge of Comparator 2's
output, or on the falling edge of Comparator 1's output.
The comparator output is used for interrupt generation,
Port 3 data inputs, or T
IN
through P31. Alternatively, the
comparators can be disabled, freeing the reference input
(P33) for use as IRQ1 and/or P33 input.
Figure 10. Port 3 Configuration
Port 3
Z8
D1
R247 = P3M
P31 (AN1)
P32 (AN2)
P33 (REF)
cc
DIG.
AN.
+
-
+
-
V
TIN
P31 Data Latch
IRQ2
IRQ3
P32 Data Latch
IRQ0
P33 Data Latch
IRQ1
PAD
PAD
PAD
0 = Digital
1 = Analog
IRQ 0,1,2 = Falling Edge Detection
IRQ3 = Rising Edge Detection
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19
1
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated
into the Z86C02/E02/L02 devices to enhance the standard
Z8
core architecture to provide the user with increased de-
sign flexibility.
RESET. This function is accomplished by means of a Pow-
er-On Reset or a Watch-Dog Timer Reset. Upon power-
up, the Power-On Reset circuit waits for T
POR
ms, plus 18
clock cycles, then starts program execution at address
000C (Hex) (Figure 11). The control registers' reset value
is shown in Table 4.
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V
CC
and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the four
following conditions:
s
Power bad to power good status
s
Stop-Mode Recovery
s
WDT time-out
s
WDH time-out (in Halt Mode)
s
WDT time-out (in Stop Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
Figure 11. Internal Reset Configuration
POR
(Cold Start)
P27
(Stop Mode)
Delay Line
T
POR
ms
18 CLK
Reset Filter
Chip
Reset
XTAL OSC
INT OSC
Table 4. Control Register
Reset Condition
Addr Reg.
D7 D6 D5 D4 D3 D2 D1 D0 Comments
FF
SPL
0
0
0
0
0
0
0
0
FE
GPR
0
0
0
0
0
0
0
0
FD
RP
0
0
0
0
0
0
0
0
FC
FLAGS U U U U U U U U
FB
IMR
0
U U U U U U U
FA
IRQ
U U
0
0
0
0
0
0 IRQ3 is used
for positive
edge
detection
F9
IPR
U U U U U U U U
F8
P01M
U U U
0
U U
0
1
F7*
P3M
U U U U U U
0
0 P2 open-drain
F6*
P2M
1
1
1
1
1
1
1
1 Inputs after
reset
F3
PRE1
U U U U U U
0
0
F2
T1
U U U U U U U U
F1
TMR
0
0
0
0
0
0
0
0
Note:
*Registers are not reset after a STOP-Mode Recovery
using P27 pin. A subsequent reset will cause these control
registers to be reconfigured as shown in Table 4 and the
user must avoid bus contention on the port pins or it may
affect device reliability.
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Program Memory. The Z8 addresses up to 512 bytes of
internal program memory (Figure 12). The first 12 bytes of
program memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that correspond
to the six available interrupts. Bytes 0-511 are on-chip one-
time programmable ROM.
Register File. The Register File consists of three I/O port
registers, 61 general-purpose registers, and 12 control
and status registers R0-R3, R4-R127 and R241-R255, re-
spectively (Figure 13). General-purpose registers occupy
the 04H to 7FH address space. I/O ports are mapped as
per the existing CMOS Z8. The instructions can access
registers directly or indirectly through an 8-bit address
field. This allows short 4-bit register addressing using the
Register Pointer. In the 4-bit mode, the register file is divid-
ed into eight working register groups, each occupying 16
continuous locations. The Register Pointer (Figure 14) ad-
dresses the starting location of the active working-register
group.
Figure 12. Program Memory Map
12
11
10
9
8
7
6
5
4
3
2
1
0
On-Chip
ROM
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IRQ5
1024
Figure 13. Register File
SPL
Stack Pointer (Bits 7-0)
Reserved
Register Pointer
Program Control Flags
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
Ports 0-1 Mode
Port 3 Mode
Port 2 Mode
To Prescaler
Timer/Counter0
T1 Prescaler
Timer/Counter1
Timer Mode
Not Implemented
General Purpose
Registers
Port 3
Port 2
Reserved
Port 0
RP
IMR
IRQ
IPR
P3M
P2M
PRE0
T0
PRE1
T1
TMR
P3
P2
P1
P0
P01M
Flags
Indentifiers
Location
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
4
3
2
1
0
128
127
Z86C02/E02/L02
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Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 60 gen-
eral-purpose registers. It is set to 00Hex after any reset.
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V
CC
voltage-specified operating range. Note:
Register R254 has been designated as a general-purpose
register. But is set to 00Hex after any reset.
Counter/Timer. There is an 8-bit programmable
counter/timers (T1), each driven by its 6-bit programmable
prescaler. The T1 prescaler is driven by internal or external
clock sources. (Figure 15).
The 6-bit prescaler divide the input frequency of the clock
source by any integer number from 1 to 64. The prescaler
drives its counter, which decrements the value (1 to 256)
that has been loaded into the counter. When both counter
and prescaler reach the end of count, a timer interrupt re-
quest IRQ5 (T1) is generated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters are
also programmed to stop upon reaching zero (Single-Pass
mode) or to automatically reload the initial value and con-
tinue counting (Modulo-N Continuous Mode).
The counter, but not the prescaler, is read at any time with-
out disturbing its value or count mode. The clock source for
T1 is user-definable and is either the internal microproces-
sor clock divided by four, or an external signal input
through Port 3. The Timer Mode register configures the ex-
ternal timer input (P31) as an external clock, a trigger input
that is retriggerable or non-retriggerable, or used as a gate
input for the internal clock.
Figure 14. Register Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7
r6
r5
r4
R253
(Register Pointer)
I/O Ports
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
r3
r2
r1
r0
Register Group 1
Register Group 0
R15 to R0
Register Group F
R15 to R4
R3 to R0
R15 to R0
FF
F0
0F
00
1F
10
2F
20
3F
30
4F
40
5F
50
6F
60
7F
70
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has five interrupts from four different
sources. These interrupts are maskable and prioritized
(Figure 16). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and one counter/timer. The Interrupt Mask
Register globally or individually enables or disables the
five interrupt requests (Table 5).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICE-
BOXTM emulator. The rising edge interrupt is not directly
supported on the Z86CCP00ZEM emulator.
Figure 15. Counter/Timers Block Diagram
OSC
2
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Clock
Logic
IRQ5
Internal Data Bus
Write
Write
Read
Internal Clock
Gated Clock
Triggered Clock
T P31
External Clock
Internal
Clock
4
IN
*
Table 5. Interrupt Types, Sources, and Vectors
Vector
Name
Source
Location
Comments
IRQ0
AN2(P32)
0,1
External (F)Edge
IRQ1
REF(P33)
2,3
External (F)Edge
IRQ2
AN1(P31)
4,5
External (F)Edge
IRQ3
AN2(P32)
6,7
External (R)Edge
IRQ4
Reserved
8,9
Reserved
IRQ5
T1
10,11
Internal
Notes:
F = Falling edge triggered
R = Rising edge triggered
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Clock. The Z8 on-chip oscillator has a high-gain, parallel-
resonant amplifier for connection to a crystal, ceramic res-
onator, or any suitable external clock source (XTAL1 = IN-
PUT, XTAL2 = OUTPUT). The crystal should be AT cut,
8 MHz max, with a series resistance (RS) of less than or
equal to 100 Ohms.
The crystal or ceramic resonator should be connected
across XTAL1 and XTAL2 using the vendors crystal or ce-
ramic resonator recommended capacitors from each pin
directly to device ground pin 14 (Figure 17). Note that the
crystal capacitor loads should be connected to V
SS
, Pin 14
to reduce Ground noise injection.
Figure 16. Interrupt Block Diagram
IRQ0 - IRQ5
IRQ
IMR
IPR
Priority
Logic
5
Global
Interrupt
Enable
Vector Select
Interrupt
Request
Figure 17. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
Ceramic
Resonator
or Crystal
External Clock
L
LC Clock
XTAL1
XTAL2
XTAL1
XTAL2
*
*
*
=Device Ground Pin
XTAL1
XTAL2
R
RC Clock
Vss *
Vss *
C
Vss *
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timer and
external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac-
tive. The device is recovered by interrupts, either external-
ly or internally generated. An interrupt request must be ex-
ecuted (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10
A. The STOP mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low input
condition on P27 releases the STOP mode. Program exe-
cution begins at location 000C(Hex). However, when P27
is used to release the STOP mode, the I/O port mode reg-
isters are not reconfigured to their default power-on condi-
tions. This prevents any I/O, configured as output when the
STOP instruction was executed, from glitching to an un-
known state. To use the P27 release approach with STOP
mode, use the following instruction:
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, i.e.:
Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT is refreshed when it is enabled within
every 1 Twdt period; otherwise, the controller resets itself,
The WDT instruction affects the flags accordingly; Z=1,
S=0, V=0. WDT = 5F (Hex)
Opcode WDT (5FH). The first time opcode 5FH is execut-
ed, the WDT is enabled and subsequent execution clears
the WDT counter. This must be done at least every T
WDT
;
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of T
POR
,
plus 18 XTAL clock cycles.The WDT does not run in stop
mode, unless the permanent WDT enable option is select-
ed. The WDT does not run in halt mode unless WDH in-
struction is executed or permanent WDT enable option is
selected.
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
Note: Opcode WDH and permanently enabled WDT is
not directly supported by the Z86CCP00ZEM.
Auto Reset Voltage (V
LV
). The Z8 has an auto-reset built-
in. The auto-reset circuit resets the Z8 when it detects the
V
CC
below V
LV
. Figure 18 shows the Auto Reset Voltage
versus temperature.
LD
P2M, #1XXX XXXXB
NOP
STOP
Notes:
X = Dependent on user's application.
Stop-Mode Recovery pin P27 is not edge triggered.
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT mode
Z86C02/E02/L02
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Options
The Z86C02/E02/L02 offers ROM protect, Low Noise,
Auto Latch Disable, RC Oscillator, and Permanent WDT
enable features as options. The Z86E02 must be power
cycled to fully implement the selected option after pro-
gramming.
Low Noise. The Z8 can operate in a low EMI emission
mode by selecting the low noise option. Use of this feature
will result in:
s
All drivers slew rates are reduced to 10 ns (typical).
s
Internal SCLK/TCLK = XTAL operation is limited to a
maximum of 4 MHz - 250 ns cycle time.
s
Output drivers have resistances of 200 ohms (typical).
s
Oscillator divide-by-two circuitry is eliminated.
ROM Protect. ROM Protect fully protects the Z8 ROM
code from being read externally. When ROM Protect is se-
lected, the instructions LDC and LDCI are supported.
(However, instructions LDE and LDEI are not supported.)
EPROM/TEST MODE Disable. When selected, this bit will
permanently disable EPROM and Factory Test mode.
Auto Latch Disable. Auto Latch Disable option when Se-
lected will globally disable all Auto Latches.
RC. RC Oscillator option when selected will allow using a
resistor (R) and a capacitor (C) as a clock source.
WDT Enable. WDT Enable option bit when selected will
have the WDT permanently enabled in all modes and can
not be stopped in HALT or STOP Mode.
EPROM Mode Description. In addition to V
DD
and GND
(V
SS
), the Z8 changes all its pin functions in the EPROM
mode. XTAL2 has no function, XTAL1 functions as /CE,
P31 functions as /OE, P32 functions as EPM, P33 func-
tions as V
PP
, and P02 functions as /PGM.
Please note that when using the device in a noisy environ-
ment, it is suggested that the voltages on the EPM and CE
pins be clamped to V
CC
through a diode to V
CC
to prevent
accidentally entering the OTP mode. The V
PP
requires
both a diode and a 100 pF capacitor.
User Modes. Table 6 shows the programming voltage of
each mode of Z86E02.
Figure 18. Typical Auto Reset Voltage (V
LV
) vs. Temperature
2.6
2.7
2.8
2.9
3.0
3.2
Vcc
(Volts)
40
C
40
C
Temp
2.5
20
C
0
C
20
C
60
C
80
C
100
C
3.1
1.8
1.9
2.0
2.1
2.2
2.4
1.7
2.3
1.6
Z86E02
Z86L02
Z86C02
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Internal Address Counter. The address of Z86E02 is
generated internally with a counter clocked through pin
P01 (Clock). Each clock signal increases the address by
one and the "high" level of pin P00 (Clear) will reset the ad-
dress to zero. Figure 19 shows the setup time of the serial
address input.
Programming Waveform. Figures 20, 21, 22, and 23
show the programming waveforms of each mode. Table 7
shows the timing of programming waveforms.
Programming Algorithm. Figure 24 shows the flow chart
of the Z86E02 programming algorithm.
Table 6. EPROM Programming Table
Programming
Modes
V
PP
EPM
/CE
/OE
/PGM
ADDR
DATA
V
CC
*
EPROM READ
NU
V
H
V
IL
V
IL
V
IH
ADDR
Out
5.0V
PROGRAM
V
H
V
IH
V
IL
V
IH
V
IL
ADDR
In
6.4V
PROGRAM VERIFY
V
H
V
IH
V
IL
V
IL
V
IH
ADDR
Out
6.4V
ROM PROTECT
V
H
V
H
V
H
V
IH
V
IL
NU
NU
5.0-6.4V
LOW NOISE
SELECT
V
H
V
IH
V
H
V
IH
V
IL
NU
NU
5.0-6.4V
AUTO LATCH
DISABLE
V
H
V
IH
V
H
V
IL
V
IL
NU
NU
5.0-6.4V
WDT ENABLE
V
H
V
IL
V
H
V
IH
V
IL
NU
NU
5.0-6.4V
EPROM/TEST
MODE Disable
V
H
V
IL
V
H
V
IL
V
IL
NU
NU
5.0-6.4V
Notes: V
H
=13.0V
0.25 V
DC
.
V
IH
=As per specific Z8 DC specification.
V
IL
=As per specific Z8 DC specification.
X=Not used, but must be set to V
H
, V
IH
, or V
IL
level.
NU=Not used, but must be set to either V
IH
or V
IL
level.
I
PP
during programming = 40 mA maximum.
I
CC
during programming, verify, or read = 40 mA maximum.
* V
CC
has a tolerance of
0.25V.
Table 7. Z86E02 Timing of Programming Waveforms
Parameters
Name
Min
Max
Units
1
Address Setup Time
2
s
2
Data Setup Time
2
s
3
V
PP
Setup
2
s
4
V
CC
Setup Time
2
s
5
Chip Enable Setup Time
2
s
6
Program Pulse Width
0.95
ms
7
Data Hold Time
2
s
8
/OE Setup Time
2
s
9
Data Access Time
188
4000
ns
10
Data Output Float Time
100
ns
11
Over-program Pulse Width
2.85
3.2
ms
12
EPM Setup Time
2
s
13
/PGM Setup Time
2
s
14
Address to /OE Setup Time
2
s
15
Option Program Pulse Width
150
ms
16
/OE Low Width
250
ns
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Figure 19. Z86E02 Address Counter Waveform
P01 = Clock
P00 = Clear
T2
T4
T3
T1
Internal
Address
T5
0 Min
9
Data
Vih
Vil
Invalid
Valid
Invalid
Valid
Legend:
T1 Reset Clock Width
T2 Input Clock High
T3 Input Clock Period
T4 Input Clock Low
T5 Clock to Address Counter Out Delay
30 ns Min
30 ns Min
70 ns Min
30 ns Min
15 ns Max
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Figure 20. Z86E02 Programming Waveform (EPROM Read)
Data
VIH
VIL
Invalid
Valid
Invalid
Valid
VIH
VIL
Address Stable
Address
Address Stable
0 Min
9
12
0 Min
EPM
VH
VIL
VCC
5V
/CE
VIH
VIL
/OE
VIH
VIL
VPP
VH
VIH
/PGM
VIH
VIL
3
16
16
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Figure 21. Z86E02 Programming Waveform (Program and Verify)
Address
VIH
VIL
Data
VIH
VIL
VPP
VIH
VCC
6.4V
3
4
5
/CE
VH
VIH
/PGM
VIH
VIL
12
15
15
EPM
VIL
Auto Latch
WDT
15
ETM
Disable
5V
VIH
VIL
VH
8
/OE
VIL
VIH
8
VIL
12
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Figure 22. Z86E02 Programming Options Waveform (ROM Protect and Low Noise Program)
Address
V
IH
V
IL
Data
V
IH
V
IL
V
PP
V
IH
V
CC
6.4V
/OE
3
4
5
/CE
V
H
V
IH
/PGM
V
IH
V
IL
12
15
15
EPM
V
IH
ROM Protect
Low Noise
5V
V
IL
V
IL
V
IH
V
H
12
V
H
V
IH
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Figure 23. Z86E02 Programming Options Waveform (Auto Latch Disable,
Permanent WDT Enable, and EPROM/TEST MODE Disable)
Address
VIH
VIL
Data
VIH
VIL
VPP
VIH
VCC
6.4V
3
4
5
/CE
VH
VIH
/PGM
VIH
VIL
12
15
15
EPM
VIL
Auto Latch
WDT
15
ETM
Disable
5V
VIH
VIL
VH
8
/OE
VIL
VIH
8
VIL
12
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
FUNCTIONAL DESCRIPTION (Continued)
Figure 24. Z86E02 Programming Algorithm
Start
Vcc = 6.4V
Vpp
= 13.0V
N = 0
Program
1 ms Pulse
Increment N
N = 25 ?
Yes
No
Verify
One Byte
Pass
Fail
Prog. One Pulse
3xN ms Duration
Verify Byte
Fail
Pass
Increment
Address
Last Addr ?
Yes
No
Vcc = Vpp = 5.0V
Verify All
Bytes
Device Failed
Addr =
First Location
Fail
Pass
Device Passed
Z86C02/E02/L02
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Z8 CONTROL REGISTERS
Figure 25. Timer Mode Register (F1
H
: Read/Write)
Figure 26. Counter Timer 1 Register (f2
H
:Read/Write)
Figure 27. Prescaler! Register (F3
H
: Write Only)
Figure 28. Port 2 Mode Register (F6
H
: Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
0 Disable T Count
1 Enable T Count
Reserved
(Must be 0)
0
0
0 No Function
1 Load T 1
0 Disable T Count
1 Enable T Count
1
1
T Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
IN
R241 TMR
Reserved (Must be 0.)
D7
D6
D5
D4
D3
D2
D1
D0
T Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T Current Value
(When READ)
1
1
R242 T1
D7
D6
D5
D4
D3
D2
D1
D0
Count Mode
0 = T Single Pass
1 = T Modulo N
1
1
Clock Source
1 = T Internal
0 = T External Timing Input
(T ) Mode
IN
1
1
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R243 PRE1
D7
D6
D5
D4
D3
D2
D1
D0
P2 - P2 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
7
0
R246 P2M
Figure 29. Port 3 Mode Register (F7
H
: Write Only)
Figure 30. Port 0 and 1 Mode Register
(F8
H
: Write Only)
Figure 31. Interrupt Priority Register
(F9
H
: Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
0 Port 2 Open-Drain
1 Port 2 Push-pull
Port 3 Inputs
0 Digital Mode
1 Analog Mode
Reserved (Must be 0)
R247 P3M
D7
D6
D5
D4
D3
D2
D1
D0
P0
3
-P0
0
Mode
00 = Output
01 = Input
Reserved (Must be 1.)
R248 P01M
Reserved (Must be 0.)
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0.)
R249 IPR
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
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P R E L I M I N A R Y
DS96DZ80301
Z8 CONTROL REGISTERS (Continued)
Figure 32. Interrupt Request Register
(FA
H
: Read/Write)
Figure 33. Interrupt Mask Register (FB
H
: Read/Write)
Figure 34. Flag Register (FC
H
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P32 Input
IRQ4 = Reserved
IRQ5 = T1
Reserved (Must be 0.)
R250 IRQ
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0.)
1 Enables IRQ5-IRQ0
(D = IRQ0)
1 Enables Interrupts
0
R251 IMR
D7
D6
D5
D4
D3
D2
D1
D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
R252 Flags
Figure 35. Register Pointer FD
H
: Read/Write)
Figure 36. Stack Pointer (FF
H
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0.)
Register Pointer
R253 RP
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Lower
Byte (SP - SP )
0
7
R255 SPL
Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
35
1
PACKAGE INFORMATION
Figure 37. 18-Pin DIP Package Diagram
Figure 38. 18-Pin SOIC Package Diagram
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
Zilog
36
P R E L I M I N A R Y
DS96DZ80301
ORDERING INFORMATION
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES
Preferred Package
P = Plastic DIP
Longer Lead Time
S = SOIC
Preferred Temperature
S = 0
C to +70
C
E = 40
C to +105
C
Speed
08 = 8 MHz
Environmental
C = Plastic Standard
Standard Temperature
18-Pin DIP
18-Pin SOIC
Z86E0208PSC
Z86E0208SSC
Z86L0208PSC
Z86L0208SSC
Z86C0208PSC
Z86C0208SSC
Z86E0208PSC1903
Z86E0208SSC1903
Extended Temperature
18-Pin DIP
18-Pin SOIC
Z86E0208PEC
Z86E0208SEC
Z86L0208PEC
Z86L0208SEC
Z86C0208PEC
Z86C0208SEC
Z86E0208PEC1903
Z86E0208SEC1903
Example:
Z 86E08 08 P S C is a Z86E08, 08 MHz, DIP, 0
to +70
C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
Z86C02/E02/L02
Zilog
Cost Effective, 512-Byte ROM CMOS Z8
Microcontrollers
DS96DZ80301
P R E L I M I N A R Y
37
1
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