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Электронный компонент: Z86L0408HSC

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DS97LVO0901
P R E L I M I N A R Y
1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z86L04/L08
1
Z8 8-B
IT
C
OST
-E
FFECTIVE
M
ICROCONTROLLERS
FEATURES
s
18-Pin DIP and SOIC Packages
s
0
C to + 70
C Standard Temperature
s
2.0V to 3.9V Operating Range
s
14 Input / Output Lines
s
Five Vectored, Prioritized Interrupts from Five Different
Sources
s
Two On-Board Comparators
s
Software Enabled Watch-Dog Timer (WDT)
s
Programmable Interrupt Polarity
s
Two Standby Modes: STOP and HALT
s
Low-Voltage Protection
s
ROM Mask/OTP Options:
ROM Protect
Auto Latch Disable
Permanent Watch-Dog Timer (WDT)
RC Oscillator
32 kHz Crystal Operation
Low EMI
WDT Clock Source (Z86L04 only)
s
Two Programmable 8-Bit Counter/Timers with
6-Bit Programmable Prescalers
s
Power-On Reset (POR) Timer
s
On-Chip Oscillator that Accepts RC, Crystal, Ceramic
Resonator, LC, or External Clock Drive
s
Clock-Free WDT Reset
s
Low-Power Consumption (40 mw)
s
Fast Instruction Pointer (1.5
s @ 8 MHz)
s
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
GENERAL DESCRIPTION
Zilog's Z86L04/L08 microcontrollers (MCUs) are members
of the Z8 single-chip MCU family, which offer easy soft-
ware/hardware system expansion.
For applications demanding powerful I/O capabilities, the
MCU's dedicated input and output lines are grouped into
three ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.
One on-chip counter/timer, with a large number of user-se-
lectable modes, off-load the system of administering real-
time tasks such as counting/timing and I/O data communi-
cations. Additionally, two on-board comparators process
analog signals with a common reference voltage (Figure
1).
Device
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Auto
Latch
Permanent
WDT
Z86L04
1K
125
8
Optional Optional
Z86L08
2K
125
8
Optional Optional
Note:
*General-Purpose
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
2
P R E L I M I N A R Y
DS97LVO0901
GENERAL DESCRIPTION
(Continued)
Note:
All Signals with a preceding front slash, "/", are ac-
tive Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Figure 1. Z86L04/L08 Functional Block Diagram
Port 3
Counter/
Timer
Interrupt
Control
Two Analog
Comparators
Port 2
I/O
(Bit Programmable)
FLAG
Register
Pointer
General-Purpose
Register File
Machine
Timing & Inst.
Control
Program
Memory
Program
Counter
Vcc
GND
XTAL
Port 0
I/O
Input
ALU
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
3
1
Figure 2. EPROM Programming Mode Block Diagram
Z8 MCU
Address
Counter
Address MUX
Data MUX
Z8 POR
T2
Option Bits
EPROM
PGM
Mode Logic
D7-D0
D7-D0
D7-D0
A10-A0
A10-A0
A10-A0
3 Bits
Clear
P00
Clock
P01
EPM
P32
/CE
XT1
/PGM
P02
VPP
P33
/OE
P31
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
4
P R E L I M I N A R Y
DS97LVO0901
PIN DESCRIPTIONS
Figure 3. 18-Pin Standard Mode Configuration
Table 1. 18-Pin Standard Mode Identification
Pin #
Symbol
Function
Direction
1-4
P24-P27
Port 2, Pins 4, 5, 6, 7In/Output
5
V
CC
Power Supply
6
XTAL2
Crystal Oscillator
Clock
Output
7
XTAL1
Crystal Oscillator
Clock
Input
8
P31
Port 3, Pin 1, AN1
Input
9
P32
Port 3, Pin 2, AN2
Input
10
P33
Port 3, Pin 3, REF
Input
11-13
P00-P02
Port 0, Pins 0, 1, 2
In/Output
14
GND
Ground
15-18
P20-P23
Port 2, Pins 0, 1, 2, 3In/Output
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
P23
P22
P21
P20
GND
P02
P01
P00
P33
18
DIP 18 - Pin
1
9
10
Figure 4. 18-Pin SOIC Configuration
Table 2. 18-Pin SOIC Pin Identification
Pin #
Symbol
Function
Direction
1-4
P24-P27
Port 2, Pins 4,5,6,7 In/Output
5
V
CC
Power Supply
6
XTAL2
Crystal Osc. Clock Output
7
XTAL1
Crystal Osc. Clock Input
8
P31
Port 3, Pin 1, AN1
Input
9
P32
Port 3, Pin 2, AN2
Input
10
P33
Port 3, Pin 3, REF
Input
11-13
P00-P02
Port 0, Pins 0,1,2
In/Output
14
GND
Ground
15-18
P20-P23
Port 2, Pins 0,1,2,3 In/Output
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
P23
P22
P21
P20
GND
P02
P01
P00
P33
18
SOIC 18 - Pin
1
9
10
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
5
1
ABSOLUTE MAXIMUM RATINGS
Notes:
Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation of
the device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
Total power dissipation should not exceed 462 mW for the
package. Power dissipation is calculated as follows:
1.
This applies to all pins except where otherwise noted.
2.
Maximum current into pin must be
600
A.
There is no input protection diode from pin to V
DD
.
3.
This excludes Pin 6 and Pin 7.
4.
Device pin is not at an output Low state.
Total Power dissipation = V
DD
x [I
DD
(sum of I
OH
)] + sum of [(V
DD
V
OH
) x I
OH
] + sum of (V
0L
x I
0L
)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 5).
Capacitance
T
A
= 25
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Min
Max
Units
Ambient Temperature under Bias
40
+105
C
Storage Temperature
65
+150
C
Voltage on any Pin with Respect to V
SS
[Note 1]
0.7
+12
V
Voltage on V
DD
Pin with Respect to V
SS
0.3
+7
V
Voltage on Pin 7 with Respect to V
SS
[Note 2] (Z86C02/L02)
0.7
V
DD
+1
V
Voltage on Pin 7,8,9,10 with Respect to V
SS
[Note 2] (Z86E02)
0.7
V
DD
+1
V
Total Power Dissipation
462
mW
Maximum Allowed Current out of V
SS
300
mA
Maximum Allowed Current into V
DD
270
mA
Maximum Allowed Current into an Input Pin [Note 3]
600
+600
A
Maximum Allowed Current into an Open-Drain Pin [Note 4]
600
+600
A
Maximum Allowed Output Current Sinked by Any I/O Pin
20
mA
Maximum Allowed Output Current Sourced by Any I/O Pin
20
mA
Maximum Allowed Output Current Sinked by Port 2, Port 0
80
mA
Maximum Allowed Output Current Sourced by Port 2, Port 0
80
mA
Figure 5. Test Load Diagram
From Output
Under Test
150 pF
Parameter
Min
Max
Input capacitance
0
15 pF
Output capacitance
0
20 pF
I/O capacitance
0
25 pF
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
6
P R E L I M I N A R Y
DS97LVO0901
DC CHARACTERISTICS
Z86L04/L08
T
A
= 0
C to +70
C
Typical
Sym.
Parameter
V
CC
[3]
Min
Max
@ 25
C
Units
Conditions
Notes
V
CH
Clock Input High
Voltage
2.0V
0.9 V
CC
V
CC
+0.3
V
Driven by External
Clock Generator
3.9V
0.9 V
CC
V
CC
+0.3
V
Driven by External
Clock Generator
V
CL
Clock Input Low
Voltage
2.0V
V
SS
0.3
0.1 V
CC
V
Driven by External
Clock Generator
3.9V
V
SS
0.3
0.1 V
CC
V
Driven by External
Clock Generator
V
IH
Input High Voltage
2.0V
0.9 V
CC
V
CC
+0.3
V
1
3.9V
0.9 V
CC
V
CC
+0.3
V
1
V
IL
Input Low Voltage
2.0V
V
SS
0.3
0.1 V
CC
V
1
3.9V
V
SS
0.3
0.1 V
CC
V
1
V
OH
Output High Voltage
2.0V
V
CC
0.4
3.0
V
I
OH
= 500
A
4,5
3.9V
V
CC
0.4
3.0
V
I
OH
= 500
A
4,5
V
OL1
Output Low Voltage
2.0V
0.8
0.2
V
I
OL
= +1.0 mA
4,5
3.9V
0.4
0.1
V
I
OL
= +1.0 mA
4,5
V
OL2
Output Low Voltage
2.0V
1.0
0.8
V
I
OL
= + 3.0 mA
4,5
3.9V
0.8
0.3
V
I
OL
= + 3.0 mA
4,5
V
OFFSET
Comparator Input
Offset Voltage
2.0V
25
10
mV
3.9V
25
10
mV
V
LV
V
CC
Low Voltage
Auto Reset
1.4
2.15
V
I
IL
Input Leakage
(Input Bias Current
of Comparator)
2.0V
1.0
1.0
A
V
IN
= 0V, V
CC
3.9V
1.0
1.0
A
V
IN
= 0V, V
CC
I
OL
Output Leakage
2.0V
1.0
1.0
A
V
IN
= 0V, V
CC
3.9V
1.0
1.0
A
V
IN
= 0V, V
CC
V
ICR
Comparator Input
Common Mode
Voltage Range
2.0
3.9
0
0
V
CC
1.0
V
CC
1.0
V
V
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
7
1
T
A
= 0
C to +70
C Typical
Sym Parameter
V
CC
[3]
Min
Max
@ 25
C
Units
Conditions
Notes
I
CC
Supply Current
2.0V
3.3
mA
@ 2 MHz
5,6
3.9V
6.8
mA
@ 2 MHz
5,6
2.0V
6.0
mA
@ 8 MHz
5,6
3.9V
9.0
mA
@ 8 MHz
5,6
I
CC1
Standby Current (Halt Mode)
2.0V
2.3
mA
@ 2 MHz
5,6,7
3.9V
3.8
mA
@ 2 MHz
5,6,7
2.0V
3.8
mA
@ 8 MHz
5,6,7
3.9V
4.8
mA
@ 8 MHz
5,6,7
I
CC2
Standby Current (Stop Mode)
2.0V
10
1.0
A
6,7
3.9V
10
1.0
A
6,7
I
ALL
Auto Latch Low Current
2.0V
12
3.0
A
0V < V
IN
< V
CC
3.9V
32
16
A
0V < V
IN
< V
CC
I
ALH
Auto Latch High Current
2.0V
8
-1.5
A
0V < V
IN
< V
CC
3.9V
16
-8.0
A
Notes:
1. Port 0, 2, and 3 only.
2. V
SS
= 0V = GND. The device operates down to V
LV
. The minimum operational V
CC
is determined by the value of the voltage V
LV
at the ambient temperature.
3. V
CC
= 2.0V to 3.9V, typical values measured at V
CC
= 3.3 V.
4. Standard Mode (not Low EMI mode).
5. Inputs at V
CC
or V
SS
, outputs are unloaded.
6. WDT is not running.
7. Comparator inputs at V
CC
.
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
8
P R E L I M I N A R Y
DS97LVO0901
AC ELECTRICAL CHARACTERISTICS
Figure 6. AC Electrical Timing Diagram
1
3
4
8
2
2
3
T
IRQ
IN
N
6
5
7
7
9
Clock
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
9
1
AC ELECTRICAL CHARACTERISTICS
Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
T
A
= 0
C to +70
C
8 MHz
No.
Symbol
Parameter
V
CC
Min
Max
Units
Notes
1
TpC
Input Clock Period
2.0V
125
DC
ns
1
3.9V
125
DC
ns
1
2
TrC,TfC
Clock Input Rise and Fall Times
2.0V
25
ns
1
3.9V
25
ns
1
3
TwC
Input Clock Width
2.0V
62
ns
1
3.9V
62
ns
1
4
TwTinL
Timer Input Low Width
2.0V
70
ns
1
.39V
70
ns
1
5
TwTinH
Timer Input High Width
2.0V
5TpC
1
3.9V
5TpC
1
6
TpTin
Timer Input Period
2.0V
8TpC
1
3.9V
8TpC
1
7
TrTin,
TtTin
Timer Input Rise and Fall Time
2.0V
100
ns
1
3.9V
100
ns
1
8
TwIL
Int. Request Input Low Time
2.0V
70
ns
1,2,3
3.9V
70
ns
1,2,3
9
TwIH
Int. Request Input High Time
3.0V
5TpC
1,2,3
3.9V
5TpC
1,2,3
10
Twdt
Watch-Dog Timer Delay Time Before Time-Out
2.0V
25
ms
3.9V
10
ms
11
Tpor
Power-On Reset Time
2.0V
70
ms
4
3.9V
50
ms
4
2.0V
20
ms
5
3.9V
6
ms
5
Notes:
1. Timing Reference uses 0.7 V
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. IRQ 0,1,2 only.
4. For Z86L08 using internal RC oscillator.
5. For Z86L04 using internal RC oscillator.
Precaution: Maximum frequency in Low EMI mode is 1 MHz.
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
10
P R E L I M I N A R Y
DS97LVO0901
PIN FUNCTIONS
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input
and output, respectively). These pins connect a parallel-
resonant crystal, LC, RC, or an external single-phase
clock (8 MHz max) to the on-chip clock oscillator and buff-
er.
Port 0, P02-P00. Port 0 is a 3-bit bidirectional, Schmitt-trig-
gered CMOS compatible I/O port. These three I/O lines
can be globally configured under software control to be in-
puts or outputs (Figure 7).
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs (except P33, P32, P31) that are not external-
ly driven. A valid CMOS level, rather than a floating node,
reduces excessive supply current flow in the input buffer.
On Power-up and Reset, the Auto Latch will set the ports
to an undetermined state of 0 or 1. Default condition is
Auto Latches enabled.
Figure 7. Port 0 Configuration
Open
Out
In
PAD
Port 0 (I/O)
Z8
Auto Latch Option
R 500 k
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
11
1
Port 2, P27-P20. Port 2 is an 8-bit, bit-programmable, bi-
directional, Schmitt-triggered, CMOS, compatible I/O port.
These eight I/O lines can be configured under software
control to be inputs or outputs, independently. Bits pro-
grammed as outputs can be globally programmed as ei-
ther push-pull or open-drain (Figure 8).
Figure 8. Port 2 Configuration
Open-Drain
Open
Out
In
1.5 2.3 Hysteresis
PAD
Port 2 (I/O)
Port 2
Z8
Auto Latch Option
R 500 k
VCC @ 5.0V
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
12
P R E L I M I N A R Y
DS97LVO0901
PIN FUNCTIONS (Continued)
Port 3, P33-P31. Port 3 is a 3-bit, CMOS, compatible port
with three fixed input (P33-P31) lines. These three input
lines can be configured under software control as digital
Schmitt-trigger inputs or analog inputs.
These three input lines are also used as the interrupt
sources IRQ0-IRQ3 and as the timer input signal T
IN
(Fig-
ure 9).
Figure 9. Port 3 Configuration
Port 3
Z8
D1
R247 = P3M
P31 (AN1)
P32 (AN2)
P33 (REF)
cc
DIG.
AN.
+
-
+
-
V
TIN
P31 Data Latch
IRQ2
IRQ3
P32 Data Latch
IRQ0
P33 Data Latch
IRQ1
PAD
PAD
PAD
0 = Digital
1 = Analog
IRQ 0,1,2 = Falling Edge Detection
IRQ3 = Rising Edge Detection
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
13
1
Comparator Inputs. Two analog comparators are added
to input of Port 3, P31 and P32, for interface flexibility. The
comparators reference voltage P33 (REF) is common to
both comparators.
Typical applications for the on-board comparators; Zero
crossing detection, A/D conversion, voltage scaling, and
threshold detection. In analog mode, P33 input functions
serve as a reference voltage to the comparators.
The dual comparator (common inverting terminal) features
a single power supply which discontinues power in STOP
mode. The common voltage range is 0-4V when the V
CC
is 5.0V; the power supply and common mode rejection ra-
tios are 90 dB and 60 dB, respectively.
Interrupts are generated on either edge of Comparator 2's
output, or on the falling edge of Comparator 1's output.
The comparator output is used for interrupt generation,
Port 3 data inputs, or T
IN
through P31. Alternatively, the
comparators can be disabled, freeing the reference input
(P33) for use as IRQ1 and/or P33 input.
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated
into the Z86L04/L08 devices to enhance the standard Z8
core architecture to provide the user with increased design
flexibility.
RESET. This function is accomplished by means of a Pow-
er-On Reset or a Watch-Dog Timer Reset. Upon power-
up, the Power-On Reset circuit waits for T
POR
ms, plus 18
clock cycles, then starts program execution at address
000C (Hex) (Figure 10). The control registers' reset values
are shown in Table 3.
Figure 10. Internal Reset Configuration
POR
(Cold Start)
P27
(Stop Mode)
Delay Line
T
POR
ms
18 CLK
Reset Filter
Chip
Reset
XTAL OSC
INT OSC
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
14
P R E L I M I N A R Y
DS97LVO0901
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V
CC
and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the five
following conditions:
s
Power bad to power good status
s
Stop-Mode Recovery
s
WDT time-out
s
WDT time-out (in HALT Mode)
s
WDT time-out (in STOP Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
Table 3. Control Register Reset Values
Reset Condition
Addr Reg.
D7 D6 D5 D4 D3 D2 D1 D0 Comments
FF
SPL
0
0
0
0
0
0
0
0
FE
GPR
0
0
0
0
0
0
0
0
FD
RP
0
0
0
0
0
0
0
0
FC
FLAGS U U U U U U U U
FB
IMR
0
U U U U U U U
FA
IRQ
U U
0
0
0
0
0
0 IRQ3 is used
for positive
edge
detection
F9
IPR
U U U U U U U U
F8*
P01M
U U U
0
U U
0
1
F7*
P3M
U U U U U U
0
0 P2 open-drain
F6*
P2M
1
1
1
1
1
1
1
1 Inputs after
reset
F5
PRE0
U U U U U U U
0
F4
T0
U U U U U U U U
F3
PRE1
U U U U U U
0
0
F2
T1
U U U U U U U U
F1
TMR
0
0
0
0
0
0
0
0
Notes:
*Registers are not reset after a STOP-Mode Recovery using P27
pin. A subsequent reset will cause these control registers to be
reconfigured as shown in Table 4 and the user must avoid bus
contention on the port pins or it may affect device reliability.
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
15
1
Program Memory. The Z8 addresses up to 1024,2048
bytes of internal program memory (Figure 11). The first 12
bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that cor-
respond to the six available interrupts. Bytes
0-1023/0-2047 are on-chip mask programmable ROM.
Register File. The Register File consists of three I/O port
registers, 61 general-purpose registers, and 12 control
and status registers R0-R3, R4-R127 and R241-R255, re-
spectively (Figure 12). General-purpose registers occupy
the 04H to 7FH address space. I/O ports are mapped as
per the existing CMOS Z8. The instructions can access
registers directly or indirectly through an 8-bit address
field. This allows short 4-bit register addressing using the
Register Pointer. In the 4-bit mode, the register file is divid-
ed into eight working register groups, each occupying 16
continuous locations. The Register Pointer (Figure 13) ad-
dresses the starting location of the active working-register
group.
Figure 11. Program Memory Map
12
11
10
9
8
7
6
5
4
3
2
1
0
On-Chip
ROM
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IRQ5
1024/2047
Figure 12. Register File
SPL
Stack Pointer (Bits 7-0)
General Purpose GPR
Register Pointer
Program Control Flags
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
Ports 0-1 Mode
Port 3 Mode
Port 2 Mode
To Prescaler
Timer/Counter0
T1 Prescaler
Timer/Counter1
Timer Mode
Not Implemented
General Purpose
Registers
Port 3
Port 2
Reserved
Port 0
RP
IMR
IRQ
IPR
P3M
P2M
PRE0
T0
PRE1
T1
TMR
P3
P2
P1
P0
P01M
Flags
Indentifiers
Location
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
4
3
2
1
0
128
127
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
16
P R E L I M I N A R Y
DS97LVO0901
FUNCTIONAL DESCRIPTION (Continued)
Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 60 gen-
eral-purpose registers. It is set to 00Hex after any reset.
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V
CC
voltage-specified operating range. Note:
Register R254 has been designated as a general-purpose
register. But is set to 00Hex after any reset.
Counter/Timer. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its 6-bit pro-
grammable prescaler. The T1 prescaler is driven by inter-
nal or external clock sources. (Figure 14).
The 6-bit prescaler divide the input frequency of the clock
source by any integer number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256)
that has been loaded into the counter. When both counter
and prescaler reach the end of count, a timer interrupt re-
quest IRQ5 (T1 or IRQ4 (T0) is generated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters are
also programmed to stop upon reaching zero (Single-Pass
mode) or to automatically reload the initial value and con-
tinue counting (Modulo-N Continuous Mode).
The counters, but not the prescaler, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal mi-
croprocessor clock divided by four, or an external signal in-
put through Port 3. The Timer Mode register configures the
external timer input (P31) as an external clock, a trigger in-
put that is retriggerable or non-retriggerable, or used as a
gate input for the internal clock.
Figure 13. Register Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7
r6
r5
r4
R253
(Register Pointer)
I/O Ports
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
r3
r2
r1
r0
Register Group 1
Register Group 0
R15 to R0
Register Group F
R15 to R4
R3 to R0
R15 to R0
FF
F0
0F
00
1F
10
2F
20
3F
30
4F
40
5F
50
6F
60
7F
70
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
17
1
Figure 14. Counter/Timers Block Diagram
OSC
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
4
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
2
Clock
Logic
IRQ4
IRQ5
Internal Data Bus
Write
Write
Read
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
Write
Read
Internal Data Bus
External Clock
Internal Clock
4
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
18
P R E L I M I N A R Y
DS97LVO0901
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has five interrupts from four different
sources. These interrupts are maskable and prioritized
(Figure 15). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and one counter/timer. The Interrupt Mask
Register globally or individually enables or disables the
five interrupt requests (Table 4).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICE-
BOXTM emulator. The rising edge interrupt is not directly
supported on the Z86CCP00ZEM emulator.
Table 4. Interrupt Types, Sources, and Vectors
Vector
Name
Source
Location
Comments
IRQ0
AN2(P32)
0,1
External (F)Edge
IRQ1
REF(P33)
2,3
External (F)Edge
IRQ2
AN1(P31)
4,5
External (F)Edge
IRQ3
AN2(P32)
6,7
External (R)Edge
IRQ4
T0
8,9
Internal
IRQ5
T1
10,11
Internal
Note:
F = Falling edge triggered
R = Rising edge triggered
Figure 15. Interrupt Block Diagram
IRQ0 - IRQ5
IRQ
IMR
IPR
Priority
Logic
6
Global
Interrupt
Enable
Vector Select
Interrupt
Request
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
19
1
Clock. The Z8 on-chip oscillator has a high-gain, parallel-
resonant amplifier for connection to a crystal, ceramic res-
onator, or any suitable external clock source (XTAL1 = IN-
PUT, XTAL2 = OUTPUT). The crystal should be AT cut,
8 MHz max, with a series resistance (RS) of less than or
equal to 100 Ohms.
The crystal or ceramic resonator should be connected
across XTAL1 and XTAL2 using the vendors crystal or ce-
ramic resonator recommended capacitors from each pin
directly to device ground pin 14 (Figure 16). Note that the
crystal capacitor loads should be connected to V
SS
, Pin 14
to reduce Ground noise injection.
Figure 16. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
Ceramic
Resonator
or Crystal
External Clock
L
LC Clock
XTAL1
XTAL2
XTAL1
XTAL2
*
*
*
=Device Ground Pin
XTAL1
XTAL2
R
RC Clock
Vss *
Vss *
C
Vss *
Note: If 32 KHz oscillator is selected then an external 10 Megohm resistor must be connected between XTAL1 and
XTAL2 pins.
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
20
P R E L I M I N A R Y
DS97LVO0901
FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timer and
external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac-
tive. The device is recovered by interrupts, either external-
ly or internally generated. An interrupt request must be ex-
ecuted (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10
A. The STOP mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low condition
on pin P27 releases the STOP mode even if P27 is an out-
put. Program execution begins at location 000C(Hex).
However, when P27 is used to release the STOP mode,
the I/O port mode registers are not reconfigured to their de-
fault power-on conditions. This prevents any I/O, config-
ured as output when the STOP instruction was executed,
from glitching to an unknown state. To use the P27 release
approach with STOP mode, use the following instruction:
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, such as:
Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT is refreshed when it is enabled within
every 1 Twdt period; otherwise, the controller resets itself,
The WDT instruction affects the flags accordingly; Z=1,
S=0, V=0. WDT = 5F (Hex)
Opcode WDT (5FH). The first time opcode 5FH is execut-
ed, the WDT is enabled and subsequent execution clears
the WDT counter. This must be done at least every T
WDT
;
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of T
POR
,
plus 18 XTAL clock cycles. The internal RC driven WDT
does not run in stop mode, unless the permanent WDT en-
able option is selected. The WDT does not run in halt
mode unless WDH instruction is executed or permanent
WDT enable option is selected.
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
Note: Opcode WDH and permanently enabled WDT is
not directly supported by the Z86CCP00ZEM.
WDT Clock Source. The WDT clock source option selects
the clock source for the WDT. It can be the internal on-
board RC oscillator or the internal system clock (SCLK). If
the SCLK is selected, then the WDT time out (T
WDT
) is
130,416 x SCLK and the T
POR
is 16,362 x SCLK. Also, if
the permanent WDT option is selected in this case; the
WDT will not run in STOP mode. (Z86L04 only)
Auto Reset Voltage (V
LV
). The Z8 has an auto-reset built-
in. The auto-reset circuit resets the Z8 when it detects the
V
CC
below V
LV
. Figure 17 shows the Auto Reset Voltage
versus temperature.
LD
P2M, #1XXX XXXXB
NOP
STOP
Notes:
X = Dependent on user's application.
Stop-Mode Recovery pin P27 is not edge triggered.
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT mode
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
21
1
OPTIONS
ROM protect, Low Noise, Auto Latch Disable, RC Oscilla-
tor, 32 kHz Crystal and Permanent WDT enable features
as options and must be selected at the time of ROM code
submissions.
ROM Protect. ROM Protect fully protects the Z8 ROM
code from being read externally. When ROM Protect is se-
lected, the instructions LDC and LDCI are supported.
(However, instructions LDE and LDEI are not supported.)
Auto Latch Disable. Auto Latch Disable option when Se-
lected will globally disable all Auto Latches.
RC. RC Oscillator option when selected will allow using a
resistor (R) and a capacitor (C) as a clock source.
WDT Clock Source. This selects the clock source of the
WDT and POR counter chain to be driven by either the in-
ternal system clock or the internal on-board RC oscillator.
(Z86L04 only).
Low EMI. The Low EMI (Low noise) mode by passes the
divide by two clock circuit (SCLK = XTAL/1) and lowers the
output sink and drive currents by 75 percent. The maxi-
mum oscillator frequency at XTAL pins is 1MHz.
WDT Enable. WDT Enable option bit when selected will
have the WDT permanently enabled in all modes and can
not be stopped in HALT or STOP Mode, if the internal RC
oscillator is selected as the clock source. If the system
clock (SCLK) is the clock source, the WDT will be stopped
in STOP mode.
Please note that when using the device in a noisy environ-
ment, it is suggested that the voltages on the EPM and CE
pins be clamped to V
CC
through a diode to V
CC
to prevent
accidentally entering the OTP mode. The V
PP
requires
both a diode and a 100 pF capacitor.
32 kHz Crystal. This disables the internal feedback resis-
tor on the crystal oscillator circuit (not for RC oscillator cir-
cuit) so that a 32 kHz crystal can be connected to the
XTAL1 and XTAL2 pins.
Figure 17. Typical Auto Reset Voltage (V
LV
) vs. Temperature
2.6
2.7
2.8
2.9
3.0
3.2
Vcc
(Volts)
40
C
40
C
Temp
2.5
20
C
0
C
20
C
60
C
80
C
100
C
3.1
1.8
1.9
2.0
2.1
2.2
2.4
1.7
2.3
1.6
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
22
P R E L I M I N A R Y
DS97LVO0901
Z8 CONTROL REGISTERS
Figure 18. Timer Mode Register (F1
H
: Read/Write)
Figure 19. Counter Timer 1 Register (f2
H
:Read/Write)
Figure 20. Prescaler1 Register (F3
H
: Write Only)
Figure 21. Port 2 Mode Register (F6
H
: Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
0 Disable T Count
1 Enable T Count
Reserved
(Must be 0)
0
0
0 No Function
1 Load T 1
0 Disable T Count
1 Enable T Count
1
1
T Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
IN
R241 TMR
Reserved (Must be 0.)
D7 D6
D5
D4 D3
D2 D1
D0
T Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T Current Value
(When READ)
1
1
R242 T1
D7 D6
D5 D4
D3 D2
D1
D0
Count Mode
0 T Single Pass
1 T Modulo
1
1
Clock Source
1 T Internal
0 T External Timing Input
(T ) Mode
IN
1
1
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R243 PRE1
D7 D6
D5
D4 D3
D2 D1
D0
P2 - P2 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
7
0
R246 P2M
Figure 22. Port 3 Mode Register (F7
H
: Write Only)
Figure 23. Port 0 and 1 Mode Register
(F8
H
: Write Only)
Figure 24. Interrupt Priority Register
(F9
H
: Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
0 Port 2 Open-Drain
1 Port 2 Push-pull
Port 3 Inputs
0 Digital Mode
1 Analog Mode
Reserved (Must be 0)
R247 P3M
D7
D6
D5
D4
D3
D2
D1
D0
P0
3
-P0
0
Mode
00 = Output
01 = Input
Reserved (Must be 1.)
R248 P01M
Reserved (Must be 0.)
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved (Must be 0.)
R249 IPR
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
23
1
Figure 25. Interrupt Request Register
(FA
H
: Read/Write)
Figure 26. Interrupt Mask Register (FB
H
: Read/Write)
Figure 27. Flag Register (FC
H
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P32 Input
IRQ4 = Reserved
IRQ5 = T1
Reserved (Must be 0.)
R250 IRQ
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0.)
1 Enables IRQ5-IRQ0
(D = IRQ0)
1 Enables Interrupts
0
R251 IMR
D7 D6
D5
D4 D3
D2 D1
D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
R252 Flags
Figure 28. Register Pointer FD
H
: Read/Write)
Figure 29. Stack Pointer (FF
H
: Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0.)
Register Pointer
R253 RP
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Lower
Byte (SP - SP )
7
0
R255 SPL
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
24
P R E L I M I N A R Y
DS97LVO0901
PACKAGE INFORMATION
Figure 30. 18-Pin DIP Package Diagram
Figure 31. 18-Pin SOIC Package Diagram
Z86L04/L08
Zilog
Z8 8-Bit Cost-Effective Microcontrollers
DS97LVO0901
P R E L I M I N A R Y
25
1
ORDERING INFORMATION
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES
Preferred Package
P = Plastic DIP
Longer Lead Time
S = SOIC
Preferred Temperature
S = 0
C to +70
C
Speed
08 = 8 MHz
Environmental
C = Plastic Standard
1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog's products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
Standard Temperature
18-Pin DIP
18-Pin SOIC
Z86L0408PSC
Z86L0408SSC
Z86L0808PSC
Z86L0808SSC
Example:
Z 86L08 08 P S C is a Z86L08, 08 MHz, Plastic DIP, 0
C to +70
C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
26
P R E L I M I N A R Y
DS97LVO0901