DS97KEY0102

P R E L I M I N A R Y

RELIMINARY

RODUCT

PECIFICATION

Z86U18

USB D

EVICE

ONTROLLER

WITH

CMOS Z86K15 MCU

FEATURES

USB Serial Interface Engine, Transceiver, and MCU
Intergrated for USB Function Controller

+4.0V to +5.5V Operating Range

Low Power Consumption: 60 mW @ 6 MHz

Digital Inputs CMOS Levels with Internal Pull-Up
Resistors

Four Direct Connect LED Drive Ports

Power-On Reset (POR), Hardware Watch-Dog Timer
(WDT)

Intergrated USB Transceiver @ 1.5 Mb/sec

For Use In A Variety of Applications Including Keyboards
and Game Controllers

Programmable 8-Bit Counter/Timer, with 6-Bit
Programmable Prescaler

Five Vectored, Priority Interrupts from Five Different
Sources

On-Chip Oscillator, Which Accepts A Crystal, Ceramic
Resonator, LC or External Clock Drive (all clock speeds
@ 6 MHz)

Low System EMI Emission

HALT/STOP Modes

GENERAL DESCRIPTION

The Z86U18 USB Controller is a member of the Z8

MCU

family. The Z86U18 is characterized by a flexible I/O
scheme, an efficient register architecture, and a number of
ancillary features. It contains a dedicated USB interface
(transceiver and SIE).

For applications demanding powerful I/O capabilities, the
Z86U18 (40- and 44-pin versions) provides 32 pins dedi-
cated to application input and output. These lines are
grouped into four ports, each port consists of eight lines
and are configurable under software control to provide tim-
ing, status signals, and serial or parallel I/O ports. It also
has 2 pins to connect directly to the USB cable.

To unburden the system from coping with real-time tasks,
such as counting/timing and I/O data communications, the
Z86U18 offers an on-chip counter/timer with a large num-
ber of user-selectable modes.

The Z86U18 achieves low EMI by means of several circuit
implementations in the output drivers and clock circuitry of
the device.

With fast execution, efficient use of memory, sophisticated
interrupt, input/output bit-manipulation capabilities, and
easy hardware/software system expansion, along with low
cost and low power consumption, the Z86U18 meets the
needs of a variety of sophisticated applications (Figure 1:
Functional Block Diagram)

Notes

: All signals with a preceding front slash, "/", are ac-

tive Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).

Device

ROM

(KB)

RAM

(Bytes)

I/O

Lines

Speed

(MHz)

Z86U18

188

Z86U18

USB Device Controller with CMOS Z86K15 MCU

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GENERAL DESCRIPTION

(Continued)

Power connections follow conventional descriptions be-
low:

This device is based on the Z86K15 device with the follow-
ing changes or modifications:

Power-On Reset

(POR): POR timing is a function of

the system clock.

POR = (3

* 2

)/f = .098

POR is in seconds and frequency in Hz. It may need
a programmable timer for warm reset (USB reset).

Watch-Dog Timer

(WDT): WDT is also driven by the

system clock and subject to same tolerance. The
WDT can be programmed for time out value of:

WDT = POR/2

EMI, 801-2 and 801-4 Compliance

: When used with

good engineering practice, this device should meet
Class B FCC with at least 10 dB of margin and comply
with the 801-2 group 4 air discharge. It shall meet 801-
4 EFT requirements in a system.

XTAL

: Drive to 3-pin ceramic resonator (@ 6 MHz).

XTAL In

: From ceramic resonator or crystal.

Connection

Circuit

Device

Power

Ground

GND

Figure 1. Z86U18 Functional Block Diagram

Port 3

Interrupt

Control

Port 2

I/O

(Bit Programmable)

ALU

Flags

Pointer

Machine

Timing & Inst.

Control

Program

Counter

GND

AL1

AL2

Output

Input

Port 0

Port 1

Open-Drain

Output

Open-Drain

Output

WDT

POR

Input

Counter/

Timers

USB SIE
and Trans

Program
Memory
4 KB ROM

VCC

D+

D-

3.3 V

VCC

USB

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

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USB FUNCTIONAL BLOCK DESCRIPTION

The USB portion of the chip is divided into two areas, the
transceiver and the Serial Interface Engine (SIE). The
transceiver handles incoming differential signals and "sin-
gle ended zero" (SE0). It also converts output data in dig-
ital form to differential drive at the proper levels.

The SIE does all other processing on incoming and out go-
ing data. This includes signal recovery timing, bit stuffing,
validity checking, data sequencing, and handshaking to

the host. Data flow into and out of the MCU portions is pro-
cessed through eight registers mapped into Expanded
Register File Memory at locations 010 to 017.

The USB SIE handles two endpoints (control at Endpoint
0 and data into the host from Endpoint 1). All communica-
tions are at the 1.5 Mb/sec HID class data rate. Future de-
vices will handle the full 12 Mb/sec data rate.

USB SUSPEND/RESUME FUNCTIONALITY

Suspend is intitiated by the host only, when it stops send-
ing start of frame signaling or start of frame keep alive
pulse.

When SIE detects the absence of start of frame signaling
from the host for more than 3 miliseconds, it sets the Sus-
pend bit in Reg7 and the Supspend Interrupt bit in Reg6
which interrupts the microcontroller. There is also an inter-
nal Suspend node that reflects the state of the Suspend bit
in Reg7. This Suspend node is used to put the tranceiver
in Suspend mode. When the microcontroller gets the Sus-
pend Interrupt, it stops all the clocks.

Resume can be initiated by host or by UC. Host initiates
Resume by sending J to K transition on D+ and D- pins.
Upon detecting J to K transition, the GFI makes Resume-
out signal active, which is used to wake the UC. Once the
UC is up, it clears the suspend bit in Reg7. UC can initiate
Resume by writing 1 to Send Resume bit in Reg7 for long-
er than 10mSec. This makes GFI to send J to K transition
on D+ and D- pins which indicates to the host the Resume
state. After 10 msec UC also clears the Suspend bit in
Reg7.

U18 EMULATIONS AND CODE DEVELOPMENT

An existing ICEBOXª Emulator has been modified by the
addition of an adaptor board. This board includes a FPGA
with the logic of the SIE, a commercial USB transceiver,
and a voltage regulator. These three functions adapt our
Z86C15/K15 to the USB world allowing the customer to
develop code to be placed into the ROM of U18s.

The ICEBOX has complete functional equivalence to the
final part including pin out to the application board. This
begins with the 40-pin DIP and covers the other pin config-
urations. Once code has been verified, it can be released
to Zilog and placed into the ROM of the Z86U18.

Figure 2. Data To/From K86U18

SYNC

DATA

CRC

EOP

Data packet sent at low speed

SYNC

Hub Setup

ENDP . . .

EOP

Hub enables low
speed port outputs

Preamble

sent at full speed

Token sent at low speed

SYNC

Hub Setup

EOP

Preamble

sent at full speed

Hub enables low
speed port outputs

Handshake sent at low speed

Hub enables low
speed port outputs

PID

Z86U18

USB Device Controller with CMOS Z86K15 MCU

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PIN IDENTIFICATION

Figure 3. 40-Pin DIP Pin ConÞguration

P36
P17
P16
P15
P14
P13
P12
P11
P10
P35

GND

P00
P01
P02
P03
P04
P05
P06
P07
P34

P23
P22
P21
P20
P37
P24
Test
XTALI (IN)
XTAL0
GND
P25
P26
VUSB
V

D+
D-
P30
P31
P32
P33

Z86UXX

DIP

3
4

5
6

7
8
9

10
11

12
13

14
15

18
19

39
38

37
36

35
34

31
30

29
28

27
26

25
24

23
22

(OUT)

Pin assignments to be determined.

Figure 4. 44-Pin PLCC and QFP Pin Assignments

Z86U18

PLCC/QFP

7
8
9
10
11
12
13
14
15
16
17

XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX

XXX

39
38
37
36
35
34
33
32
31
30
29

Z86U18

USB Device Controller with CMOS Z86K15 MCU

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ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to ab-
solute maximum rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONS

The characteristics listed here apply for standard test con-
ditions as noted. All voltages are referenced to GND. Pos-
itive current flows into the referenced pin (Figure 7).

CAPACITANCE

= 25

C; V

= GND = 0V; f = 1.0 MHz; unmeasured pins returned to GND.

Symbol

Description

Min

Max

Units

Supply Voltage*

Ð0.3

+7.0

STG

Storage Temp

Ð65

+150

Oper Ambient Temp

+105

Note:

* Voltage on all pins with respect to GND.

Figure 7. Test Load Diagram

From Output

Under Test

150 pF

Parameter

Max

Input Capacitance

12 pF

Output Capacitance

12 pF

I/O Capacitance

12 pF

Note:

Frequency tolerance

10%

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

DS97KEY0102

P R E L I M I N A R Y

DC CHARACTERISTICS

= 4.0V to 5.5V @ 0

C to +70

Sym

Parameter

Min

Max

Unit Condition

Clock Input High Voltage

0.7 V

+ 0.3V

Driven by External Clock Generator

Clock Input Low Voltage

GND Ð0.3

0.2 V

Driven by External Clock Generator

Input High Voltage

0.7 V

+ 0.3

Input Low Voltage

GND Ð0.3

0.2 V

Output High Voltage

Ð0.4

= Ð2.0 mA

Output High Voltage

Ð0.6

= Ð2.0 mA (see note 1 below.)

Output Low Voltage

= 4 mA

Output Low Voltage

= 4 mA (see note 1 below.)

Output Low

= V

Ð2.2 V (see note 1 below.)

Output Leakage

Ð1

mA V

= 0V, 5.25V

Supply Current

@ 6.0 MHz

CC1

Halt Mode Current

TBD

@ 6.0 MHz

CC2

Stop Mode Current

Pull Up Resistor

6.76

14.04

K ohm

Pull Up Resistor (P26-P25)

1.8

K ohm

USB

Voltage Regulator Output

3.0

3.6

D+,D- Differential Signaling

D- > D+

D+ > D-

@ > 200mV Difference (see note 2
below)

Notes:

1. Ports P37-P34. These may be used for LEDs or as general-purpose outputs requiring high sink current.
2. Except for SE0 for EOP and RESET (See 7.1.4 of USB Specification).

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

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AC ELECTRICAL CHARACTERISTICS
Additional Timing Table

°C to +70°C

5.0V, 6 MHz

Symbol

Parameter

Min

Max

Units

Notes

TpC

Input Clock Period

150

250

TrC,TfC

Clock Input Rise & Fall Times

TwC

Input Clock Width

TwTinL

Timer Input Low Width

TwTinH

Timer Input High Width

2.5TpC

TpTin

Timer Input Period

4TpC

TrTin

Timer Input Rise & Fall Timer

100

TwIL

Int. Request Low Time

1,2

TwIH

Int. Request Input High Time

3TpC

1,2

Twsm

Stop-Mode Recovery Width Spec

5TpC

Tost

Oscillator Start-up Time

5TpC

Twdt

Watch-Dog Timer

3,0

D+, D-

Differential Rise and Fall Times

300

Notes:

1. Timing Reference uses 0.7 V

for a logic 1 and 0.2 V

for a logic 0.

2. Interrupt request through Port 3 (P33-P31)
3. See USB Specification 7.1.1.2

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

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FUNCTIONAL DESCRIPTION

Program Memory. The 16-bit program counter addresses
4 KB of program memory space at internal locations (Fig-
ure 12).

The first 12 bytes of program memory are reserved for the
interrupt vectors. These locations have five 16-bit vectors
that correspond to the six available interrupts.

Byte 12 to byte 4095 consists of on-chip, mask pro-
grammed ROM. Addresses 4096 and greater are re-
served. The 4 KB program memory is mask programma-
ble.

Register File. The register file consists of four I/O port reg-
isters, 188 general-purpose registers and 11 control and
status registers (R3-R0, R4-191, and R255-R240, respec-
tively). The instructions can access registers directly or in-
directly through an 8-bit address field. This allows short, 4-
bit register addressing using the Register Pointer (Figure
13). In the 4-bit mode, the register file is divided into12
working-register groups, each occupying 16 continuous lo-
cations. The Register Pointer addresses the starting loca-
tion of the active working register group.

Note: To use the Bank Pointer: The instruction SRP 01
must be used to access the USB registers in the Expanded
Register File Space. These 8 registers (as defined on pp.
21-24) are available along with those registers from 10h to
BFh. Setting SRP 0 will allow access to the register loca-
tions 0 to BFh, including the I/O port registers at 0-3.

Figure 12. Program Memory Map

On-Chip

ROM

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

Reserved

(T0)

(USB)

P31

(IRQ2)

P33

(IRQ1)

P32

(IRQ0)

Reserved

65535

4096
4095

Reserved

Figure 13. Register Pointer Register

D7 D6 D5 D4 D3 D2 D1 D0

R253 RP

Bank Pointer

Working Register
Group

Default setting after RESET = 00000000

Z86U18
USB Device Controller with CMOS Z86K15 MCU

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FUNCTIONAL DESCRIPTION (Continued)

Figure 14. Register File Architecture

Working Register

Group Pointer

Bank Pointer

%FF

%FO

%0F

%00

Z8 Reg. File

REGISTER POINTER

% FF

% FE

% FD

% FC

% FB

% FA

% F9

% F8

% F7

% F6

% F5

% F4

% F3

% F2

% F1

% F0

SPL

Reserved

FLAGS

IMR

IRQ

IPR

Reserved

P3M

P2M

PRE0

Reserved

TMR

PORT REGISTERS

REG. GROUP (0)

Z8 STANDARD CONTROL REGISTERS

% (0) 03

% (0) 02

% (0) 01

% (0) 00

*
*

Reserved

Note:

Will not be reset with a

STOP Mode Recovery

Not

available

%BF

Usb Register Bank 1

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

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Counter/Timers. There is an 8-bit programmable
counter/timer (T0) driven by its own 6-bit programmable
prescaler (Figure 15).

The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. The pres-
caler drives the counter, which decrements the counter
value (1 to 256) on the prescaler overflow. When both the
counter and prescaler reach the end of count, a timer inter-
rupt request, IRQ4, is generated.

The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counter can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode) The
counter, but not the prescaler, is read at any time without
disturbing its value or count mode.

Figure 15. Counter/Timers Block Diagram

PRE0

Initial Value

Current Value

6-Bit

Down

Counter

8-bit

Down

Counter

IRQ4

Write

Read

Internal Data Bus

OSC

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USB Device Controller with CMOS Z86K15 MCU

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FUNCTIONAL DESCRIPTION (Continued)

Watch-Dog Timer. The Watch-Dog Timer is activated au-
tomatically by power-on

WDT Hot bit. Bit 7 of the Interrupt Request register (IRQ
register FAH) determines whether a hot start or cold start
occurred. A cold start is defined as reset occurring from
the power-up of the Z86U18 (the default upon power-up is
0). A hot start occurs when a WDT time-out has occurred
(bit 7 is set to 1). Bit 7 of the IRQ register is read-only and
is automatically reset to 0 when accessed.

Watch-Dog Timer Mode Register (WDTMR). The WDT-
MR is: WDT (ms)

» 50 ms.

WDT During HALT (D5-R250). This bit determines wheth-
er or not the WDT is active during HALT Mode. The default
is 1, and a 1 indicates active during HALT.

Figure 16. WDT Turn-On Timing After Reset

VCC

Internal

Reset

POR

Reset

Delay

* Reset Delay = POR 98.57 ms at 6 MHz.

18 Tpc

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

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Interrupts. The Z86U18 has five different interrupts from
three different groups. These interrupts are maskable and
prioritized (Figure 17). The five sources are divided as fol-
lows: three sources are claimed by Port 3 lines P33-P31,
one is claimed by the counter/timer, and the other is
claimed by the USB interface. The Interrupt Masked Reg-
ister globally or individually enables or disables the six in-
terrupts requests.

When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All interrupts are
vectored through locations in the program memory. When
an interrupt machine cycle is activated an interrupt request
is granted. Thus, this disables all of the subsequent inter-
rupts, saves the Program Counter and status flags, and
then branches to the program memory vector location re-
served for that interrupt. This memory location and the
next byte contain the 16-bit address of the interrupt service
routine for that particular interrupt request.

To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt request needs service.

EMI. Lower EMI on the Z86U18 is achieved through circuit
modifications. The internal divide-by-two circuit has been
removed to further reduce EMI.

The Z86U18 also accepts external clock from Pin 33 (40-
Pin DIP).

Figure 17. Interrupt Block Diagram

IRQ

IMR

Priority

Logic

Global

Interrupt

Enable

Vector Select

IRQ0-IRQ4

IPR

Figure 18. Oscillator ConÞguration

XTAL1 (in)

XTAL2 (out)

External Clock

XTAL1

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USB Device Controller with CMOS Z86K15 MCU

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FUNCTIONAL DESCRIPTION (Continued)

Power-On-Reset (POR). A timer circuit is triggered by the
system oscillator and is used for the Power-On Reset
(POR) timer function. The POR time allows V

and the os-

cillator circuit to stabilize before instruction execution be-
gins. POR period is defined as:

The POR timer circuit is a one-shot timer triggered by low-
er fail to Power OK status. The POR time is a nominal 100
ms at 6 MHz. The POR time is bypassed after Stop-Mode
Recovery.

HALT. HALT turns off the internal CPU clock, but not the
oscillator. The counter/timer and external interrupts IRQ0,
IRQ1, IRQ2, and IRQ3 remain active. The Z86U18 recov-
ers by interrupts, either externally or internally.

USB Reset. Detection by the SIE of a reset from the Host
will cause the chip to reset. The reset will be remembered
so that the program can decide the source of the reset.
The USB Reset will act even if the chip is in the STOP
mode.

STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation. It reduces the standby current to
less than 10

mA. The STOP Mode is terminated by an in-

terrupt. An interrupt from any of the active (enabled) inter-
rupts will remove the chip from the STOP Mode ( Ports 31-
33 and the USB reset). The timer can not do this as the
clock is stopped. This causes the processor to restart the
application program at the address or the vector of the in-
terrupt and continue the program at the end of the interrupt
service routine. In order to enter STOP (or HALT) Mode, it
is necessary to first flush the instruction pipeline to avoid
suspending execution in mid-instruction. To do this, the
user must execute a NOP (opcode=FFH) immediately be-
fore the appropriate sleep instruction, such as:

POR (ms) = 98 ms

NOP

; clear the pipeline

STOP

; enter STOP Mode

NOP

; clear the pipeline

HALT

; enter HALT Mode

Z86U18

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USB Device Controller with CMOS Z86K15 MCU

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Z8 CONTROL REGISTER DIAGRAMS

Figure 19. Timer Mode Register

(F1

: Read/Write)

Figure 20. Counter/Timer 0 Register

(F4

: Read/Write)

Figure 21. Prescaler 0 Register

(F5

: Write Only)

Figure 22. Port 2 Mode Register

(F6

: Write Only)

0 = Disable T0 Count
1 = Enable T0 Count

0 = No Function
1 = Load T0

R241 TMR

Reserved (Must be 0)

T0 Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T0 Current Value
(When READ)

R244 T0

Count Mode

0 = T Single Pass
1 = T Modulo N

Reserved (Must be 0)

Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)

R245 PRE0

P24-P27 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT

R246 P2M

Reserved

Figure 23. Port 2 Open Drain Register

(F7

: Write Only)

Figure 24. Interrupt Priority Register

(F9

: Write Only)

Figure 25. Interrupt Request Register

(FA

: Read/Write)

0 Port 2 Open-Drain
1 Port 2 Push-Pull

D7 D6

D3 D2

Reserved (Must be 0)

R247 P3M

Interrupt Group Priority

Reserved = 000
C > A > B = 001
A > B > C = 010
A > C > B = 011
B > C > A = 100
C > B > A = 101
B > A > C = 110
Reserved = 111

IRQ0, IRQ2 Priority (Group B)

0 = IRQ2 > IRQ0
1 = IRQ0 > IRQ2

IRQ1, IRQ4 Priority (Group C)

0 = IRQ1 > IRQ4
1 = IRQ4 > IRQ1

Reserved (Must be 0)

R249 IPR

R250 IRQ

IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = USB
IRQ4 = T0

WDT During HALT
0 OFF *
1 ON

Stop Flag
0 POR/WDT*
1 Stop Recovery

On RESET

WDT Hot Bit (Read Only)
0 POR*
1 WDT Timeout

Z86U18
USB Device Controller with CMOS Z86K15 MCU

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Z8 CONTROL REGISTER DIAGRAMS (Continued)

Figure 26. Interrupt Mask Register

(FB

: Read/Write)

Figure 27. Flag Register

(FC

: Read/Write)

Figure 28. Register Pointer

(FD

: Read/Write)

D7 D6

1 Enables IRQ5-IRQ0
(D0 = IRQ0)

Reserved (Must be 0)

1=Global Interrupt Enable
0=Global Interrupt Disable

R251 IMR

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

R252 Flags

Bank Pointer

R253 RP

Figure 29. Stack Pointer

(FF

: Read/Write)

Stack Pointer Lower
Byte (SP0-SP7)

R255 SPL

Z86U18

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USB REGISTERS

REGISTER DESCRIPTIONS

Table 1. Address Offset

Located @ 01 in Expanded Register Space

Register

Address

Reset Value

Function Address

Endpoint 0 CSR

Endpoint 0 Write Count

Endpoint FIFO

IN CSR

IN FIFO

Interrupt Register

Miscellaneous Register

Figure 30. Function Address Register

Function Address

Not Used

000h

Bit

SIE

Description

6:0

R/W

Upon receiving a SET_Address descriptor, the microcontroller writes this
register with the address received from the host.

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USB Device Controller with CMOS Z86K15 MCU

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REGISTER DESCRIPTIONS (Continued)

Figure 31. Endpoint 0 CS Register

D6 D5

D4 D3 D2

D1 D0

Out _pkt _rdy

In _pkt _rdy
Force Stall
Data End
Setup End
Send Stall

Serviced Out Packet Ready

Serviced Setup End

001h

Bit No

Bit Description

SIE

Description

Serviced Setup End

The microcontroller writes a 1 to this register to clear setup end bit.

Serviced Outpacket
Ready

The microcontroller writes a 1 to this register to clear out packet ready
bit.

Send STALL

If the microcontroller decodes an invalid descriptor, it writes a 1 to this
register before clearing out_pkt_rdy bit or when microcontroller decodes
a set feature or clear feature USB command from the host.

Setup End

If the function receives a new setup transaction before the previous one
is complete (entire length of data is transferred), this bit is set. Upon
seeing this bit set, the microcontroller should abort the current set
operation.

Data End

During the data phase of a control transfer after the microcontroller has
received/sent the last data as speciÞed in the setup phase, it sets this
bit.

Force STALL

The SIE writes to this register, when it encounters a protocol violation,
and issues a STALL handshake to the current control transfer.

In Packet Ready

During the data phase, after the microcontroller has Þlled the data, it sets
this bit. It is cleared by SIE upon successful transmittion of data.

Out Packet Ready

The SIE sets this bit after writing data to the FIFO. The microcontroller
clears this bit by writing it to Serviced Out Packet Ready bit.

Figure 32. Endpoint 0 Write Count Register

Write Count

00000

002h

Bit

SIE

Description

2:0

The contents indicates the number of bytes in the FIFO.

Z86U18

Zilog

USB Device Controller with CMOS Z86K15 MCU

DS97KEY0102

P R E L I M I N A R Y

Figure 33. Endpoint 0 FIFO Register

D1 D0

FIFO Data

003

Bit

SIE

Description

7:0

R/W

This is the Endpoint 0 FIFO data register.

Figure 34. IN CS Register

000

D6 D5

D4 D3 D2

D1 D0

In_pkt _rdy

Force Stall

IN MAXP

004

/Bit No

Bit Description

SIE

Description

4:2

IN MAXP

Before setting in_pkt_rdy, the microcontroller writes the maximum packet
size to these bits. The default value = 8 Bytes.

Force STALL

R/W

The SIE writes this register, when it encounters a protocol violation, and
issues a STALL handshake to the current transfer. The microcontroller sets
this bit, when it receives a SET_FEATURE (ENDPOINT_STALL), and clears
it, when it receives a CLEAR_FEATURE (ENDPOINT_STALL).

In Packet Ready W

After the microcontroller has Þlled the data, it sets this bit. It is cleared by
SIE upon successful transmission of data.

Figure 35. IN FIFO Register

D1 D0

FIFO Data

005h

Bit

SIE

Description

7:0

The microcontroller writes IN data to this register.

Z86U18
USB Device Controller with CMOS Z86K15 MCU

Zilog

P R E L I M I N A R Y

DS97KEY0102

REGISTER DESCRIPTIONS (Continued)

Figure 36. Interrupt Register

Endpoint 0 Interrupt

Suspend Interrupt

00000

IN Endpoint Interrupt

006h

Resume Interrupt

Bit No

Bit Description

SIE

Description

Resume Interupt

The ßag is sent on the Host signal to resume operations.

Suspend Interrupt

The bit is set when theSuspend signaling is received from the host.

IN Endpoint Interrupt

This bit is set upon:
1) clearing in_pkt_ rdy
2) setting Force STALL.

Endpoint 0 Interrupt

This bit set by SIE upon:
1) setting out_pkt_rdy
2) clearing in_pkt_rdy
3) setting Force STALL
4) clearing data_end
5) setting data_end

Figure 37. Misc. Register

D6 D5

D4 D3 D2

D1 D0

Suspend

Interrupt Mask Bits

000

Send Resume

007h

Bit No

Bit Description

SIE

Description

4:2

Interrupt Mask Bits

R/W

This has bit correspondence to the interrupt register. A value of 1, implies
that particular interrupt is disabled.

Send Resume

The microcontroller writes a 1 to this bit, while in suspend mode, and
wants to start a resume sequence after the clocks are running. This bit is
set high for a duration of at least 10 ms by microcontroller.

Suspend

R/W

This bit is set by the SIE when, the microcontroller is to enter suspend
mode. The microcontroller clears this bit after Þnishing resume signaling,
or after it receives a resume out interrupt, and the clocks have started.

Z86U18
USB Device Controller with CMOS Z86K15 MCU

Zilog

P R E L I M I N A R Y

DS97KEY0102

ORDERING INFORMATION

For fast results, contact your Zilog sales office for assistance in ordering the part desired.

CODES

Package
P = Plastic DIP
V = Plastic Leaded Chip Carrier
F = Quad Flat Pack

Speed
06 = 6 MHz

Environment
C = Plastic Standard

Temperature
S = 0

°C to +70°C

© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.

ZilogÕs products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com

6 MHz

40-Pin DIP

44-Pin PLCC

44-PIN QFP

28-Pin DIP

28-Pin SOIC

Z86U18PSC

Z86U18VSC

Z86U18FSC

Z86U18PSC

Z86U18SSC

Example:

Z 86U18 05 P S C

Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix

is a Z86U18, 6 MHz, DIP, 0

°C to +70°C, Plastic Standard Flow

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Document Outline

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Document Outline

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