Z89165/166/167/168/169

DTAD C

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ILOG

CP96TAD0103

FEATURES

25 Expanded Register Files

47 Input/Output Lines (Z89165)
31 Input/Output Lines (Z89166)
43 Input/Output Lines (Core Processor)

Six Vectored, Prioritized Z8 Interrupts with
Programmable Polarity

Three Vectored, Prioritized DSP Interrupts with
Programmable Polarity

Two Analog Comparators

Two Programmable Z8 8-Bit Counter/Timers,
Each with Two 6-Bit Programmable Prescaler

Watch-Dog Timer /Power-On Reset

On-Chip Oscillator that Accepts a Crystal,
Ceramic Resonator, LC, RC, or External Clock Drive

RAM and ROM Protect, Low-EMI Option

USTOMER

ROCUREMENT

PECIFICATION

Part

Z8 ROM

Z8 RAM*

Speed

Number

(KBytes)

(MHz)

Z89165

236

Z89166

ROMless

236

Z89167

236

Z89168

ROMless

236

Z89169

236

*General-Purpose

Part

DSP ROM

DSP RAM

Speed

Number

(Words)

(MHz)

Z89165

512

Z89166

512

Z89167

512

Z89168

512

Z89169

512

68- and 84-Pin PLCC Packages

4.5- to 5.5-Volt Operating Range

Low-Power Consumption (200 mW Typical)

C to +70

C Temperature Range

GENERAL DESCRIPTION

Zilog's Digital Voice Processor Controller family
combines a Z8

microcontroller and a DSP processor

on-chip for a cost-effective turnkey system in digital
telephone answering devices and other voice processing
applications.

The dual-processor architecture is loosely coupled by
mailbox registers and an interrupt system, enabling DSP or
Z8 programs to be directed by events in each other's
domain.

The Z8 microcontroller uses an expanded register file to
allow access to register-mapped peripheral and I/O
circuits for programming versatility.

The 16-bit DSP processor features a 24-bit ALU and
accumulator with single-cycle instructions, providing the
algorithm processing power necessary for telephone voice
quality.

Z89165/167/169

AND

Z89166/168 (ROM

LESS

)

NHANCED

UAL

-P

ROCESSOR

DTAD C

ONTROLLERS

The Z89165/166 devices offer a half-flash 8-bit A/D
converter with up to 128 kHz sample rate and a 10-bit
Pulse-Width modulator (PWM) D/A converter, eliminating
the need for an external CODEC.

The Z89167/168/169 devices feature a hardware ARAM
interface, as well as a dual-CODEC interface. A 10-bit
PWM D/A converter is also on-chip.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

Ground

GND

Z89165/166/167/168/169

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ONTROLLERS

CP96TAD0103

ILOG

GENERAL DESCRIPTION

(Continued)

Port 0

P00
P01
P02
P03

P04
P05
P06
P07

P10

P11

P12
P13
P14
P15
P16
P17

P20
P21
P22
P23
P24
P25
P26
P27

P31
P32
P33

P40
P41
P42
P43
P44
P45
P46
P47

P50
P51
P52
P53
P54
P55
P56
P57

RMLS

/AS

/DS

R/W

Timer 0

Capture Reg.

Port 3

Port 1

Port 4

Port 2

Port 5

Timer 1

256 x 8 Bit

24 Kbytes

Program

ROM

(Z89165)

Z8 Core

Internal Address Bus

Internal Data Bus

Expanded Register

File

(Z8)

Peripheral

(DSP)

Expanded
Register Bus

Extended Bus of the DSP

6K Words

Program

ROM

DSP Core

Internal Address Bus

Internal Data Bus

DSP Port

PWM

(10-Bit)

ADC

(8-Bit)

Timer 2

Timer 3

Extended Bus of the DSP

Ext.

Memory

Control

OSC

Power

XTAL1
XTAL2

VDD

GND

/RESET

INT 1

INT 2

DSP0
DSP1

AN IN
AN VDD
AN GND
VREF+
VREF-

PWM

256 Word

RAM 0

256 Word

RAM 1

P34
P35
P36
P37

Input

Output

I/O

(Bit

Programmable)

I/O

(Bit

Programmable)

Address

or I/O

(Nibble

Programmable)

Address/Data

or I/O

(Byte

Programmable)

I/O

(Bit

Programmable)

mailbox

Z89165/166 Functional Block Diagram

Z89165/166/167/168/169

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ONTROLLERS

ILOG

CP96TAD0103

Port 0

P00
P01
P02
P03

P04
P05
P06
P07

P10

P11

P12
P13
P14
P15
P16
P17

P20
P21
P22
P23
P24
P25
P26
P27

P40
P41
P42
P43
P44
P45
P46
P47

P50
P51
P52
P53

Timer0

Port 4

Port 1

Port 5

Port 2

ARAM

Controller

Timer1

256 x 8-Bit

24 Kbytes (167)
32 Kbytes (169)

Program ROM

Z8 Core

Internal Register Bus

Timer3

Timer2

Power

ARAM

Control

I/O

(Bit

Programmable)

/RAS
/CAS
ARAM_R/W
ARAM_/OE

Address

or I/O

(Nibble

Programmable)

Address/Data

or I/O

(Byte

Programmable)

I/O

(Bit

Programmable)

DIN

DENA0

DCLK

DOUT

DENA1

PWM

(10-Bit)

Port 3

I/O

(Bit

Programmable)

Internal Address Bus

Internal Data Bus

8K Words

Program ROM

Address Bus

Data Bus

DSP

Core

Peripheral

Registers

(DSP)

Extended

(Z8)

Peripheral Data Bus of the DSP

Mailbox

Data0
Data1
Data2
Data3
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ARAM_SEL0
ARAM_SEL1

Input

Output

P31
P32
P33

P34
P35
P36
P37

CODEC

Interface

RMLS

/AS

/DS

R/W

Z8 EXT.

Memory

Control

PWM

/RESET
VDD
GND

-5V

Control

Out -5V

OSC

XTAL1
XTAL2

GENERAL DESCRIPTION

(Continued)

Z89167/168/169 Functional Block Diagram

Z89165/166/167/168/169

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ONTROLLERS

CP96TAD0103

ILOG

Z89165 68-Pin PLCC Pin Identification

Z89166 68-Pin PLCC Pin Identification

Pin Name

Function Direction

+5V

Power

5V Power Input
(Digital Power)

GND

Power

Device Ground
(Digital Ground)

AIN

8-Bit A to D Converter Input

Vref

AIN

Low Reference Level for
A to D Converter

Vref+

AIN

High Reference Level for
A to D Converter

AN VDD

Power

ADC +5V Power
(Analog Power)

AN GND

Power

ADC Ground
(Analog Ground)

P00-P07 Data

I/O

General-Purpose I/O Port

P10-P17 Data

I/O

General-Purpose I/O Port

P20-P27 Data

I/O

General-Purpose I/O Port

Pin Identification

Pin Name

Function Direction

P31-P37 Data

I/O

General-Purpose I/O Port

P40-P47 Data

I/O

General-Purpose I/O Port

P50-P57 Data

I/O

General-Purpose I/O Port

DSP0-DSP1 Data 0

General-Purpose 0 Port

XTAL1

OSC1

20.48 MHz Crystal
Oscillator Input

XTAL2

OSC2

20.48 MHz Crystal
Oscillator Input

/RESET

I/O

System RESET

PWM

Out

10-Bit PWM, 5V TTL Output

Z89165

68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

P31

P32

P33

P34

VDD

P35

P14

DSP1

DSP0

P36

P13

P37

P40

P12

P06

P41

P42

VREF+

ANIN

VREF-

ANGND

/AS

/RESET

R//W

PWM

P10

P47

P11

P46

P53

P45

P44

P43

N/C

XTAL2

XTAL1

P22

P56

P23

P55

P54

GND

P17

P05

P24

P16

P25

P15

P26

P27

N/C

P00

P01

P02

P03

P57

P50

P04

VDD

RMLS

/DS

P51

P52

P21

P20

P07

GND

ANVDD

PIN DESCRIPTION

Z89166

68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

P31

P32

P33

P34

VDD

P35

P14

DSP1

DSP0

P36

P13

P37

P40

P12

P06

P41

P42

VREF+

ANIN

VREF-

ANGND

/AS

/RESET

R//W

PWM

P10

P47

P11

P46

P53

P45

P44

P43

/SYNC

XTAL2

XTAL1

P22

P56

P23

P55

P54

GND

P17

P05

P24

P16

P25

P15

P26

P27

SCLK

P00

P01

P02

P03

P57

P50

P04

VDD

/DS

P51

P52

P21

P20

P07

GND

ANVDD

Z89165/166/167/168/169

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ONTROLLERS

ILOG

CP96TAD0103

1 84

Z89168

84-Pin PLCC

42 43

VCC

ADDR0

ADDR1

ADDR2

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ARAM_SEL0

ARAM_SEL1

DATA0

DATA1

DATA2

DATA3

/RAS

/CAS

GND

VCC

C_CLOCK

C_EN0

C_EN1

P50

P51

P52

P53

OUT_5V

GND

/AS

P37

P36

P35

P34

P33

P32

P31

PWM

P10

GND

P11

P12

P13

R/W

P14

P15

P16

P17

VCC

P00

P01

P02

P03

P04

P05

P06

P07

/RESET

ARAM_R/W

ARAM_OE

ADDR3

AL1

AL2

P27

P26

P24

P23

P22

P21

P20

/DS

P47

P46

P45

P44

P43

P42

P41

P40

C_DIN

C_DOU

P25

PIN DESCRIPTION

(Continued)

Z89168 84-Pin PLCC Pin Identification

Z89165/166/167/168/169

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ONTROLLERS

CP96TAD0103

ILOG

PIN DESCRIPTION

(Continued)

Z89168 84-Pin PLCC Pin Identification

I/O Port
Functions

Pin Number

I/O

Function

32, 54, 65

Digital Ground

12, 44, 74, 45

Digital VCC = +5 V

P00-P07

43-36

Input/Output

P00-P07 (General-purpose nibble programmable I/O port.)

P10-P17

55, 53-51, 49-46

Input/Output

P10-P17 (General-purpose byte programmable I/O port.)

P20-P27

2-9

Input/Output

P20-P27 (General-purpose bit programmable I/O.)

P31-P37

57-63

Input/Output

P31-P37 (General-purpose I/O port. Bits P31-P33 are inputs, while
bits P34-P37 are outputs.)

P40-P47

77-84

Input/Output

P40-P47 (General-purpose bit programmable I/O.)

P50-P53

70-67

Input/Output

P50-P53 (General-purpose bit programmable I/O.)

C_DIN

Input

Data input from CODEC.

C_DOUT

Output

Data output to CODEC.

C_CLOCK

Output

CODEC clock (2.048 MHz)

C_ENA0

Output

CODEC 0 enable (8 kHz)

C_ENA1

Output

CODEC 1 enable (8 kHz)

PWM

Output

Pulse Width Modulator output

DATA0

Input/Output

Data 0 I/O of the ARAM Interface

DATA1

Input/Output

Data 1 I/O of the ARAM Interface

DATA2

Input/Output

Data 2 I/O of the ARAM Interface

DATA3

Input/Output

Data 3 I/O of the ARAM Interface

ADDR0

Output

Address 0 line of the ARAM Interface

ADDR1

Output

Address 1 line of the ARAM Interface

ADDR2

Output

Address 2 line of the ARAM Interface

ADDR3

Output

Address 3 line of the ARAM Interface

ADDR4

Output

Address 4 line of the ARAM Interface

ADDR5

Output

Address 5 line of the ARAM Interface

ADDR6

Output

Address 6 line of the ARAM Interface

ADDR7

Output

Address 7 line of the ARAM Interface

ADDR8

Output

Address 8 line of the ARAM Interface

ADDR9

Output

Address 9 line of the ARAM Interface

ADDR10

Output

Address 10 line of the ARAM Interface for 4 Meg ARAMs. Select 2
output of ARAM Interface for 1 Meg ARAMs support. The latter
mode is used to switch between different pages of ARAM.

ARAM_SEL0

Output

Select 0 output of ARAM Interface. Used to switch between
different pages of ARAM.

ARAM_SEL1

Output

Select 1 output of ARAM Interface. Used to switch between
different pages of ARAM.

/RAS

Output

Row Address Strobe of ARAM Interface.

/CAS

Output

Column Address Strobe of ARAM Interface.

ARAM_R/W

Output

Read/Write Strobe of ARAM Interface.

ARAM_/OE

Output

Output Enable Strobe of ARAM Interface.

XTAL1

Input

24.57 MHz crystal input

XTAL2

Output

24.57 MHz crystal output

/Reset

Input

/RESET input

R/W

Output

external memory interface R/W output

/AS

Output

Z8 external memory interface /AS output

/DS

Output

Z8 external memory interface /DS output

Z89165/166/167/168/169

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ONTROLLERS

ILOG

CP96TAD0103

1 84

Z89C169/Z89C167

84-Pin PLCC

42 43

VCC

ADDR0

ADDR1

ADDR2

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ARAM_SEL0

ARAM_SEL1

DATA0

DATA1

DATA2

DATA3

/RAS

/CAS

GND

VCC

C_CLOCK

C_EN0

C_EN1

P50

P51

P52

P53

OUT_5V

GND

/AS

P37

P36

P35

P34

P33

P32

P31

PWM

P10

GND

P11

P12

P13

R/W

P14

P15

P16

P17

RMLS

VCC

P00

P01

P02

P03

P04

P05

P06

P07

/RESET

ARAM_R/W

ARAM_OE

ADDR3

AL1

AL2

P27

P26

P24

P23

P22

P21

P20

/DS

P47

P46

P45

P44

P43

P42

P41

P40

C_DIN

C_DOU

P25

PIN DESCRIPTION

(Continued)

Z89167/169 84-Pin PLCC Pin Identification

Z89165/166/167/168/169

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ONTROLLERS

CP96TAD0103

ILOG

PIN DESCRIPTION

(Continued)

Z89169/Z89167 84-Pin PLCC, Pin Identification

I/O Port
Functions

Pin Number

I/O

Function

32, 54, 65

Digital Ground

12, 44, 74

Digital VCC = +5 V

P00-P07

43-36

Input/Output

P00-P07 (General-purpose nibble programmable I/O port.)

P10-P17

55, 53-51, 49-46

Input/Output

P10-P17 (General-purpose byte programmable I/O port.)

P20-P27

2-9

Input/Output

P20-P27 (General-purpose bit programmable I/O.)

P31-P37

57-63

Input/Output

P31-P37 (General-purpose I/O port. Bits P31-P33 are inputs, while
bits P34-P37 are outputs.)

P40-P47

77-84

Input/Output

P40-P47 (General-purpose bit programmable I/O.)

P50-P53

70-67

Input/Output

P50-P53 (General-purpose bit programmable I/O.)

C_DIN

Input

Data input from CODEC.

C_DOUT

Output

Data output to CODEC.

C_CLOCK

Output

CODEC clock (2.048 MHz)

C_ENA0

Output

CODEC 0 enable (8 kHz)

C_ENA1

Output

CODEC 1 enable (8 kHz)

PWM

Output

Pulse Width Modulator output

DATA0

Input/Output

Data 0 I/O of the ARAM Interface

DATA1

Input/Output

Data 1 I/O of the ARAM Interface

DATA2

Input/Output

Data 2 I/O of the ARAM Interface

DATA3

Input/Output

Data 3 I/O of the ARAM Interface

ADDR0

Output

Address 0 line of the ARAM Interface

ADDR1

Output

Address 1 line of the ARAM Interface

ADDR2

Output

Address 2 line of the ARAM Interface

ADDR3

Output

Address 3 line of the ARAM Interface

ADDR4

Output

Address 4 line of the ARAM Interface

ADDR5

Output

Address 5 line of the ARAM Interface

ADDR6

Output

Address 6 line of the ARAM Interface

ADDR7

Output

Address 7 line of the ARAM Interface

ADDR8

Output

Address 8 line of the ARAM Interface

ADDR9

Output

Address 9 line of the ARAM Interface

ADDR10

Output

Address 10 line of the ARAM Interface for 4 Meg ARAMs. Select 2
output of ARAM Interface for 1 Meg ARAMs support. The latter
mode is used to switch between different pages of ARAM.

ARAM_SEL0

Output

Select 0 output of ARAM Interface. Used to switch between
different pages of ARAM.

ARAM_SEL1

Output

Select 1 output of ARAM Interface. Used to switch between
different pages of ARAM.

/RAS

Output

Row Address Strobe of ARAM Interface.

/CAS

Output

Column Address Strobe of ARAM Interface.

ARAM_R/W

Output

Read/Write Strobe of ARAM Interface.

ARAM_/OE

Output

Output Enable Strobe of ARAM Interface.

XTAL1

Input

24.57 MHz crystal input

XTAL2

Output

24.57 MHz crystal output

ROMLESS

Input

Romless mode input (P0 and P1 are switched to D/A mode if

this pin is connected to VCC). Internally this pin is tight to GND.

/Reset

InputOutput

/RESET input/output

R/W

Output

Z8 external memory interface R/W output

/AS

Output

Z8 external memory interface /AS output

/DS

Output

Z8 external memory interface /DS output

Z89165/166/167/168/169

DTAD C

ONTROLLERS

ILOG

CP96TAD0103

Notes:

Voltage on all pins with respect to GND.

See Ordering Information.

Symbol

Description

Min

Max

Units

Supply Voltage (*)

0.3

+7.0

STG

Storage Temp

+150

Oper Ambient Temp

Power Dissipation

2.2

Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended
period may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load
Diagram).

+5V

From Output

Under Test

150 pF

9.1 k

2.1 k

Test Load Diagram

CAPACITANCE

= 25

C, V

= GND = 0V, f = 1.0 MHz, unmeasured pins to GND.

Parameter

Max

Input capacitance

12 pF

Output capacitance

12 pF

I/O capacitance

12 pF

DC ELECTRICAL CHARACTERISTICS

= 0

C to +70

Typical

Sym

Parameter

Note [1]

Min

Max

@ 25

Units

Notes

Supply Current

5.0 V

CC1

Halt Mode Current

5.0 V

CC2

Stop Mode Current

[2]

Notes:

[1] 5.0V

0.5V.

[2] The typical Stop Mode Current value is 500

A. The transient characteristics of the Stop Mode Current will vary according to the application and

should be validated in the specific application by the customer.

Z89165/166/167/168/169

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CP96TAD0103

ILOG

DC ELECTRICAL CHARACTERISTICS
Z89165/Z89166

= 0

Typical

to +70

Sym

Parameter

Note [1]

Min

Max

Units

Conditions

MAX

Max Input Voltage

5.0V

= 250

Clock Input High Voltage

5.0V

0.9 V

+0.3

2.5

Driven by External Clock Generator

Clock Input Low Voltage

5.0V

GND-0.3

0.1 V

1.5

Driven by External Clock Generator

Input High Voltage

5.0V

0.7 V

+0.3

2.5

Input Low Voltage

5.0V

GND-0.3

0.2 V

1.5

Output High Voltage

5.0V

-0.4

4.8

= -2.0 mA (Does not include XTAL2)

OL1

Output Low Voltage

5.0V

0.4

0.1

= +4.0 mA

OL2

Output Low Voltage

5.0V

1.2

0.3

= +12 mA, 3 Pin Max

(Does not include XTAL2)

Reset Input High Voltage

5.0V

0.8 V

2.1

Reset Input Low Voltage

5.0V

GND-0.3

0.2 V

1.7

OFFSET

Comparator Input Offset

5.0V

Voltage

Input Leakage

5.0V

-5

= OV, V

Output Leakage

5.0V

-5

= OV, V

Reset Input Current

5.0V

-55

-30

Notes:

[1] 5.0

10% (V).

Z89165/166/167/168/169

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CP96TAD0103

Z891650A ADDITIONAL DC ELECTRICAL CHARACTERISTICS

1. A/D CONVERTER: ABSOLUTE INPUT CURRENT VALUES

S y m b o l

P a r a m e t e r

M a x i m u m

N o t e s

Anin

input

Vref+

1.1 mA

With Vref = 0V

Vref+ = 5.5V

With Vref = Vref+ Vref+ = 5.5V

input

Vref

1.1 mA

With Vref+ = 5.5V

Vref = 0V

With Vref+ = Vref+ Vref = 0V

The following parameters should be verified on the ATE under
these conditions: 5.5V @ 25

2. OTHER PINS

Pin Under Test V a l u e

A d d i t i o n a l

C o n d i t i o n

Romless Pin
I

(max) =

No Reset

(max) =

No Reset

(max) =

1mA

During Reset

XTAL1
I

(max) =

While XTAL2 = 0V

No Reset

(max) =

While XTAL2 = 5.5V

No Reset

XTAL2
I

(max) =

While XTAL1 = 0V

Stop Mode Invoked

(max) =

While XTAL2 = 5V

Stop Mode Invoked

(max) =

1 mA

While XTAL1 = 0V

No Reset

(max) =

1 mA

While XTAL2 = 5V

No Reset

(max) =

4 mA

While XTAL1 = 0V

During Reset

(max) =

4 mA

While XTAL2 = 5V

During Reset

(min) =

2 mA

= 1V

= 4.5V Temp = 70

(min) =

-1mA

= V

-1V

= 4.5V Temp = 70

(max) =

7 mA

= 1V

= 5.5V Temp = 0

(max) =

6mA

= V

-1V

= 5.5V Temp = 0

P31, P32, P33
I

(max) =

Z89165/166/167/168/169

DTAD C

ONTROLLERS

CP96TAD0103

ILOG

DC ELECTRICAL CHARACTERISTICS
Z89167/168/169

= 0

to +70

Typical

Units

Sym

Parameter

Min

Max

Conditions

Notes

Max Input Voltage

4.5V

250 uA

5.5V

250 uA

Clock Input High Voltage

4.5V

0.9 V

+0.3

1.3

Driven by External Clock Generator

5.5V

0.9 V

+0.3

2.5

Driven by External Clock Generator

Clock Input Low Voltage

4.5V

GND-0.3

0.1 V

0.7

Driven by External Clock Generator

5.5V

GND-0.3

0.1 V

1.5

Driven by External Clock Generator

Input High Voltage

4.5V

0.7 V

+0.3

1.3

5.5V

0.7 V

+0.3

2.5

Input Low Voltage

4.5V

GND-0.3

0.2 V

0.7

5.5V

GND-0.3

0.2 V

1.5

Output High Voltge

4.5V

-0.4

3.1

= -2.0 mA

[1]

5.5V

-0.4

4.8

= -2.0 mA

OL1

Output Low Voltage

4.5V

0.6

0.2

= +4.0 mA

5.5V

0.4

0.1

= +4.0 mA

OL2

Output Low Voltage

4.5V

1.2

0.3

= +6 mA, 3 Pin Max

5.5V

1.2

0.3

= +12 mA, 3 Pin Max

Reset Input High Voltage

4.5V

.8 V

1.5

5.5V

.8 V

2.1

Reset Input Low Voltage

4.5V

GND-0.3

0.2 V

1.1

5.5V

GND-0.3

0.2 V

1.7

OFFSET

Comparator Input Offset

4.5V

Voltage

5.5V

Input Leakage

4.5V

-5

= OV, V

5.5V

-5

= OV, V

Output Leakage

4.5V

-5

= OV, V

5.5V

-5

= OV, V

Reset Input Current

4.5V

-45

-20

5.5V

-55

-30

Note:

[1] P10, P11 are measured at 4.5V only.

Z89165/166/167/168/169

DTAD C

ONTROLLERS

CP96TAD0103

ILOG

AC CHARACTERISTICS
Z89165/166

External I/O or Memory Read and Write Timing Table

C to +70

Symbol

Parameter

Note [4]

Min

Max

Units

Notes

TdA(AS)

Address Valid to /AS Rise Delay

5.0V

[2,3]

TdAS(A)

/AS Rise to Address Float Delay

5.0V

[2,3]

TdAS(DR)

/AS Rise to Read Data Req'd Valid

5.0V

150

[1,2,3]

TwAS

/AS Low Width

5.0V

[2,3]

TdAZ(DS)

Address Float to /DS Fall

5.0V

-3

TwDSR

/DS (Read) Low Width

5.0V

125

[1,2,3]

TwDSW

/DS (Write) Low Width

5.0V

[1,2,3]

TdDSR(DR)

/DS Fall to Read Data Req'd Valid

5.0V

[1,2,3]

ThDR(DS)

Read Data to /DS Rise Hold Time

5.0V

[2,3]

TdDS(A)

/DS Rise to Address Active Delay

5.0V

[2,3]

TdDS(AS)

/DS Rise to /AS Fall Delay

5.0V

[2,3]

TdR/W(AS)

R//W Valid to /AS Rise Delay

5.0V

[2,3]

TdDS(R/W)

/DS Rise to R//W Not Valid

5.0V

[2,3]

TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay

5.0V

[2,3]

TdDS(DW)

/DS Rise to Write Data Not Valid Delay

5.0V

[2,3]

TdA(DR)

Address Valid to Read Data Req'd Valid

5.0V

180

[1,2,3]

TdAS(DS)

/AS Rise to /DS Fall Delay

5.0V

[2,3]

TdDI(DS)

Data Input Setup to /DS Rise

5.0V

[1,2,3]

TdDM(AS)

/DM Valid to /AS Fall Delay

5.0V

[2,3]

Notes:

[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.
[4] 5.0 V

0.5 V.

Standard Test Load
All timing references use 0.9 V

for a logic 1 and 0.1 V

for a logic 0.

Z89165/166/167/168/169

DTAD C

ONTROLLERS

ILOG

CP96TAD0103

AC CHARACTERISTICS
Z89167/168/169

External I/O or Memory Read and Write Timing Table

C to +70

Symbol

Parameter

Note [4]

Min

Max

Units

Notes

TdA(AS)

Address Valid to /AS Rise Delay

5.0V

[2,3]

TdAS(A)

/AS Rise to Address Float Delay

5.0V

[2,3]

TdAS(DR)

/AS Rise to Read Data Req'd Valid

5.0V

130

[1,2,3]

TwAS

/AS Low Width

5.0V

[2,3]

TdAZ(DS)

Address Float to /DS Fall

5.0V

TwDSR

/DS (Read) Low Width

5.0V

[1,2,3]

TwDSW

/DS (Write) Low Width

5.0V

[1,2,3]

TdDSR(DR)

/DS Fall to Read Data Req'd Valid

5.0V

[1,2,3]

ThDR(DS)

Read Data to /DS Rise Hold Time

5.0V

[2,3]

TdDS(A)

/DS Rise to Address Active Delay

5.0V

[2,3]

TdDS(AS)

/DS Rise to /AS Fall Delay

5.0V

[2,3]

TdR/W(AS)

R//W Valid to /AS Rise Delay

5.0V

[2,3]

TdDS(R/W)

/DS Rise to R//W Not Valid

5.0V

[2,3]

TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay

5.0V

[2,3]

TdDS(DW)

/DS Rise to Write Data Not Valid Delay

5.0V

[2,3]

TdA(DR)

Address Valid to Read Data Req'd Valid

5.0V

160

[1,2,3]

TdAS(DS)

/AS Rise to /DS Fall Delay

5.0V

[2,3]

TdDI(DS)

Data Input Setup to /DS Rise

5.0V

[1,2,3]

TdDM(AS)

/DM Valid to /AS Fall Delay

5.0V

[2,3]

Notes:

[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.
[4] 5.0 V

0.5 V.

Standard Test Load
All timing references use 0.9 V

for a logic 1 and 0.1 V

for a logic 0.

Z89165/166/167/168/169

DTAD C

ONTROLLERS

ILOG

CP96TAD0103

AC ELECTRICAL CHARACTERISTICS
Z89165/166

Additional Timing Table

C to +70

No Symbol

Parameter

Note [6]

Min

Max

Units

Notes

TpC

Input Clock Period

5.0 V

48.83

[1]

TrC,TfC

Clock Input Rise & Fall Times

5.0 V

[1]

TwC

Input Clock Width

5.0 V

[1]

TwTinL

Timer Input Low Width

5.0 V

TwTinH

Timer Input High Width

5.0 V

3TpC

[1]

TpTin

Timer Input Period

5.0 V

8TpC

[1]

TrTin,

Timer Input Rise & Fall Timer

5.0 V

100

[1]

TfTin

8A TwIL

Int. Request Low Time

5.0 V

[1,2]

8B TwIL

Int. Request Low Time

5.0 V

3TpC

[1]

TwIH

Int. Request Input High Time

5.0 V

3TpC

[1]

10 Twsm

Stop-Mode Recovery Width Spec

5.0 V

[1]

5TpC

11 Tost

Oscillator Startup Time

5.0 V

5TpC

[3]

12 Twdt

Watch-Dog Timer

5.0 V

D1=0, D0 = 0 [4]

5.0 V

D1=0, D0 = 1 [4]

5.0 V

D1=1, D0 = 0 [4]

5.0 V

D1=1, D0 = 1 [4]

Notes:

[1] Timing Reference uses 0.9 V

for a logic 1 and 0.1 V

for a logic 0.

[2] Interrupt request via Port 3 (P31-P33).
[3] SMR-D5 = 0.
[4] Reg. WDT.
[5] 5.0V

0.5V.

Z89165/166/167/168/169

DTAD C

ONTROLLERS

CP96TAD0103

ILOG

AC ELECTRICAL CHARACTERISTICS
Z89167/168/169

Additional Timing Table

C to +70

Symbol

Parameter

Note [5]

Min

Max

Units

Notes

TpC

Input Clock Period

5.0 V

41.67

[1]

TrC,TfC

Clock Input Rise & Fall Times

5.0 V

[1]

TwC

Input Clock Width

5.0 V

[1]

TwTinL

Timer Input Low Width

5.0 V

TwTinH

Timer Input High Width

5.0 V

3TpC

[1]

TpTin

Timer Input Period

5.0 V

8TpC

[1]

TrTin,

Timer Input Rise & Fall Timer

5.0 V

100

[1]

TfTin

TwIL

Int. Request Low Time

5.0 V

[1,2]

TwIL

Int. Request Low Time

5.0 V

3TpC

[1]

TwIH

Int. Request Input High Time

5.0 V

3TpC

[1]

Twsm

Stop-Mode Recovery Width Spec

5.0 V

[1]

5TpC

Tost

Oscillator Startup Time

5.0 V

5TpC

[3]

Twdt

Watch-Dog Timer

5.0 V

D1=0, D0 = 0 [4]

5.0 V

D1=0, D0 = 1 [4]

5.0 V

D1=1, D0 = 0 [4]

5.0 V

100

D1=1, D0 = 1 [4]

Notes:

[1] Timing Reference uses 0.9 V

for a logic 1 and 0.1 V

for a logic 0.

[2] Interrupt request via Port 3 (P31-P33).
[3] SMR-D5 = 0.
[4] Reg. WDT.
[5] 5.0V

0.5V.

Z89165/166/167/168/169

DTAD C

ONTROLLERS

CP96TAD0103

ILOG

AC ELECTRICAL CHARACTERISTICS
Z89165/166

Handshake Timing Table

C to +70

Data

Symbol

Parameter

Note [1]

Min

Max

Units

Direction

TsDI(DAV)

Data In Setup Time

5.0 V

ThDI(RDY)

RDY to Data Hold Time

5.0 V

TwDAV

Data Available Width

5.0 V

TdDAVI(RDY)

DAV Fall to RDY Fall Delay

5.0 V

TdDAVId(RDY)

DAV Rise to RDY Rise Delay

5.0 V

TdDO(DAV)

RDY Rise to DAV Fall Delay

5.0 V

TcLDAV0(RDY)

Data Out to DAV Fall Delay

5.0 V

TpC

OUT

TcLDAV0(RDY)

DAV Fall to RDY Fall Delay

5.0 V

OUT

TdRDY0(DAV)

RDY Fall to DAV Rise Delay

5.0 V

OUT

10 TwRDY

RDY Width

5.0 V

OUT

11 TdRDY0d(DAV)

RDY Rise to DAV Fall Delay

5.0 V

OUT

Notes:

[1] 5.0 V

0.5 V

AC ELECTRICAL CHARACTERISTICS
Z89167/168/169

Handshake Timing Table

C to +70

Data

Symbol

Parameter

Note [1]

Min

Max

Units

Direction

TsDI(DAV)

Data In Setup Time

5.0 V

ThDI(RDY)

Ready to Data In Hold Time

5.0 V

TwDAV

Data Available Width

5.0 V

110

TdDAVI(RDY)

DAV Fall to RDY Fall Delay

5.0 V

115

TdDAVId(RDY)

DAV Rise to RDY Rise Delay

5.0 V

TdDO(DAV)

RDY Rise to DAV Fall Delay

5.0 V

TcLDAV0(RDY)

Data Out to DAV Fall Delay

5.0 V

OUT

TcLDAV0(RDY)

DAV Fall to RDY Fall Delay

5.0 V

OUT

TdRDY0(DAV)

RDY Fall to DAV Rise Delay

5.0 V

115

OUT

10 TwRDY

RDY Width

5.0 V

OUT

11 TdRDY0d(DAV)

RDY Rise to DAV Fall Delay

5.0 V

OUT

Notes:

[1] 5.0 V

0.5 V

Z89165/166/167/168/169

DTAD C

ONTROLLERS

ILOG

CP96TAD0103

ELECTRICAL CHARACTERISTICS
Z89165/166 A/D CONVERTER

A/D Converter Electrical Characteristics

= 5.0V

10%

Parameter

Minimum

Typical

Maximum

Units

Resolution

Bits

Integral non-linearity

0.5

LSB

Differential non-linearity

0.5

LSB

Zero Error at 25

250

Supply Range

4.5

5.0

5.5

Volts

Input voltage range

Volts

Conversion time

sec

Input capacitance on ANA

range

+2.5

Volts

range

GND

2.5

Volts

-VA

2.5

Volts

Notes:

Voltage 4.5V 5.5V
Temp 0-70

Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com

© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: Z89166

Document Outline

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