1
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
GENERAL DESCRIPTION
DC-4222-03
(10-10-94)
The Z89303/05/07 Digital Television Controllers are
application-specific controllers designed to provide
complete audio and video control of television receivers,
video recorders, with advanced on-screen display facilities.
The Z89303/05/07 are 24K, 16K and 12K ROM versions in
52-pin SDIP packages. The powerful 12 MHz Z89C00
RISC processor core allows the user to control the on-
board peripheral functions and registers using the standard
processor instruction set.
The extensive character attributes can be controlled in two
modes: by the on-screen display controller character
control mode for maximum display control flexibility, and
closed caption mode for optimum display of closed caption
text.
Closed caption text can be decoded directly from the
composite video signal with the assistance of the
processor's digital signal processing capabilities and
displayed on the screen. The character representation in
this mode allows for a simple attribute control through the
insertion of control characters, and each word of RAM
specifies two displayed characters.
The character control mode provides access to the full set
of attribute controls. Each word of RAM specifies a single
displayed character and basic character attributes, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that incude underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency. The 16-bit
display character representation allows the modification of
some key attributes on a character-by-character basis. A
character's pixel array is stored as a 16- or 18-word
representation in Character Graphics ROM (CGROM).
The ROM contents are referenced by a 16-bit word stored
in video RAM (VRAM) defining the character type and its
key attributes.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry standard I
2
C port.
Additional hardware provides the capability to display two
times normal size characters. The smoothing logic
contained in the on-screen display circuit improves the
appearance of larger fonts. Fringing circuitry can be
activated to improve the visibiity of text by surrounding the
character lines with a one-pixel border.
RGB outputs provide the direct video signals, and a
blanking output is provided to control the video multiplexor.
Dot clock and verticle line synchronization are normally
obtained from H_FLYBACK and V_FLYBACK, but can be
generated by the Z89303/05/047, and driven to the external
deflection unit through the bidirectional SYNC ports when
external video synchronization signals are not present.
User control can be monitored through the keypad scanning
port, or the 16-bit remote control capture register. Receiver
functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
All nine PWM ports are available in the 52-pin package.
The Z89303/05/07 has two internal 12 MHz VCOs that are
referenced to a 32 KHz internal oscillator to provide the
system clock. In Sleep mode, the controller uses the 32
KHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP mode when main power is not available for
minimal power consumption.
Z89303/05/07
DIGITAL TELEVISION CONTROLLER
2
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
GENERAL DESCRIPTION
(Continued)
Functional Block Diagram
Capture
IRIN
ADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F
Control
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
CPU
RAM
640 x 16
ROM
12K x 16
16K x 16
24K x 16
OSD
V1
V2
V3
BLANK
HALFBLNK
PWM
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
Port1
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 19
Port 17
Port 00
Register Addr/Data
Address
Data
ROM Data
ROM Addr
Note: Z89307
has 12K words of ROM.
Z89305 has 16K words.
Z89302/03 has 24K words.
Note: Shaded pin functions
not available on 40-pin device.
Port0F
3
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
52-Pin Shrink DIP Configuration
1
2
9
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
14
10
11
12
13
15
16
17
18
19
20
37
36
35
34
33
32
Z89303
Z89305
Z89307
52-Pin
Shrink
DIP
PWM9
IRIN
Port18/G<0>
Port19
Port0E
Port00/ADC2
Port01/I2SSC
Port02/I2SSD
Port03
GND
Port04/ADC4
Port05/ADC3
Port06/Counter
Port07/CSync
Port08/R<1>
Port09
VCC
Port10/R<0>
Port11/I2MSC
Port12/I2MSD
PWM8
PWM7
PWM6
Port14/B<0>
ADC5
CVI/ADC0
XTAL1
LPF
Port0F/HalfBlnk
/Reset
Port17/ADC1
Blank
V1
21
22
23
24
25
31
30
29
28
27
26
52
Port15/B<1>
Port13/G<1>
V3
V2
AN GND
XTAL2
Port16/SCLK
Port0A
Port0B
PWM5
PWM4
PWM3
PWM2
PWM1
AN VCC
VSync
HSync
Port0D
Port0C
4
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
PIN DESCRIPTIONS
Z89303/05/07
Pin
Z89303/05/07
Configuration
Name
Function
52-Pin
Direction
Reset
V
CC
+5 V
17,38
PWR
GND
0 V
10,40
PWR
IRIN
Infrared Remote Capture Input
2
I
I
ADC[5:0]
a
4-Bit Analog to Digital Converter 44,11,12,6,35,43
nAI
I
Input
b
PWM10,
14-Bit Pulse Width Modulator
,1
OD
O
PWM9
Output
PWM[8:1]
c
8-Bit Pulse Width Modulator
52,51,50,49,
OD
O
Output
48,47,46,45
Port0[F:0]
d
Bit Programmable
36,5,28,27,26,25,
B
I
Input/Output Ports
16,15,14,13,12,
11,9,8,7,6
Port1[9:0]
c
Bit Programmable
4,3,35,24,23,22,
B
I
Input/Output Ports
21,20,19,18
SCLf
12C Clock I/O
7 or 19
BOD
SCD
g
12C Data I/O
8 or 20
BOD
XTAL1
Crystal Oscillator Input
3 9
AI
I
XTAL2
Crystal Oscillator Output
4 1
AO
O
LPF
Loop Filter
4 2
AB
O
HSYNC
H_Sync
2 9
B
I
VSYNC
V_Sync
3 0
B
I
/RESET
Device Reset
3 7
I
I
V[3:1]
OSD Video Output
31,32,33
O
O
(Typically Drive B, G, and R Outputs)
Blank
OSD Blank Output
3 4
O
O
Half Blank
h
OSD Half Blank Output
3 6
O
RGB Digital
R[1:0],G[1:0], and B[1:0]
23,22,21,
O
Outputs
i
Outputs of the RGB Matrix
18,15,3
SCLK
k
Internal Processor SCLK
2 4
O
5
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
V1, V2, V3 ANALOG OUTPUT
Specifications V
CC
= 5.25 V
V
CC
= 5.25 V
Condition
Limit
Output Voltage
Bit = 11
4.55 V +/ 0.25 V
Bit = 10
3.205V +/ 0.2 V
Bit = 01
1.95 V +/ 0.15 V
Bit = 00
0.65 V +/ 0.1 V
Settling Time
70% of DC Level, 10pf Load
< 50 nsec
V1, V2, V3 ANALOG OUTPUT
Specifications V
CC
= 4.75V
V
CC
= 4.75V
Condition
Limit
Output Voltage
Bit = 11
3.90 V +/ 0.25 V
Bit = 10
2.90 V +/ 0.2 V
Bit = 01
1.90 V +/ 0.15 V
Bit = 00
0.1 V +/ 0.1 V
Settling Time
70% of DC Level, 10pf Load
< 50 nsec
32K Oscillator Recommended Circuit
Notes:
c) PWM[8,7] is not available on the 40-pin DIP version.
d) Port0[F:A] is not available on the 40-pin DIP version.
e) Port19 is not available on the 40-pin DIP version.
f) SCL I/O pin is shared with Port0 or Port11.
g) SCD I/O pin is shared with Port02 or Port12.
h) Half Blank output is a function shared with Port0F.
Half Blank output is not available on the 40-pin DIP version.
i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
k) Internal processor SCLK is shared with Port16.
Z893XX
6
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
Conditions
V
CC
Power Supply Voltage
0
7
V
V
ID
Input Voltage
0.3
V
CC
+0.3
V
Digital Inputs
V
IA
Input Voltage
0.3
V
CC
+0.3
V
Analog Inputs (A/D0...A/D4)
V
O
Output Voltage
0.3
V
CC
+0.3
V
All Push-Pull Digital Output
V
O
Output Voltage
0.3
V
CC
+8.0
V
Open-Drain PWM Outputs
(PWM1...PWM8)
I
OH
Output Current High
10
mA
One Pin
I
OH
Output Current High
100
mA
All Pins
I
OL
Output Current Low
20
mA
One Pin
I
OL
Output Current Low
200
mA
All Pins
T
A
Operating Temperature
0
7 0
C
T
A
Storage Temperature
65
150
C
DC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= 4.5 V to + 5.5 V; F
OSC
= 32.768 KHz
Symbol
Parameter
Min
Max
Typical
Units
Conditions
V
IL
Input Voltage Low
0
0.2 V
CC
0.4
V
V
IH
Input Voltage High
0.6 V
CC
V
CC
3.6
V
V
PU
Max. Pull-Up Voltage
1 2
V
PWM0...PWM8 Only
V
OL
Output Voltage Low
0.4
0.16
V
@ I
OL
= 1 mA
V
OL
Output Voltage High
V
CC
0.9
4.75
V
@ I
OL
= 0.75 mA
V
XL
Input Voltage XTAL1 Low
0.3 V
CC
1.0
V
External Clock
V
XH
Input Voltage XTAL1 High
V
CC
2.0
3.5
V
Generator Driven
V
HY
Schmitt Hysteresis
3.0
0.75
0.5
V
On XTAL1 Input Pin
I
IR
Reset Input Current
150
90
A
V
RL
= 0 V
I
IL
Input Leakage
3.0
3.0
0.01
A
@ 0 V and V
CC
I
CC
Supply Current
100
6 0
mA
I
CC1E
Supply Current of the OTP
700
300
A
Sleep Mode @ 32 KHz
I
CC1
Supply Current
300
100
A
Sleep Mode @ 32 KHz
I
CC2
Supply Current
1 0
5
A
Sleep Mode
7
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
AC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= 4.5 V to 5.5 V; F
OSC
= 32.768 KHz
Symbol
Parameter
Min
Max
Typical
Units
T
P
C
Input Clock Period
16
100
32
S
T
R
C,T
F
C
Clock Input Rise and Fall
12
S
T
D
POR
Power On Reset Delay
0.8
1.2
s
AC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= 4.5 V to 5.5 V; F
OSC
= 32.768 KHz
Symbol
Parameter
Min
Max
Typical
Units
T
W
RES
Power-On Reset Min. Width
5TPC
S
T
D
H
S
H_Sync Incoming Signal Width
5.5
12.5
1 1
S
T
D
V
S
V_Sync Incoming Signal Width
0.15
1.5
1.0
m S
T
D
E
S
Time Delay Between Leading Edge
12
+ 1 2
0
S
of V_Sync and H_Sync in Even Field
T
D
O
S
Time Delay Between Leading Edge
2 0
4 4
3 2
S
of H_Sync in Odd Field
T
W
HV
S
H_Sync/V_Sync Edge Width
2.0
0.5
S
Notes:
All timing of the I
2
C bus interface are defined by related specifications
of the I
2
C bus interface.
8
P R E L I M I N A R Y
Z89303/05/07
CPS DC-4222-03
Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
1994 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-con-
formance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
and delays. No production release is authorized or com-
mitted until the Customer and Zilog have agreed upon a
Customer Procurement Specification for this project.
Development Projects:
Customer is cautioned that while reasonable efforts will be
employed to meet performance objectives and milestone
dates, development is subject to unanticipated problems
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