1
P R E L I M I N A R Y
Z89331
CP95TEL1400
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
CP95TEL1400 11/95
FEATURES
n
Part
ROM
RAM*
Speed
Number
(KB)
(Bytes)
(MHz)
Z89331
2 4
640
1 2
*General-Purpose
n
42-Pin SDIP Package
n
4.75- to 5.25-Volt Operating Range
n
0
C to +70
C Temperature Range
n
One-Time Programmable
Z89331
OTP DIGITAL
TELEVISION CONTROLLER
n
Serial Interfacing I
2
C Port
n
Fully Customized Character Set
n
Character-Control and Closed-Caption Modes
n
Keypad User Control
n
TV Tuner Serial Interface
n
Direct Video Signals
n
Low-EMI Option
GENERAL DESCRIPTION
The Z89331 One-Time Programmable (OTP) Digital
Television Controller is designed to provide complete
audio and video control of television receivers, video
recorders, and advanced on-screen display facilities. The
Z89331 features a Z89C00 RISC processor core that
controls on-board peripheral functions and registers using
the standard processor instruction set.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes. Closed-caption text can be
decoded directly from the composite video signal and
displayed on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry-standard I
2
C port.
User control can be monitored through the keypad scanning
port, or the 16-bit remote control capture register. Receiver
functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
2
P R E L I M I N A R Y
Z89331
CP95TEL1400
GENERAL DESCRIPTION
(Continued)
Capture
IRIN
ADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F
Control
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
CPU
Z89C00
Core
RAM
640 x 16
ROM
12K x 16
16K x 16
24K x 16
OSD
V1
V2
V3
BLANK
HALFBLNK
PWM
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
Port1
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 19
Port 17
Port 00
Port 05
Port 04
Register Addr/Data
Address
Data
ROM Data
ROM Addr
Note: Dotted pin functions
not available on 42-pin device.
Port0F
I2C
SCL
SCD
Port 01/11
Port 02/12
Functional Block Diagram
3
P R E L I M I N A R Y
Z89331
CP95TEL1400
1
2
9
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
14
10
11
12
13
15
16
17
18
19
20
26
25
24
23
22
21
Z89331
42-Pin
Shrink
DIP
PWM10
PWM9
PWM5
PWM4
PWM3
PWM2
PWM1
Port 03
Port 04/ADC4
Port 05/ADC3
Port 00/ADC2
Port 17/ADC1
GND
Port 10/R<0>
Port 06/Counter
Port 18/G<0>
Port 13/G<1>
Port 14/B<0>
Port 15/B<1>
Port 16/SCLK
Port12/I2MSD
Port 11/12MSC
Port 02/I2SSD
Port 09
Port 08/R<1>
IRIN
Port 07/CSync
/Reset
XTAL2
Port 01/I2SSC
XTAL1
VCC
ANGND
CVI/ADC0
VBlank
V1
V2
V3
VSync
HSync
41
42
Port 0F/HalfBlnk
LPF
42-Pin Shrink DIP Pin Configuration
4
P R E L I M I N A R Y
Z89331
CP95TEL1400
PIN DESCRIPTIONS
Z89331
Pin
Z89331
Configuration
Name
Function
42-Pin SDIP
Direction
Reset
V
CC
+5 V
34
PWR
PWR
GND
0 V
13,30
PWR
PWR
IRIN
Infrared Remote Capture Input
36
I
I
ADC[5:0]
a
4-Bit Analog to Digital Converter
,9,10,11,12,2,8
AI
I
Input
b
PWM9
14-Bit Pulse Width Modulator
1,2
OD
O
Output
PWM[8:1]
c
8-Bit Pulse Width Modulator
,,,3,4
OD
OD
Output
5,6,7
Port0[F:0]
d
Bit Programmable
21,,,,,,
B
I
Input/Output Ports
38,37,35,,,
15,8,40,39,11
Port1[9:0]
e
Bit Programmable
,16,12,20,
B
I
Input/Output Ports
19,18,17,42,
41,14
MSSCL
f
I
2
C Clock I/O
4 1
BOD
MSSCD
g
I
2
C Data I/O
4 2
BOD
I
SSCL
h
I
2
C Clock I/O
3 9
BOD
I
SSCD
i
I
2
C Data I/O
4 0
BOD
I
XTAL1
Crystal Oscillator Input
3 1
AI
AI
XTAL2
Crystal Oscillator Output
3 2
AO
AO
LPF
Loop Filter
2 9
AB
AB
HSYNC
H_Sync
2 6
B
I
VSYNC
V_Sync
2 7
B
I
/RESET
Device Reset
3 3
I
I
V[3:1]
OSD Video Output
22,23,24
O
O
(Typically Drive B, G, and R Outputs)
Blank
OSD Blank Output
2 5
O
O
Half Blank
h
OSD Half Blank Output
2 1
O
I
RGB Digital
R[1:0],G[1:0], and B[1:0]
37,14,17,
O
I
Outputs
i
Outputs of the RGB Matrix
16,19,18
SCLK
k
Internal Processor SCLK
2 0
O
I
e) Port19 is not available on the 42-pin DIP version.
f) SCL I/O pin is shared with Port01 or Port11.
g) SCD I/O pin is shared with Port02 or Port12.
h) Half Blank output is a function shared with Port0F.
i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
k) Internal processor SCLK is shared with Port16.
Notes:
a) ADC1 input is shared with Port 17, ADC2 input Pin is shared with
Port 00. ADC3 input pin is shared with Port 05 and ADC4 input pin
is shared with Port 04.
b) ADC0 and ADC5 have a clamp circuit that facilitates Composite
video input.
c) PWM[8,7] is not available on the 42-pin DIP version.
d) Port0[F:A] is not available on the 42-pin DIP version.
5
P R E L I M I N A R Y
Z89331
CP95TEL1400
V1, V2, V3 ANALOG OUTPUT
Specifications V
CC
= 5.25 V
V
CC
= 5.25 V
Condition
Limit
Output Voltage
Bit = 11
3.9 V +/ 0.3 V
Bit = 10
3.0 V +/ 0.3 V
Bit = 01
1.8 V +/ 0.3 V
Bit = 00
0.6 V +/ 0.3 V
Settling Time
70% of DC Level, 10pf Load
< 50 nsec
V1, V2, V3 ANALOG OUTPUT
Specifications V
CC
= 4.75V
V
CC
= 4.75V
Condition
Limit
Output Voltage
Bit = 11
3.5 V +/ 0.3 V
Bit = 10
2.6 V +/ 0.3 V
Bit = 01
1.6 V +/ 0.3 V
Bit = 00
0.5 V +/ 0.3 V
Settling Time
70% of DC Level, 10pf Load
< 50 nsec
6
P R E L I M I N A R Y
Z89331
CP95TEL1400
DC CHARACTERISTICS
T
A
= 0
C to + 70
C; V
CC
= + 4.75 V to + 5.25V
TA = 0
to + 70
C
Typical
Symbol
Parameter
Min
Max
@ 25
C
Units
Conditions
V
IL
Input Voltage Low
0
0.2 V
CC
1.48
V
V
IH
Input Voltage High
0.7 V
CC
V
CC
3.0
V
V
HY
Schmitt Hysteresis
0.1 V
CC
0.8
V
V
PU
Maximum Pull-Up Voltage
13.2
V
[2]
V
OL
Output Voltage Low
0.4
0.16
V
I
OL
= 1.00 mA
0.4
0.19
V
I
OL
= mA, [1]
0.4
0.19
V
I
OL
=0.75 mA, [2]
V
OH
Output Voltage High
V
CC
0.4
4.75
V
I
OH
= 0.75 mA
I
IR
Reset Input Current
80
46
A
V
RL
= 0 V
I
IL
Input Leakage
3.0
3.0
0.01
A
0 V, V
CC
I
OL
Tri-State Leakage
3.0
3.0
0.02
A
0 V, V
CC
Note:
[1] Port 0, 1
[2] PWM Open-Drain
7
P R E L I M I N A R Y
Z89331
CP95TEL1400
Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
1995 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
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provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-con-
formance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
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