Z89390
CPS DC-9030-01
P R E L I M I N A R Y
DC 9030-00
1
Z
ILOG
The Z89390 is a CMOS Digital Signal Processor (DSP).
Single-cycle instruction execution and a Harvard bus
structure promotes efficient algorithm execution. The
processor contains 512 word data RAM and 64K word of
external program address space is accessible. Six register
pointers provide circular buffering capabilities and dual
operand fetching. Three vectored interrupts are
complemented by a six level stack. The CODEC interface
enables high-speed transfer rates to accommodate digital
audio and voice data. A dedicated Counter/Timer provides
the necessary timing signals for the CODEC interface. An
additional 13-bit timer is available for general-purpose
use.
The Z89390 is optimized to accommodate intricate signal
processing algorithms. The 20-MIP operating performance
and efficient architecture provides real-time execution.
Compression, filtering, frequency detection, audio, voice
detection/synthesis and other available algorithms can all
be accommodated. The on-board peripherals provide
additional cost advantages.
GENERAL DESCRIPTION
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z89390
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
Development tools for the IBM PC include a relocatable
assembler, a linker loader debugger.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
2
DC 9030-00
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GENERAL DESCRIPTION
(Continued)
Z89391 Functional Block Diagram
CODEC
Interface
Register
Pointer
0-2
16-Bit Bus
Stack
ACC
24-Bit Bus
ALU
B
A
256 Word
RAM
1
16 x16
Multiplier
Y
P
X
24-bit
Instruction
Register
256 Word
RAM
0
Register
Pointer
4-6
PC
16-bit
I/O
Port
MUX
D Bus
Status
(5)
Switch
Shifter
24
P Bus
EXT0-15
WAIT, RD/WR, /OS
EA0-2
Ready
Interrupt
16
3
3
UI0-1
UO0-1
2
2
User
Port
/INTO-2
/RESET
S-Bus
Switch
Note: EXT5, EXT6, and INTERRUPT1 are used for the CODEC Interface. EXT4 and
INTERRUPT2 are used for the 13-bit timer.
RXD
TXD
SCLK
FS0
FS1
13-Bit
Timer
EXT4
EXT5-1 EXT5-2
EXT6-1
EXT7-1
EXT6-2
EXT7-2
PD15-PD0
PA15-PA0
External Program ROM
16
16
16
16
PD
PA
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
DC 9030-00
3
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PIN DESCRIPTION
84-Pin PLCC Pin Assignments
1
84
33
42 43
32
53
54
11
12
75
74
VSS
EXT3
PA8
EXT4
PA9
VSSP
EXT5
PA10
EXT6
PA11
EXT7
TXD
PA12
EXT8
PA13
EXT9
VSS
PA14
EXT10
PA15
VCC
N/C
EXT15
PA
7
VSS
PA
6
EXT14
PA
5
EXT13
PA
4
EXT12
RXD
VSS
PA
3
EXT2
PA
2
EXT1
PA
1
EXT0
VSS
VCC
PA
0
VSS
PD15
UO1
PD13
UO0
PD12
INT0
FS0
HALT
PD11
CLK
/D5
PD10
VDDP
PD9
EA2
PD8
EA1
VDD
FS1
PD14
PD7
VCC
EA0
PD6
/RESET
PD5
W
AIT
PD4
RD//WR
VDD
SCLK
UI0
UI1
PD3
INT1
PD2
INT2
PD1
EXT1
1
PD0
VSS
Z89390
84-Pin PLCC
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
4
DC 9030-00
Z
ILOG
+5V
From Output
Under Test
30 pF
9.1 K
2.1 K
Symbol
Description
Min.
Max.
Units
V
CC
Supply Voltage (*)
0.3
+7.0
V
T
STG
Storage Temp
65
+150
C
T
A
Oper Ambient Temp
C
Notes:
* Voltage on all pins with respect to GND.
See Ordering Information.
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended period may affect
device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to ground.
Positive current flows into the referenced pin (Test Load).
. Test Load Diagram
DC ELECTRICAL CHARACTERISTICS
(V
DD
= 5V
10%, T
A
= 0
C to +70
C unless otherwise specified)
Symbol
Parameter
Condition
Min.
Max.
Typical
Units
I
DD
Supply Current
V
DD
= 5.25V
80
70
mA
fclock = 20 MHz
I
DC
DC Power Consumption
V
DD
= 5.25V
5
mA
V
IH
Input High Level
2.5
V
V
IL
Input Low Level
0.8
V
IL
Input Leakage
10
A
V
OH
Output High Voltage
I
OH
= 100
A
V
DD
0.2
V
V
OL
Output Low Voltage
I
OL
= 2.0 mA
0.5
V
I
FL
Output Floating Leakage Current
5
A
ABSOLUTE MAXIMUM RATINGS
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
DC 9030-00
5
Z
ILOG
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 5V 10%, T
A
= 0
C to +70
C unless otherwise specified)
Symbol
Parameter
Min (ns)
Max (ns)
Clock
TCY
Clock Cycle Time
50
Tr
Clock Rise Time
2
Tf
Clock Fall Time
2
CPW
Clock Pulse Width
23
I/O
DSSET
/DS Setup Time from CLOCK Fall
0
15
DSHOLD
/DS Hold Time from CLOCK Rise
4
15
EASET
EA Setup Time to /DS Fall
12
EAHOLD
EA Hold Time from /DS Rise
4
RDSET
Data Read Setup Time to /DS Rise
14
RDHOLD
Data Read Hold Time from /DS Rise
6
WRSET
Data Write Setup Time to /DS Rise
18
WRHOLD
Data Write Hold Time from /DS Rise
5
Interrupt
INTSET
Interrupt Setup Time to CLOCK Fall
7
INTWIDTH
Interrupt Low Pulse Width
1 TCY
Codec Interface
SSET
SCLK Setup Time from Clock Rise
15
FSSET
FSYNC Setup Time from SCLK Rise
6
TXSET
TXD Setup Time from SCLK Rise
7
RXSET
RXD Setup Time to SCLK Fall
7
RXHOLD
RXD Hold Time from SCLK Fall
0
Reset
RRISE
Reset Rise Time
1000
RSET
Reset Setup Time to CLOCK Rise
15
RWIDTH
Interrupt Low Pulse Width
2 TCY
External Program Memory
PASET
PA Setup Time from CLOCK Rise
5
PDSET
PD Setup Time to CLOCK Rise
10
PDHOLD
PD Hold Time from CLOCK Rise
10
Wait State
WSET
WAIT Setup Time to CLOCK Rise
23
WHOLD
WAIT Hold Time from CLOCK Rise
1
Halt
HSET
Halt Setup Time to CLOCK Rise
3
HHOLD
Halt Hold Time from CLOCK Rise
10
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
6
DC 9030-00
Z
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AC TIMING DIAGRAM
TCY
Tr
Tf
CPW
DSHOLD
DSSET
EASET
EAHOLD
RDSET
RDHOLD
Data In
Valid Address Out
CLOCK
/DS
EA(2:0)
RD//WR
EXT(15:0)
Read Timing Diagram
TCY
WSET
WHOLD
Valid Address Out
Data In
CLOCK
WAIT
/DS
EA(2:0)
RD//WR
EXT(15:0)
Read Timing Diagram Using WAIT Pin
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
DC 9030-00
7
Z
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TCY
DSHOLD
DSSET
EASET
EAHOLD
WRSET
WRHOLD
Data In
Valid Address Out
EAHOLD
EASET
EXT(15:0)
RD//WR
EA(2:0)
/DS
CLOCK
Write Timing Diagram
TCY
WSET
WHOLD
Valid Address Out
Data In
CLOCK
WAIT
/DS
EA(2:0)
RD//WR
EXT(15:0)
Write Timing Diagram Using WAIT Pin
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
8
DC 9030-00
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AC TIMING
(Continued)
Codec Interface Timing Diagram
TCY
SSET
FSSET
FSSET
TXSET
RXSET
RXHOLD
1
0
1
0
1
1
0
1
0
1
CLOCK
SCLK
FS0, FS1
TXD
RXD
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
DC 9030-00
9
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AC TIMING
(Continued)
TCY
INTWidth
INTSET
Fetch N 1
Fetch N
Fetch N +1
Fetch Int_Addr
Fetch I
Fetch I +1
Execute N 1
Execute N
CALL Int Routine
Execute Int Routine
CLOCK
INT 0,1,2
PROGRAM
ADDRESS
EXECUTE
Interrupt Timing Diagram
TCY
HHOLD
HSET
CLOCK
HALT
HALT Timing Diagram
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
10
DC 9030-00
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AC TIMING
(Continued)
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Code Execution
Tri-Stated
Tri-Stated
Access Reset Vector
Intact*
* The RAM and hardware registers are left intact
during a warm reset. A cold reset will produce
random data in these locations. The status
register is set to zeroes in both cases.
CLOCK
/RESET
INTERNAL
RESET
EXECUTE
RD/WR
/DS
UO0-1
EA0-2
EXT0-15
PA0-15
RAM/
REGISTERS
TCY
RSET
RRISE
RWIDTH
RESET Timing Diagram
TCY
PDSET
PDHOLD
Valid
Valid
Valid
Valid
Valid
Valid
PASET
CLOCK
PROGRAM
ADDRESS
PROGRAM
DATA
External Memory Port Timing Diagram
Z89390
CPS DC-9030-01
P R E L I M I N A R Y
DC 9030-00
11
Z
ILOG
Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
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information contained in this document.
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