1
Z89462
CP95DSP0400
P R E L I M I N A R Y
FEATURES
Z89462
16-B
IT
, F
IXED
-P
OINT
D
IGITAL
S
IGNAL
P
ROCESSOR
P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
CP95DSP0400 (8/95)
Prog. RAM
Prog./Data
Data RAM
Speed
Part
(K Words)
(K Words)
(Words)
(MHz)
Z89462
1
64
512
20, 40
s
100-Pin QFP and 124-Pin PGA Packages
s
0
C to +70
C Temperature Range
s
3.3- to 5.0-Volt Operating Range
40 MHz Operation @ 5.0V
20 MHz Operation @ 3.3V
s
Six RAM Pointers for 4K-Word RAM Banks
s
Three Maskable Vectored Interrupts, Edge or Level
Trigger Selectable
s
Enhanced Instruction Set
s
Single-Cycle Instruction Execution
s
Four-Stage Pipeline
On-Board Peripherals
s
Dual 8/16-Bit CODEC Interface
s
Wait-State Generator
s
Two 16-Bit Timer/Counters
s
Dynamic Program Bus Sizing
GENERAL DESCRIPTION
The Z89462 is a high-performance Digital Signal Processor
(DSP) optimized for processing and transferring data. This
enhanced processor provides an upward migration path
for its Z89C00/Z89321 predecessors.
The DSP provides three 12-bit Register Pointers for each
RAM bank. These pointers may be incremented or
decremented automatically to implement circular buffers
without software overhead.
Three prioritized and individually maskable interrupts are
provided for use by external peripherals requiring service
from the DSP. The interrupt inputs can be individually
conditioned for edge or level trigger. Acknowledgement of
an activated interrupt occurs at the end of an instruction
execution.
Two banks of 512 x 16-bit data RAM are available.
Expansion of the on-chip data RAM is provided through
future upgrades.
External interfaces include Address Bus and Data Bus for
external Program Memory, Address Bus and Data Bus for
external Data Memory, three vectored interrupt ports, and
two input/two output user ports.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Z89462
CP95DSP0400
2
P R E L I M I N A R Y
GENERAL DESCRIPTION
(Continued)
Timers
CODEC
Program
RAM
1KW
WSG_BYWD
RAM1
512W
RAM0
512W
MDR
MBUS_RAM01
Control
TxD
RxD
SCLK
FS0
FS1
MD15-MD0
X
Y
Multiplier
Bit
Field
Unit
BFR
ALU
AE
MUX
B
A
PH
P
PL
PB
BFB
32
8
32
A
AH
AL
RC
Repeat
Count
Reg
CR
Control
Reg
SR
Status
Reg
INT
CTL
User
Port
CLK
GEN
MAR
SP
FPR
MA15-MA0
MRD//WR
/MDS
PDR
/MW
AIT
/PW
AIT
/PDS
/PDSZE
/P
ALSB
PD15-PD0
PAR
PC
PBUS
Control
DSP Control
IR
INT2-0
/HLTHW
/HLTOUT
/RESET
3
IDB
16
16
16
16
16
rd,wr
waits
16
UI1-0
UO1-0
CLKIN
CLK
VDD
VSS
ds
2
P
A15-P
A0
PRD//WR
2
2
8
8
2
32
16
32
Functional Block Diagram
3
Z89462
CP95DSP0400
P R E L I M I N A R Y
PIN DESCRIPTION
Z89462
100-Pin VQFP
MA0
PA0
MA1
MA2
PA1
PA2
MA3
PA3
VDDP
VSSP
MA4
MA5
MA6
MA7
VSSI
MRD//WR
/MDS
/MWAIT
MA8
PA4
MA9
VDDP
VSSP
PA5
MA10
76
100
PD2
PALSB
INT2
PD5
PRD//WR
UI1
PD1
UI0
PD0
UO1
UO0
MD15
VDDI
MD14
MD13
VSSP
VDDP
MD12
MD11
MD10
MD9
PA15
MD8
PA14
MD7
50
26
1
25
PD6
VSSI
PD15
PD14
PD13
/HL
THW
PD12
PD1
1
PD10
/HL
T
OUT
PD9
PD8
/RESET
PD7
CKIN
PD5
CLK
/PW
AIT
PD4
INT0
PDSZE
PD3
INT1
VSSP
VDDP
75
51
5
10
15
20
30
35
40
45
60
70
55
65
80
85
90
95
PA
6
MA1
1
PA
7
MA12
PA
8
MA13
PA
9
MA14
VDDP
VSSP
MA15
MD0
VDDI
MD1
MD2
MD3
P
A10
MD4
PA
11
MD5
VDDP
VSSP
P
A12
MD6
P
A13
Pin 1
100-Pin VQFP Pin Assignments
Z89462
CP95DSP0400
4
P R E L I M I N A R Y
PIN DESCRIPTION
(Continued)
MA11
PA
4
MA8
/MW
AIT
/MDS
VSSI
MA7
MA6
MA5
MA4
VSSP
VDDP
PA
3
MA3
PA
2
MA2
PA
1
MA1
PA
0
MA0
EXEC
MRD//WR
Z89462
124-Pin PGA
UI0
PD0
UO1
UO0
MD15
VDDI
MD14
MD13
VSSP
VDDP
MD12
MD1
1
MD10
MD9
P
A15
MD8
P
A14
MD7
/MDBEN
/MAZ
PD15
PD14
PD13
/HLTHW
PD12
PD11
PD10
/HLTOUT
PD9
PD8
/RESET
PD7
CKIN
PD6
VSSI
PD5
/PAZ
PA6
PA7
MA12
PA8
MA13
PA9
MA14
VDDP
VSSP
MA15
MD0
VDDI
MD1
MD2
MD3
PA10
MD4
/BRK
PD2
P
ALSB
INT2
/PDS
PRD//WR
UI1
PD1
PA11
MD5
VDDP
VSSP
PA12
MD6
PA13
IACK
CLK
IPWAIT
PD4
INT0
PDSZE
PD3
INT1
VSSP
VDDP
MA10
PA
5
VSSP
VDDP
MA9
FETCH
1
31
63
93
124-Pin PGA Pin Assignments
5
Z89462
CP95DSP0400
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Description
Min. Max.
Units
Voltages on V
DD
with Respect to V
SS
0.5 +5.5
V
Voltages on All Pins with Respect to V
SS
0.5 (V
DD
+0.5) V
T
STG
Storage Temp
85
+150
C
T
A
Oper Ambient Temp
0
+70
C
STANDARD TEST CONDITIONS
The AC and DC Characteristics listed below apply for
standard test conditions, unless otherwise noted. All
voltages are referenced to V
SS
(= Ground = 0V). Positive
current flows into the referenced pin. Standard conditions
are as follows:
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended period may affect
device reliability.
3.0V < VDD < 3.6V
VSS = 0V
Ambient Temperature = 0
C to +70
C
Standard Test Load on All Outputs
DC ELECTRICAL CHARACTERISTICS
(5.0V Operation)
Sym.
Parameter
Min.
Max.
Unit
Note
V
IH
Input High Voltage
2.0
V
DD
+0.5
V
V
IL
Input Low Voltage
0.5
0.8
V
V
OH1
Output High Voltage (4 mA I
OH
)
2.4
V
V
OH2
Output High Voltage (250
A I
OH
)
V
DD
0.8
V
V
OL
Output Low Voltage (4 mA I
OL
)
0.5
V
I
IL
Input Leakage Current
10
+10
A
[1]
I
TL
Tri-State Leakage Current
10
+10
A
[2]
I
DD
Power Supply Current (@ 40 Mhz)
TBD
mA
[3]
I
DD2
Stopped Clock Power Supply Current
20
A
[4]
C
IN
Input Capacitance (f = 1 MHz)
15
pF
[5]
C
OUT
Output Capacitance (f = 1 Mhz)
15
pF
[5]
C
IO
I/O Capacitance (f = 1 MHz)
15
pF
[5]
C
L
Output Load Capacitance
30
pF
Notes:
[1]
V
IN
= 0.4V
[2]
0.4V < V
OUT
< 2.4V
[3]
V
DD
= 5.0V, V
IH
= 4.8V, V
IL
= 0.2V
[4]
V
DD
= 5.0V, V
IH
= 4.8V, V
IL
= 0.2V
[5]
Unmeasured pins returned to V
SS
.
Z89462
CP95DSP0400
6
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS
(5.0V Operation)
Symbol
Parameter
Min.
Max.
Unit
Note
TcCI
CLKIN Cycle Time
25
ns
TwCIh
CLKIN Width High
10
ns
TwCIl
CLKIN Width Low
10
ns
TrCI
CLKIN Rise Time
2
ns
TfCI
CLKIN Fall Time
2
ns
TdCIr(Cr)
CLKIN Rise to CLK Rise Delay
8
ns
TdCIf(Cf)
CLKIN Fall to CLK Fall Delay
8
ns
TrC
CLK Rise Time
2
ns
TfC
CLK Fall Time
2
ns
TdCr(PA)
CLK Rise to PA Valid Delay
5
ns
TdCr(PALSB)
CLK Rise to PALSB Valid Delay
5
ns
TdCr(PDSr)
CLK Rise to /PDS Rise Delay
4
ns
TdCf(PDSf)
CLK Fall to /PDS Fall Delay
4
ns
TsPW(Cr)
/PWAIT to CLK Rise Setup Time
5
ns
ThPW(Cr)
/PWAIT to CLK Rise Hold Time
0
ns
TsPSZ(Cr)
PDSZE to CLK Rise Setup Time
5
ns
ThPSZ(Cr)
PDSZE to CLK Rise Hold Time
0
ns
TdCr(PRDWR)
CLK Rise to PRD//WR Delay
5
ns
TsPD(Cr)
PD to CLK Rise Setup Time
5
ns
ThPD(Cr)
PD to CLK Rise Hold Time
0
ns
TdCR(PD)
CLK Rise to PD Valid Delay
5
ns
TdCr(PDt)
CLK Rise to PD Tri-State Delay
5
ns
TdCr(MA)
CLK Rise to MA Valid Delay
5
ns
TdCr(MDSr)
CLK Rise to /MDS Rise Delay
4
ns
TdCf(MDSf)
CLK Rise to /MDS Fall Delay
4
ns
TsMW(Cr)
/MWAIT to CLK Rise Setup Time
5
ns
ThMW(Cr)
/MWAIT to CLK Rise Hold Time
0
ns
TdCr(MRDWR)
CLK Rise to MRD//WR Delay
5
ns
TsMD(Cr)
MD to CLK Rise Setup Time
5
ns
ThMD(Cr)
MD to CLK Rise Hold Time
0
ns
TdCr(MD)
CLK Rise to MD Valid Delay
5
ns
TdCr(MDt)
CLK Rise to MD Tri-State Delay
5
ns
TsINT(Cr)
INT2-0 to CLK Rise Setup Time
5
ns
[1]
TwINTh
INT2-0 Width High
10
ns
TwHLTHWl
/HLTHW Width Low
10
TcCI
[2]
TwHLTHWh
/HLTHW Width High
2
TcCI
[2]
TdCr(HLTOUT)
CLK Rise to HLTOUT Delay
5
ns
TwRESETl
/RESET Width Low
3
TcCI
[2]
Notes:
[1] INT2-0 can also be asserted/deasserted asynchronously.
[2] These signals are asserted/deasserted asynchronously.
.
7
Z89462
CP95DSP0400
P R E L I M I N A R Y
DC ELECTRICAL CHARACTERISTICS
(3.0V Operation)
Sym.
Parameter
Min.
Max.
Unit
Note
V
IH
Input High Voltage
2.0
V
DD
+0.5
V
V
IL
Input Low Voltage
0.5
0.6
V
V
OH
Output High Voltage (200
A I
OH
)
2.15
V
V
OL
Output Low Voltage (4 mA I
OL
)
0.4
V
I
IL
Input Leakage Current
10
+10
A
[1]
I
TL
Tri-State Leakage Current
10
+10
A
[2]
I
DD
Power Supply Current (@ 40 Mhz)
TBD
mA
[3]
I
DD2
Stopped Clock Power Supply Current
20
A
[4]
C
IN
Input Capacitance (f = 1 MHz)
15
pF
[5]
C
OUT
Output Capacitance (f = 1 Mhz)
15
pF
[5]
C
IO
I/O Capacitance (f = 1 MHz)
15
pF
[5]
C
L
Output Load Capacitance
30
pF
Notes:
[1]
V
IN
= 0.4V
[2]
0.4V < V
OUT
< 2.15V
[3]
V
DD
= 3.3V, V
IH
= 3.0V, V
IL
= 0.2V
[4]
V
DD
= 3.3V, V
IH
= 3.0V, V
IL
= 0.2V
[5]
Unmeasured pins returned to V
SS
.
Z89462
CP95DSP0400
8
P R E L I M I N A R Y
1995 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
and that, in addition to all other limitations on Zilog liability
stated on the front and back of the acknowledgement,
Zilog makes no claim as to quality and reliability under the
CPS. The product remains subject to standard warranty for
replacement due to defects in materials and workmanship.
Low Margin:
Customer is advised that this product does not meet
Zilog's internal guardbanded test policies for the
specification requested and is supplied on an exception
basis. Customer is cautioned that delivery may be uncertain
Development Projects:
Customer is cautioned that while reasonable efforts will be
employed to meet performance objectives and milestone
dates, development is subject to unanticipated problems
and delays. No production release is authorized or
committed until the Customer and Zilog have agreed upon
a Customer Procurement Specification for this project.
conformance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-
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