PS024604-1005

P R E L I M I N A R Y

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PS024604-1005

P R E L I M I N A R Y

Table of Contents

Z8FMC16100 Series Flash MCU

Product Specification

iii

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Z8FMC16100 Series Flash MCU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pulse-Width Modulator for Motor Control Applications . . . . . . . . . . . . . . . . . . . . . . 3
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Random Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UART with LIN and IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reset and Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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Table of Contents

Z8FMC16100 Series Flash MCU
Product Specification

Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Fault Detect Logic Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Stop-Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . . . . . . . 28
Stop-Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . . . . 28
PWM Fault0 and Reset pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Reset Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Reset Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Port A-C Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Port A�C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A-C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Port A�C Output Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt and System Exception Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
System Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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Table of Contents

Z8FMC16100 Series Flash MCU

Product Specification

IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Watch-Dog Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 65

Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PWM Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

PWM Off State and Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PWM Channel Pair Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PWM Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PWM Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PWM Period and Count Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PWM Duty Cycle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Independent and Complementary PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Manual Off-State Control of PWM Output Channels . . . . . . . . . . . . . . . . . . . . . . . 72
Deadband Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Minimum PWM Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Synchronization of PWM and Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . 73
PWM Timer and Fault Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Fault Detection and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PWM Operation in CPU Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PWM Operation in CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Observing the State of PWM Output Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PWM Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PWM 0�2 Duty Cycle High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 77
PWM Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PWM Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PWM Deadband Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PWM Minimum Pulse Width Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PWM Fault Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PWM Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PWM Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PWM Input Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PWM Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Table of Contents

Z8FMC16100 Series Flash MCU
Product Specification

Current Sense ADC Trigger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

General-Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timer 0 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timer 0 Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timer 0 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Timer 0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Data Format for Standard UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 114
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . . 116
Clear To Send Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LIN-UART Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LIN Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LIN-UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LIN-UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

LIN-UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

LIN-UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
LIN-UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
LIN-UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
LIN-UART Mode Select and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LIN-UART Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
LIN-UART Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
LIN-UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
LIN-UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 140

Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . 148

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Multimaster Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

I2C Master/Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

I2C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Comparison with the Master Mode Only I2C Controller . . . . . . . . . . . . . . . . . . . . 165

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
I

C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Master Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Slave Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
I2C Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
I2C State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
I2C Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
I2C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Comparator and Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

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Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Operational Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Comparator and Op Amp Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
ADC Timer 0 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Internal Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
ADC Raw Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Sample Settling Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Sample Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ADC Clock Prescale Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
ADC Timer Capture High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
ADC Timer Capture Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

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Product Specification

Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

User Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Trim Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
User Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Clock Selection Following System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Clock Failure Detection and Recovery for Primary Oscillator . . . . . . . . . . . . . . . . 232
Clock Failure Detection and Recovery for WDT Oscillator . . . . . . . . . . . . . . . . . 233
Oscillator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Oscillator Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Automatic Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Break Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
OCDCNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Baud Reload Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

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Product Specification

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 265

General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . 271
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Appendix A--Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
General Purpose RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Trim Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

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Table of Contents

Z8FMC16100 Series Flash MCU

Product Specification

Comparator and Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
GPIO Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
GPIO Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
GPIO Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Reset and Watch-Dog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Flash Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
eZ8 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Op Code Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

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Product Specification

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List of Figures

Figure 1. Z8FMC16100 Series Flash MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. Z8FMC16100 Series Flash MCU in 32-Pin QFN and LQFP Package . . . . . . . 8

Figure 3. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 6. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 7. PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 8. Edge-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 9. Center-Aligned PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 10. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 11. LIN-UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 12. LIN-UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . 113

Figure 13. LIN-UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . 113

Figure 14. LIN-UART Driver Enable Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 15. LIN-UART Asynchronous Multiprocessor Mode Data Format . . . . . . . . . 119

Figure 16. LIN-UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . 126

Figure 17. Noise Filter System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 18. Noise Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 19. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . . 145

Figure 20. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 21. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 22. SPI Configured as a Master in a Single Master, Single Slave System . . . . 149

Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System . . . 150

Figure 24. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 25. SPI Timing When Phase is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 26. SPI Timing When Phase is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 27. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 28. Data Transfer Format--Master Write Transaction with a 7-Bit Address . . 171

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Figure 29. Data Transfer Format--Master Write Transaction with a 10-Bit Address . 172

Figure 30. Data Transfer Format--Master Read Transaction with a 7-Bit Address . . . 174

Figure 31. Data Transfer Format--Master Read Transaction with a 10-Bit Address . . 175

Figure 32. Data Transfer Format--Slave Receive Transaction with 7-Bit Address . . . 179

Figure 33. Data Transfer Format--Slave Receive Transaction with 10-Bit Address . . 180

Figure 34. Data Transfer Format--Slave Transmit Transaction with 7-bit Address . . 181

Figure 35. Data Transfer Format--Slave Transmit Transaction with 10-Bit Address . 182

Figure 36. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 37. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 38. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 39. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 40. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . . 237

Figure 41. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 42. Interfacing the On-Chip Debugger's DBG Pin with

an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 43. Interfacing the On-Chip Debugger's DBG Pin with

an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 44. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 45. Typical Active Mode I

Versus System Clock Frequency . . . . . . . . . . . . 261

Figure 46. Maximum Active Mode I

Versus System Clock Frequency . . . . . . . . . . 261

Figure 47. Typical Halt Mode I

Versus System Clock Frequency . . . . . . . . . . . . . . 262

Figure 48. Maximum Halt Mode I

Versus System Clock Frequency . . . . . . . . . . . . 262

Figure 49. Maximum Stop Mode I

with VBO enabled versus Supply Voltage . . . . 263

Figure 50. Maximum Stop Mode I

with VBO Disabled vs. Supply Voltage . . . . . . 264

Figure 51. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 52. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 53. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 54. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 55. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 56. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 57. Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

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Product Specification

xvii

List of Tables

Table 1. Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Pin Characteristics of the Z8FMC16100 Series Flash MCU . . . . . . . . . . . . . . . 11
Table 3. Z8FMC16100 Series Flash MCU Program Memory Maps . . . . . . . . . . . . . . . . 14
Table 4. Z8FMC16100 Series Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Reset and Stop-Mode Recovery Characteristics and Latency . . . . . . . . . . . . . . 23
Table 7. System Reset Sources and Resulting Reset Action . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Stop-Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Reset Status and Control Register (RSTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Reset Status Register Values Following Reset. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Power Control Register 0(PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Port Alternate Function Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Port A�C GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Port Control Subregisters by Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Port A�C Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Port A�C Data Direction Sub-Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Port A�B Alternate Function 0 Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Port A�C Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Port A�C High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22. Port A�C STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . . . 45
Table 23. Port A�C Pull-Up Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 24. Interrupt Edge Select Sub-Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Interrupt Port Select Sub-Register (IRQPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Port A�B Alternate Function 1 Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Port A-C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Port A-C Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 29. Reset, System Exception, and Interrupt Vectors in Order of Priority . . . . . . . 52
Table 30. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. IRQ0 Enable and Priority Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 35. IRQ1 Enable and Priority Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 36. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 37. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . . 64
Table 40. Watch-Dog Timer Reload High Byte Register (WDTH). . . . . . . . . . . . . . . . . 66
Table 41. Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . . 66
Table 42. PWM High Byte Register (PWMH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 43. PWM Reload High Byte Register (PWMRH) . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 44. PWM Low Byte Register (PWML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 45. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH). . 77
Table 46. PWM Reload Low Byte Register (PWMRL). . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 47. PWM Control 0 Register (PWMCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 48. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL) . . 78
Table 49. PWM Control 1 Register (PWMCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 50. PWM Dead-Band Register (PWMDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 51. PWM Minimum Pulse Width Filter (PWMMPF) . . . . . . . . . . . . . . . . . . . . . . 82
Table 52. PWM Fault Mask Register (PWMFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. PWM Fault Status Register (PWMFSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 54. PWM Fault Control Register (PWMFCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 55. PWM Input Sample Register (PWMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 56. PWM Output Control Register (PWMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 57. Current-Sense Trigger Control Register (PWMSHC) . . . . . . . . . . . . . . . . . . . 88
Table 58. Timer 0 High Byte Register (T0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 59. Timer 0 Low Byte Register (T0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 60. Timer 0 Reload High Byte Register (T0RH) . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 61. Timer 0 Reload Low Byte Register (T0RL) . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 62. Timer 0 PWM High Byte Register (T0PWMH) . . . . . . . . . . . . . . . . . . . . . . 105
Table 63. Timer 0 PWM Low Byte Register (T0PWML) . . . . . . . . . . . . . . . . . . . . . . . 105
Table 64. Timer 0 Control 0 Register (T0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 65. Timer 0 Control 1 Register (T0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 66. LIN-UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . . . 130
Table 67. LIN-UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 68. LIN-UART Status 0 Register - standard UART mode (U0STAT0) . . . . . . . 131
Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0). . . . . . . . . . . . . . . . . 132

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Table 70. LIN-UART Mode Select and Status Register (U0MDSTAT) . . . . . . . . . . . . 133
Table 71. LIN-UART Control 0 Register (U0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 72. MultiProcessor Control Register (U0CTL1 with MSEL = 000b) . . . . . . . . . 136
Table 73. Noise Filter Control Register (U0CTL1 with MSEL = 001b) . . . . . . . . . . . . 138
Table 74. LIN Control Register (U0CTL1 with MSEL = 010b) . . . . . . . . . . . . . . . . . . 139
Table 75. LIN-UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . . . 140
Table 76. LIN-UART Baud Rate High Byte Register (U0BRH). . . . . . . . . . . . . . . . . . 140
Table 77. LIN-UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . . . 141
Table 78. LIN-UART Baud Rates, 20.0 MHz System Clock . . . . . . . . . . . . . . . . . . . . 142
Table 79. LIN-UART Baud Rates, 10.0 MHz System Clock. . . . . . . . . . . . . . . . . . . . . 142
Table 80. LIN-UART Baud Rates, 5.5296 MHz System Clock . . . . . . . . . . . . . . . . . . 143
Table 81. LIN-UART Baud Rates, 3.579545 MHz System Clock . . . . . . . . . . . . . . . . 143
Table 82. LIN-UART Baud Rates, 1.8432 MHz System Clock . . . . . . . . . . . . . . . . . . 143
Table 83. SPI Clock Phase and Clock Polarity Operation . . . . . . . . . . . . . . . . . . . . . . . 153
Table 84. SPI Data Register (SPIDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 85. SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 86. SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 87. SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 88. SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 89. SPI Baud Rate High Byte Register (SPIBRH). . . . . . . . . . . . . . . . . . . . . . . . 162
Table 90. SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 91. I2C Master/Slave Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 92. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 93. I2C Interrupt Status Register (I2CISTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 94. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 95. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . . . 188
Table 96. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 97. I2C State Register (I2CSTATE) - Description when DIAG = 0 . . . . . . . . . . 189
Table 98. I2C State Register (I2CSTATE) - Description when DIAG = 1 . . . . . . . . . . 190
Table 99. I2CSTATE_H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 100. I2CSTATE_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 101. I2C Mode Register (I2CMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 102. I2C Slave Address Register (I2CSLVAD). . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 103. Comparator and Op Amp Control Register (CMPOPC) . . . . . . . . . . . . . . . 197
Table 104. ADC Control Register 0 (ADCCT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 105. ADC Raw Data High Byte Register (ADCRD_H) . . . . . . . . . . . . . . . . . . . 204

PS024604-1005

P R E L I M I N A R Y

List of Tables

Z8FMC16100 Series Flash MCU
Product Specification

Table 106. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 107. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 108. Sample and Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 109. Sample Hold Time (ADCST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 110. ADC Clock Prescale Register (ADCCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 111. ADC Timer Capture High Byte Register (ADCTCAP_H) . . . . . . . . . . . . . 208
Table 112. ADC Timer Capture Low Byte Register (ADCTCAP_L) . . . . . . . . . . . . . . 209
Table 113. Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 114. Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 115. Z8FMC16100 Series Flash MCU Information Area Map . . . . . . . . . . . . . . 213
Table 116. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 117. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 118. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 119. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 120. Flash Frequency High Byte Register (FFREQH). . . . . . . . . . . . . . . . . . . . . 220
Table 121. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . . 221
Table 122. User Option Bits at Program Memory Address 0000H . . . . . . . . . . . . . . . . 224
Table 123. Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . 225
Table 124. Trim Bit Address Register (TRMADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 125. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 126. IPO Trim Option Bits at 0001H (IPO_TRIM) . . . . . . . . . . . . . . . . . . . . . . . 228
Table 127. IPO Trim1 Option Bits at 0002H (IPO_TRIM1) . . . . . . . . . . . . . . . . . . . . . 228
Table 128. Trim Option Bits at 0004H (ADCCAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 129. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 130. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 131. Oscillator Divide Register (OSCDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 132. Recommended Crystal Oscillator Specifications (20MHz Operation) . . . . 238
Table 133. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 134. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 135. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 136. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 137. Baud Reload Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 138. Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 139. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 140. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 141. POR and VBO Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . 265

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P R E L I M I N A R Y

List of Tables

Z8FMC16100 Series Flash MCU

Product Specification

xxi

Table 142. External RC Oscillator Electrical Characteristics and Timing. . . . . . . . . . . 266
Table 143. Internal Precision Oscillator Electrical Characteristics and Timing . . . . . . 266
Table 144. Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . 267
Table 145. Reset and Stop-Mode Recovery Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 146. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . . 267
Table 147. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 148. Operational Amplifier Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 269
Table 149. GPIO Port Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 150. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 151. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 152. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 153. UART Timing without CTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 154. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 155. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 156. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 157. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 158. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 159. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 160. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 161. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 162. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 163. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 164. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 165. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 166. Op Code Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 167. Z8FMC16100 Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 168. Ordering Information for the Z8FMC16100 Series Products* . . . . . . . . . . 303
Table 169. Current-Sense Trigger Control Register (PWMSHC) . . . . . . . . . . . . . . . . . 323

PS024604-1005

P R E L I M I N A R Y

Z8FMC16100 Series Flash MCU Features

Z8FMC16100 Series Flash MCU

Product Specification

Introduction

The Z8FMC16100 Series Flash MCU is based on ZiLOG's advanced eZ8 8-bit CPU core
and is optimized for motor control applications. It supports control of single- and mul-
tiphase variable speed motors. Target applications are consumer appliances, HVAC, fac-
tory automation, refrigeration, and automotive applications, among others.

Z8FMC16100 Series Flash MCU Features

�

20 MHz ZiLOG eZ8 CPU core

�

Up to 16 KB Flash program memory

�

512 B register RAM

�

Fast 8-channel 10-bit analog-to-digital converter

�

12-bit PWM module with three complementary pairs or six independent PWM outputs
with deadband generation and fault trip input

�

16-bit timer with capture/compare/PWM capability

�

Analog comparator

�

Operational amplifier

�

C controller supports master, slave, and multimaster modes

�

UART with interface support for LIN and IrDA

�

SPI controller

�

Internal precision oscillator

�

On-chip oscillator supports external crystals, ceramic resonators, and clock drivers

�

17 General Purpose I/O pins (GPIO)

�

Voltage Brown-Out/Power On Reset (VBO/POR)

�

Watch-Dog Timer (WDT) with internal RC oscillator

�

On-chip debugger

�

In-circuit serial programming

�

Operating at 2.7 to 3.6 volts

�

32-pin packages

�

Lead-free packaging

�

Standard and extended temperature ranges: 0� to 70� (S) and �40� to 105�C (E)

�

Up to 20 interrupts with configurable priority

PS024604-1005

P R E L I M I N A R Y

CPU and Peripheral Overview

Z8FMC16100 Series Flash MCU

Product Specification

CPU and Peripheral Overview

The eZ8 CPU, ZiLOG's latest 8-bit central processing unit, meets the continuing demand
for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of
the original Z8

�

instruction set. The eZ8 CPU features include:

�

Direct register-to-register architecture allows each register to function as an accumula-
tor, improving execution time and decreasing the required program memory

�

Software stack allows much greater depth in subroutine calls and interrupts than hard-
ware stacks

�

Compatible with existing Z8

�

assembly code

�

New instructions improve execution efficiency for code developed using higher-level
programming languages, including C

�

Pipelined instruction fetch and execution

�

New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL

�

New instructions support 12-bit linear addressing of the Register File

�

Up to 10 MIPS operation

�

C-Compiler friendly

�

2-9 clock cycles per instruction

�

For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual
(UM0128), available for download at

www.zilog.com

Pulse-Width Modulator for Motor Control Applications

To rotate a 3-phase motor three voltage and current signals must be supplied, each 120�
shifted from each other. To control a 3-phase motor the MCU must provide 6 PWM out-
puts.

The Z8FMC16100 Series Flash MCU features a flexible PWM module with three comple-
mentary pairs or six independent PWM outputs supporting deadband operation and fault
protection trip input. These features provide multiphase control capability for a variety of
motor types and ensure safe operation of the motor by providing immediate shutdown of
the PWM pins during fault condition.

10-Bit Analog-to-Digital Converter

The Z8FMC16100 Series Flash MCU devices feature up to eight channels of 10-bit A/D
conversion.

Introduction

P R E L I M I N A R Y PS024604-1005

Z8 Encore!

�

Motor Control Flash MCUs

Product Specification

Analog Comparator

The Z8FMC16100 Series Flash MCU features an on-chip analog comparator with external
input pins.

Operational Amplifier

The Z8FMC16100 Series Flash MCU features a two-input, one-output operational ampli-
fier.

General Purpose I/O

The Z8FMC16100 Series Flash MCU features 17 general purpose I/O (GPIO). Each pin is
individually programmable.

Flash Controller

The Flash Controller programs and erases the Flash memory. The Z8FMC16100 Series
Flash MCU products contain 16KB of on-chip Flash memory. A sector protection scheme
allows for flexible protection of user code.

Random Access Memory (RAM)

512B of internal RAM provides storage space for data, variables, and stack operations.

UART with LIN and IrDA

A full-duplex 9-bit UART provides serial, asynchronous communication and supports the
Local Interconnect Network (LIN) serial communications protocol. UART communica-
tion is full-duplex and capable of handling asynchronous data transfers. The UARTs sup-
port 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver
Enable signal for controlling a multitransceiver bus, such as RS-485. The LIN bus is a
cost-efficient single master, multiple slave organization that supports speeds up to 20K/
bits.

Serial Peripheral Interface

The serial peripheral interface (SPI) allows the Z8 Encore!

�

to exchange data between

other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is
a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.

PS024604-1005

P R E L I M I N A R Y I

Z8FMC16100 Series Flash MCU

Product Specification

The inter-integrated circuit (I

C) controller makes the Z8 Encore! compatible with the I

protocol. The I

C controller consists of two bidirectional bus lines, a serial data (SDA)

line and a serial clock (SCL) line. The I

C can operate as a master and/or slave and sup-

ports multimaster bus arbitration.

Internal Precision Oscillator

The Internal Precision Oscillator (IPO) provides a stable, accurate time base without the
requirement for external components. This can reduce system cost in many applications
by eliminating the requirement for external crystals or ceramic resonators. IPO frequency
is 5.5296MHz.

Crystal Oscillator

The on-chip crystal oscillator features programmable gain to support crystals and ceramic
resonators from 32KHz to 20MHz. The oscillator can also be used with clock drivers.

Standard Timer

The 16-bit reloadable timer can be used for timing/counting events and PWM signal gen-
eration. This timer provides a 16-bit programmable reload counter and operate in One-
Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes.

This timer can measure velocity from a tachometer wheel or read sensor outputs for rotor
position for brushless DC motor commutation. The standard timer can also be used for
general purpose timing and counting operations.

Interrupt Controller

The Z8FMC16100 Series Flash MCU products support 3 levels of programmable interrupt
priority. The interrupt sources include internal peripherals, general-purpose I/O pins, and
system fault detection.

Reset Controller

The Z8FMC16100 Series Flash MCU can be reset using the RESET pin, power-on reset,
Watch-Dog Timer (WDT), Stop-Mode Recovery, or Voltage Brown-Out (VBO) warning
signal.

On-Chip Debugger

The Z8FMC16100 Series Flash MCU features an integrated On-Chip Debugger (OCD).
The single-pin OCD interface provides a rich set of debugging capabilities, such as read-

PS024604-1005

P R E L I M I N A R Y Signal

Descriptions

Z8FMC16100 Series Flash MCU

Product Specification

Signal Descriptions

This section describes the Z8FMC16100 Series Flash MCU signals.

Table 1. Signal Descriptions

Signal Mnemonic

I/O

Description

General-Purpose I/O Ports A-H

PA[7:0]

I/O

Port A[7:0]. These pins are used for general-purpose I/O.

PB[7:0]

I/O

Port B[7:0]. These pins are used for general-purpose I/O.

PC[0]

I/O

Port C[0]. These pins are used for general-purpose I/O.

Pulse-Width Modulator for Motor Control

PWM0h/PWM1H

PWM2H

PWM High output.

PWM0L/PWM1L

PWM2L

PWM Low output.

FAULT0/FAULT1

PWM FAULT condition input. FAULT0 is active low, FAULT1 is active
high

SPI

MISO

I/O

Master In, Slave Out

MOSI

I/O

Master Out, Slave In.

SCLK

I/O

SPI Clock.

Slave Select

Timers

T0OUT, T0OUT

General-Purpose Timer Outputs.

T0INx

General-Purpose Timer Input. This signal is used as the capture, gating
and counter inputs.

UART Controller

TXD

Transmit Data. This signal is the transmit output from the UART and
IrDA.

RXD

Receive Data. This signal is the receiver input for the UART and IrDA.

CTS

Clear To Send signal from the receiving device that ready to receive
data.

TXDE

Driver Enable. This signal allows automatic control of external RS-485
drivers. The DE signal may be used to ensure an external RS-485 driver
is enabled when data is transmitted by the UART.

Signal and Pin Descriptions

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!

�

Motor Control Flash MCUs

Product Specification

Analog

ANA[7:0]

Analog Input. These signals are inputs to the analog-to-digital converter
(ADC).

REF

I/O

Voltage buffer output. This signal provides reference voltage for external
components.

If using the internal reference voltage generator, a 10 �F capacitor must
be placed on this pin to Ground.

CINP

Comparator positive input.

CINN

Comparator negative input.

COMPOUT

Comparator output.

OPINP

Operational amplifier positive input.

OPINN

Operational amplifier negative input.

OPOUT

Operational amplifier output.

Oscillators

The External Crystal Input is the input pin to the crystal oscillator. A
crystal can be connected between it and the X

OUT

pin to form the

oscillator. In addition, this pin is used with external RC networks or
external clock drivers to provide the system clock.

OUT

External Crystal Output. This pin is the output of the crystal oscillator. A
crystal can be connected between it and the X

pin to form the oscillator.

This pin must be left unconnected when not using a crystal.

On-Chip Debugger

DBG

I/O

Debug. This open-drain pin provides the single-pin control and data
interface to the On-Chip Debugger. For operation of the On-chip
Debugger, all power pins (V

) must be supplied with power, and all

ground pins (V

) must be grounded.

This pin is open-drain and must have an external pull-up resistor to
ensure proper operation.

Reset-PWM Fault

RESET/FAULT0

I/O

RESET input pin generates a Reset or PWM fault when asserted (driven
Low). The function selection is determined by the FLTSEL bit of the User
Options Bits at Program Memory Address 0001h, and the FAULTSEL bit
in the Reset Status and Control Register.

Table 1. Signal Descriptions (Continued)

Signal Mnemonic

I/O

Description

Caution

PS024604-1005

P R E L I M I N A R Y Pin

Characteristics

Z8FMC16100 Series Flash MCU

Product Specification

Pin Characteristics

Table 2 lists the characteristics for each of the Z8FMC16100 Series Flash MCU's 32 pins.
Data in Table 2 is sorted alphabetically by the pin symbol mnemonic.

Power Supply

VDD , AVDD

Power Supply.

VSS , AVSS

Ground.

Table 2. Pin Characteristics of the Z8FMC16100 Series Flash MCU

Symbol

Mnemonic Direction

Reset

Direction

Active Low

Active High

Tri-State

Output

Internal Pull-

or Pull-down

Schmitt

Trigger

Input

Open Drain

Output

DBG

I/O

N/A

Yes

Pull-up

Yes

PA[7:0]

I/O

N/A

Yes

Pull-up,

Programmable

Yes

Yes,

Programmable

PB[7:0]

I/O

N/A

Yes

Pull-up,

Programmable

Yes

Yes,

Programmable

PC[0]

I/O

N/A

Yes

Pull-up,

Programmable

Yes

Yes,

Programmable

PWMxH

I/O

Tristate

N/A

Yes

PWMxL

I/O

Tristate

N/A

Yes

RESET

Low

N/A

Pull-up

Yes

N/A

REF

I/O

N/A

Yes

N/A

, AV

Supply

N/A

, AV

Supply

N/A

Note: x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer.

Table 1. Signal Descriptions (Continued)

Signal Mnemonic

I/O

Description

PS024604-1005

P R E L I M I N A R Y Register

File

Z8FMC16100 Series Flash MCU

Product Specification

Address Space

The eZ8 CPU can access three distinct address spaces:

�

The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and general-purpose I/O port control registers.

�

The Program Memory contains addresses for all memory locations having executable
code and/or data.

�

The Data Memory contains addresses for all memory locations that hold data only.

These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
User Manual (UM0128), available for download at

www.zilog.com

Register File

The Z8FMC16100 Series Flash MCU supports up to 512B of internal RAM within the
Register File address space.

The Register File is composed of two sections--control regis-

ters and general-purpose registers (RAM). When instructions are executed, registers are
read from when defined as sources and written to when defined as destinations. The archi-
tecture of the eZ8 CPU allows all general-purpose registers to function as accumulators,
address pointers, index registers, stack areas, or scratch pad memory.

The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from

F00h

FFFh

. Some of the addresses within the 256-byte control register

section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value.

Writing to reserved Register File addresses is not recommended and can produce unpre-
dictable results.

The on-chip RAM always begins at address

000h

in the Register File address space. The

Z8FMC16100 Series Flash MCU devices provide 512B of on-chip RAM depending upon
the device. Reading from Register File addresses outside the available RAM addresses
(and not within the control register address space) returns an undefined value. Writing to
these Register File addresses produces no effect. See the

Ordering Information for the

Z8FMC16100 Series Products*

section on page 303 to determine the amount of RAM

available for the specific Z8FMC16100 Series Flash MCU device.

Caution:

Address Space

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!

�

Motor Control Flash MCUs

Product Specification

Program Memory

The Z8FMC16100 Series Flash MCU products contain 16 KB of on-chip Flash memory in
the Program Memory address space, depending upon the device (FMC08100 has 8 KB
and FMC04100 has 4 KB). Reading from Program Memory addresses outside the avail-
able Flash memory addresses returns

FFh

. Writing to these unimplemented Program

Memory addresses produces no effect. Table 3 describes the Program Memory Maps for
the Z8FMC16100 Series Flash MCU products.

Data Memory

The Z8FMC16100 Series Flash MCU does not use the eZ8 CPU's 64KB Data Memory
address space.

Information Area

Table 4 describes the Z8FMC16100 Series Flash MCU Information Area. This 512-byte
Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When
access is enabled, the Information Area is mapped into the Program Memory and overlays
the 512 bytes at addresses

FE00h

FFFFh

. When the Information Area access is enabled,

execution of LDC and LDCI instruction from these Program Memory addresses return the
Information Area data rather than the Program Memory data. Reads of these addresses
through the On-Chip Debugger also returns the Information Area data. Execution of code
from these addresses continues to correctly use the Program Memory. Access to the Infor-
mation Area is read-only.

Table 3. Z8FMC16100 Series Flash MCU

Program Memory Maps

Program Memory Address (Hex)

Function

Z8FMC16000 Products

0000-0001

Option Bits

0002-0003

Reset Vector

0004-0007

System Exception Vectors

0008-003F

Interrupt Vectors

0040-3FFF

Program Memory

Note: See Table 29 on page 52 for a list of the interrupt vectors.

PS024604-1005

P R E L I M I N A R Y

Z8FMC16100 Series Flash MCU

Product Specification

Register File Address Map

Table 5 provides the address map for the Register File of the Z8FMC16100 Series Flash
MCU.

Table 5. Register File Address Map

Address
(Hex)

Register Description

Mnemonic

Reset (Hex)

Page #

General Purpose RAM--Z8FMC16 devices with 512B On-Chip RAM

000�1FF

General-Purpose Register File RAM

200�EFF

Reserved

Timer 0

F00

Timer 0 High Byte Register (T0H)

T0H

103

F01

Timer 0 Low Byte Register (T0L)

T0L

103

F02

Timer 0 Reload High Byte Register (T0RH)

T0RH

104

F03

Timer 0 Reload Low Byte Register (T0RL)

T0RL

104

F04

Timer 0 PWM High Byte Register (T0PWMH)

T0PWMH

105

F05

Timer 0 PWM Low Byte Register (T0PWML)

T0PWML

105

F06

Timer 0 Control 0 Register (T0CTL0)

T0CTL0

106

F07

Timer 0 Control 1 Register (T0CTL1)

T0CTL1

107

F08

ADC Timer 0 Capture Register, High Byte

ADCTCAP_H

208

F09

ADC Timer 0 Capture Register, Low Byte

ADCTCAP_L

209

F0A�F1F

Reserved

Pulse-Width Modulator

F20

PWM Control 0 Register

PWMCTL0

F21

PWM Control 1 Register

PWMCTL1

F22

PWM Deadband Register

PWMDB

F23

PWM Minimum Pulse Width Filter

PWMMPF

F24

PWM Fault Mask Register

PWMFM

F25

PWM Fault Status Register

PWMFSTAT X0X0-0XXXb

Note: XX = undefined.

P R E L I M I N A R Y

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Motor Control Flash MCUs

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F26

PWM Input Sample Register

PWMIN

F27

PWM Output Control Register

PWMOUT

F28

PWM Fault Control Register

PWMFCTL

F29

Current Sense ADC Trigger Control Register

PWMSHC

F2A�B

Reserved

F2C

PWM High Byte Register (PWMH)

PWMH

F2D

PWM Low Byte Register (PWML)

PWML

F2E

PWM Reload High Byte Register (PWMRH)

PWMRH

F2F

PWM Reload Low Byte Register (PWMRL)

PWMRL

F30

PWM 0 High Side Duty Cycle High Byte

PWMH0Dh

F31

PWM 0 High Side Duty Cycle Low Byte

PWMH0DL

F32

PWM 0 Low Side Duty Cycle High Byte

PWML0Dh

F33

PWM 0 Low Side Duty Cycle Low Byte

PWML0DL

F34

PWM 1 High Side Duty Cycle High Byte

PWMH1DH

F35

PWM 1 High Side Duty Cycle Low Byte

PWMH1DL

F36

PWM 1 Low Side Duty Cycle High Byte

PWML1DH

F37

PWM 1 Low Side Duty Cycle Low Byte

PWML1DL

F38

PWM 2 High Side Duty Cycle High Byte

PWMH2DH

F39

PWM 2 High Side Duty Cycle Low Byte

PWMH2DL

F3A

PWM 2 Low Side Duty Cycle High Byte

PWML2DH

F3B

PWM 2 Low Side Duty Cycle Low Byte

PWML2DL

F3C�F3F

Reserved

Table 5. Register File Address Map (Continued)

Address
(Hex)

Register Description

Mnemonic

Reset (Hex)

Page #

Note: XX = undefined.

PS024604-1005

P R E L I M I N A R Y

Z8FMC16100 Series Flash MCU

Product Specification

LIN-UART

F40

LIN-UART Transmit Data Register

U0TXD

130

LIN-UART Receive Data Register

U0RXD

130

F41

LIN-UART Status 0 Register

U0STAT0

0000_011Xb

131

F42

LIN-UART Control 0 Register

U0CTL0

134

F43

LIN-UART Control 1

U0CTL1

136

F44

LIN-UART Mode Select and Status

U0MDSTAT

133

F45

LIN-UART Address Compare

U0ADDR

140

F46

LIN-UART Baud Rate High Byte

U0BRH

140

F47

LIN-UART Baud Rate Low Byte

U0BRL

141

F48�F5F

Reserved

F50

I2C Data Register

I2CDATA

184

F51

I2C Interrupt Status Register

I2CISTAT

184

F52

I2C Control Register

I2CCTL

186

F53

I2C Baud Rate High Byte Register (I2CBRH)

I2CBRH

188

F54

I2C Baud Rate Low Byte Register (I2CBRL)

I2CBRL

188

F55

I2C State Register (I2CSTATE) - Description
when DIAG = 0

I2CSTATE

189

I2C State Register (I2CSTATE) - Description
when DIAG = 1

I2CSTATE

190

F56

I2C Mode Register

I2CMODE

192

F57

I2C Slave Address Register

I2CSLVAD

193

F58�F5F

Reserved

SPI

F60

SPI Data Register

SPIDATA

157

F61

SPI Control Register

SPICTL

158

F62

SPI Status Register

SPISTAT

159

Table 5. Register File Address Map (Continued)

Address
(Hex)

Register Description

Mnemonic

Reset (Hex)

Page #

Note: XX = undefined.

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F63

SPI Mode Register

SPIMODE

160

F64

SPI Diagnostic State Register

SPIDST

161

F65

Reserved

F66

SPI Baud Rate High Byte Register (SPIBRH)

SPIBRH

162

F67

SPI Baud Rate Low Byte Register (SPIBRL)

SPIBRL

162

F68�F6F

Reserved

Analog-to-Digital Converter (ADC)

F70

ADC Control Register 0

ADCCTL0

203

F71

ADC Raw Data High Byte Register

ADCRD_H

204

F72

ADC Data High Byte Register

ADCD_H

204

F73

ADC Data Low Bits Register

ADCD_L

205

F74

Sample Settling Time Register

ADCSST

206

F75

Sample Time Register

ADCST

206

F76

ADC Clock Prescale Register

ADCCP

207

F77�F85

Reserved

Oscillator Control

F86

Oscillator Control Register

OSCCTL

233

F87

Oscillator Divide Register

OSCDIV

234

Trim Control

F88�F8F

Reserved

Comparator and Op Amp

F90

Comparator and Op Amp Control Register

CMPOPC

197

F91�FBF

Reserved

Interrupt Controller

FC0

Interrupt Request 0 Register

IRQ0

FC1

IRQ0 Enable High Bit Register (IRQ0ENH)

IRQ0ENH

FC2

IRQ0 Enable Low Bit Register (IRQ0ENL)

IRQ0ENL

Table 5. Register File Address Map (Continued)

Address
(Hex)

Register Description

Mnemonic

Reset (Hex)

Page #

Note: XX = undefined.

PS024604-1005

P R E L I M I N A R Y

Z8FMC16100 Series Flash MCU

Product Specification

FC3

Interrupt Request 1 Register

IRQ1

FC4

IRQ1 Enable High Bit Register (IRQ1ENH)

IRQ1ENH

FC5

IRQ1 Enable Low Bit Register (IRQ1ENL)

IRQ1ENL

FC9�FCE Reserved

FCF

Interrupt Control Register

IRQCTL

GPIO Port A

FD0

Port A Address

PAADDR

FD1

Port A Control

PACTL

FD2

Port A Input Data

PAIN

FD3

Port A Output Data

PAOUT

GPIO Port B

FD4

Port B Address

PBADDR

FD5

Port B Control

PBCTL

FD6

Port B Input Data

PBIN

FD7

Port B Output Data

PBOUT

GPIO Port C

FD8

Port C Address

PCADDR

FD9

Port C Control

PCCTL

FDA

Port C Input Data

PCIN

FDB

Port C Output Data

PCOUT

Reset and Watch-Dog Timer (WDT)

FF0

Reset Status and Control Register

RSTSTAT

see Table 10

FF1

Reserved

FF2

Watch-Dog Timer Reload High Byte Register
(WDTH)

WDTH

FF3

Watch-Dog Timer Reload Low Byte Register
(WDTL)

WDTL

FF4�FF5

Reserved

Table 5. Register File Address Map (Continued)

Address
(Hex)

Register Description

Mnemonic

Reset (Hex)

Page #

Note: XX = undefined.

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Trim

FF6

Trim Bit Address Register

TRMADR

227

FF7

Trim Bit Data Register

TRMDR

227

Flash Memory Controller

FF8

Flash Control Register

FCTL

217

FF8

Flash Status Register

FSTAT

218

FF9

Flash Page Select Register

FPS

218

FF9 (if
enabled)

Flash Sector Protect Register

FPROT

219

FFA

Flash Frequency High Byte Register
(FFREQH)

FFREQH

220

FFB

Flash Frequency Low Byte Register (FFREQL)

FFREQL

221

eZ8 CPU

FFC

Flags

FLAGS

Refer to the

eZ8 CPU

User Manual

(UM0128).

FFD

FFE

Stack Pointer High Byte

SPH

FFF

Stack Pointer Low Byte

SPL

Table 5. Register File Address Map (Continued)

Address
(Hex)

Register Description

Mnemonic

Reset (Hex)

Page #

Note: XX = undefined.

PS024604-1005

P R E L I M I N A R Y Reset

Types

Z8FMC16100 Series Flash MCU

Product Specification

Reset and Stop-Mode Recovery

The Reset Controller within the Z8FMC16100 Series Flash MCU controls RESET and
Stop-Mode Recovery operation. In typical operation, the following events cause a RESET
to occur:

�

Power-On Reset (POR)

�

Voltage Brown-Out (VBO)

�

Watch-Dog Timer time-out (when configured via the

WDT_RES

Option Bit to initiate a

Reset)

�

External RESET pin assertion

�

On-Chip Debugger initiated RESET (

OCDCTL[0]

set to 1)

�

Fault detect logic

When the Z8FMC16100 Series Flash MCU is in STOP mode, a Stop-Mode Recovery is
initiated by either of the following:

�

Watch-Dog Timer time-out

�

GPIO port input pin transition on an enabled Stop-Mode Recovery source

Reset Types

The Z8FMC16100 Series Flash MCU provides two different types of reset operation (Sys-
tem Reset and Stop-Mode Recovery). The type of reset is a function of both the current
operating mode of the Z8FMC16100 Series Flash MCU and the source of the reset. Table
6 lists the types of reset and their operating characteristics.

Table 6. Reset and Stop-Mode Recovery Characteristics and Latency

Reset Type

Reset Characteristics and Latency

Peripheral Control
Registers

eZ8 CPU Reset Latency (Delay)

System Reset

Reset (as
applicable)

RESET

A minimum of 66 Internal Precision Oscillator cycles.

Stop-Mode
Recovery

Unaffected, except
RSTSRC and
OSCCTL registers

Reset

A minimum of 66 Internal Precision Oscillator cycles.

Reset and Stop-Mode Recovery

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System Reset

During a system reset, the Z8FMC16100 Series Flash MCU is held in RESET for 66
cycles of the Internal Precision Oscillator. At the beginning of RESET, all GPIO pins are
configured as inputs. All GPIO programmable pull-ups are disabled.

At the start of a System Reset, the motor control PWM outputs are forced to high-imped-
ance momentarily. When the Option Bits that control the off-state have been properly
evaluated the PWM outputs are forced to the programmed off-state.

During RESET, the eZ8 CPU and on-chip peripherals are idle; however, the Internal Preci-
sion Oscillator and Watch-Dog Timer oscillator continue to run. During the first 50 clock
cycles the internal option bit registers are initialized, after which the system clock for the
core and peripherals begins operating. The eZ8 CPU and on-chip peripherals remain idle
through the next 16 cycles of the system clock after which time the internal reset signal is
deasserted.

Upon RESET, control registers within the Register File that have a defined reset value are
loaded with their reset values. Other control registers (including the Flags) and general-
purpose RAM are undefined following RESET. The eZ8 CPU fetches the RESET vector
at Program Memory addresses

0002h

and

0003h

and loads that value into the Program

Counter. Program execution begins at the RESET vector address.

Table 7 lists the system reset sources as a function of the operating mode. The text follow-
ing provides more detailed information on the individual RESET sources. Please note that
a Power-On Reset/Voltage Brown-Out event always has priority over all other possible
reset sources to ensure a full system reset occurs.

Table 7. System Reset Sources and Resulting Reset Action

Operating Mode System Reset Source

Action

Normal or HALT
modes

Power-On Reset/Voltage Brown-Out

System Reset.

Watch-Dog Timer time-out when
configured for reset.

System Reset.

RESET pin assertion.

System Reset.

Write OCDCTL[0] to 1.

System Reset except the On-Chip
Debugger is not reset.

Fault detect logic reset.

System Reset.

STOP mode

Power-On Reset/Voltage Brown-Out.

System Reset.

RESET pin assertion.

System Reset.

Fault detect logic reset.

System Reset.

PS024604-1005

P R E L I M I N A R Y Power-On

Reset

Z8FMC16100 Series Flash MCU

Product Specification

Power-On Reset

Each device in the Z8FMC16100 Series Flash MCU contains an internal Power-On Reset
(POR) circuit. The POR circuit monitors the supply voltage and holds the device in the
Reset state until the supply voltage reaches a safe operating level. After the supply voltage
exceeds the POR voltage threshold (V

POR

) and has stabilized, the POR Counter is enabled

and counts 50 cycles of the Internal Precision Oscillator. At this point the System Clock is
enabled and the POR Counter counts a total of 16 system clock pulses. The device is held
in the Reset state until this second POR Counter sequence has timed out. After the
Z8FMC16100 Series Flash MCU exits the Power-On Reset state, the eZ8 CPU fetches the
Reset vector. Following Power-On Reset, the

POR

status bit in the

Reset Status and Con-

trol Register

is set to 1.

Figure 3 illustrates Power-On Reset operation. Refer to the

On-Chip Peripheral AC and

DC Electrical Characteristics

section on page 265

for the POR threshold voltage

POR

Voltage Brown-Out Reset

The Z8FMC16100 Series Flash MCU provides low Voltage Brown-Out (VBO) protection.
The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO

Figure 3. Power-On Reset Operation

Option Bit

Counter Delay

Oscillator

Startup

System Clock

Counter Delay

Internal RESET

Signal

Internal Precision

Oscillator

System Clock

= 0.0V

= 3.3V

VBO

POR

Program Execution

Reset and Stop-Mode Recovery

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threshold voltage) and forces the device into the Reset state. While the supply voltage
remains below the Power-On Reset voltage threshold (V

POR

), the VBO holds the device in

the Reset state.

After the supply voltage again exceeds the Power-On Reset voltage threshold and stabi-
lized, the device progresses through a full System Reset sequence, as described in the
Power-On Reset section. Following Power-On Reset, the

POR

status bit in the Reset

Source

On-Chip Peripheral AC and DC Electrical Characteristics

section on page 265

for the

VBO and POR threshold voltages (V

VBO

and V

POR

The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode.
Operation during STOP mode is controlled by the

VBO_AO

Option Bit. Refer to the Option

Bits chapter for information on configuring

VBO_AO

Watch-Dog Timer Reset

If the device is in normal or HALT mode, the Watch-Dog Timer can initiate a System
Reset at time-out if the

WDT_RES

Option Bit is set to 1. This setting is the default (unpro-

grammed) setting of the

WDT_RES

Option Bit. The

WDT

status bit in the

Reset Status and

Control Register

is set to signify that the reset was initiated by the Watch-Dog Timer.

Figure 4. Voltage Brown-Out Reset Operation

Option Bit

Counter Delay

System Clock

Counter Delay

Internal RESET

Signal

Internal Precision

Oscillator

System Clock

= 3.3V

VBO

POR

Program Execution

Program

Execution

Voltage

Brown-Out

PS024604-1005

P R E L I M I N A R Y

External Pin Reset

Z8FMC16100 Series Flash MCU

Product Specification

External Pin Reset

The input-only RESET pin has a Schmitt-triggered input, an internal pull-up, an analog
filter and a digital filter to reject noise. Once the RESET pin is asserted for at least 4 sys-
tem clock cycles, the device progresses through the System Reset sequence. While the
RESET input pin is asserted Low, the Z8FMC16100 Series Flash MCU device continues
to be held in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state 16 system clock cycles following RESET pin deasser-
tion. If the RESET pin is released before the System Reset time-out, the RESET pin is
driven Low by the chip until the completion of the time-out as described in the next sec-
tion. In STOP mode the digital filter is bypassed because the System Clock is disabled.

Following a System Reset initiated by the external RESET pin, the

EXT

status bit in the

Reset Status and Control Register

is set to 1.

External Reset Indicator

During System Reset, the RESET pin functions as an open drain (active Low) reset mode
indicator in addition to the input functionality. This reset output feature allows a
Z8FMC16100 Series Flash MCU device to reset other components to which it is con-
nected, even if the reset is caused by internal sources such as POR, VBO, or WDT events
and as an indication of when the reset sequence completes.

Once an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 6 has elapsed.

On-Chip Debugger Initiated Reset

A System Reset may be initiated via the On-Chip Debugger by setting

RST

bit of the

OCDCTL register. The On-Chip Debugger is not reset but the rest of the chip goes
through a normal system reset. The

RST

bit automatically clears during the system reset.

Following the system reset, the

POR

bit in the

Reset Status and Control Register

is set.

Fault Detect Logic Reset

Fault detect circuitry exists to detect illegal state changes which may be caused by tran-
sient power or electrostatic discharge events. When such a fault is detected, a system reset
is forced. Following the system reset, the

FLTD

bit in the

Reset Status and Control Register

is set.

Reset and Stop-Mode Recovery

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Stop-Mode Recovery

STOP mode is entered by execution of a

STOP

instruction by the eZ8 CPU. Refer to the

Low-Power Modes

chapter on page 31 for detailed STOP mode information. During Stop-

Mode Recovery, the device is held in reset for 66 cycles of the Internal Precision Oscilla-
tor. Stop-Mode Recovery only affects the contents of the

Reset Status and Control Regis-

ter

and

Oscillator Control Register

. Stop-Mode Recovery does not affect any other values

in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral control
registers, and general-purpose RAM.

The eZ8 CPU fetches the Reset vector at Program Memory addresses

0002h

and

0003h

and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop-Mode Recovery, the

STOP

bit in the

Reset Status and Control

is set to 1. Table 8 lists the Stop-Mode Recovery sources and resulting actions.

The text following provides more detailed information on each of the Stop-Mode Recov-
ery sources

Stop-Mode Recovery Using Watch-Dog Timer Time-Out

If the Watch-Dog Timer times out during STOP mode, the device undergoes a Stop-Mode
Recovery sequence. In the

Reset Status and Control Register

, the

WDT

and

STOP

bits are

set to 1. If the Watch-Dog Timer is configured to generate a System Exception upon time-
out, the eZ8 CPU services the Watch-Dog Timer System Exception following the normal
Stop-Mode Recovery sequence.

Stop-Mode Recovery Using a GPIO Port Pin Transition

Each of the GPIO port pins may be configured as a Stop-Mode Recovery input source. On
any GPIO pin enabled as a Stop-Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop-Mode Recovery. The GPIO Stop-
Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in duration. In
the

Reset Status and Control Register

, the STOP bit is set to 1.

Table 8. Stop-Mode Recovery Sources and Resulting Action

Operating Mode

Stop-Mode Recovery Source

Action

Stop Mode

Watch-Dog Timer time-out when
configured for Reset

Stop-Mode Recovery

Watch-Dog Timer time-out when
configured for System Exception

Stop-Mode Recovery followed by WDT
System Exception

Data transition on any GPIO port pin
enabled as a Stop-Mode Recovery
source

Stop-Mode Recovery

PS024604-1005

P R E L I M I N A R Y

PWM Fault0 and Reset pin selection

Z8FMC16100 Series Flash MCU

Product Specification

Short pulses on the Port pin can initiate Stop-Mode Recovery without initiating an in-
terrupt (if enabled for that pin).

PWM Fault0 and Reset pin selection

The RESET pin can be set to function as a PWM Fault input. When selected, the RESET
input function is disabled. The

FLTSEL

bit in the

Reset Status and Control Register

allows

software selection of the RESET pin function. The pin function is selected by writing the
the unlock sequence followed by the mode to this register. A software write to the

FLTSEL

bit will override the value set by the

FLTSEL

user option bit

Reset Control Register Definitions

Writing the

14h

92h

unlock sequence to the Reset Status and Control Register address

unlocks access to the

FLTSEL

bit. The locking mechanism prevents spurious writes to this

bit. The following sequence is required to unlock this register and write the

FLTSEL

bit.

1. Write

14h

to the Reset Status and Control Register (RSTSTAT).

2. Write

92h

to the Reset Status and Control Register (RSTSTAT).

3. Write the

FLTSEL

bit.

All steps of the unlock sequence must be written in the order listed.

Reset Status and Control Register

The Reset Status (RSTSTAT) Register, shown in Table 9, records the cause of the most
recent Reset or Stop-Mode Recovery. All status bits are updated on each Reset or Stop-
Mode Recovery event. Table 10 indicates the possible states of the Reset status bits fol-
lowing a Reset or Stop-Mode Recovery event. The RESET pin function is also select with

FLTSEL

bit.

Caution:

Reset and Stop-Mode Recovery

P R E L I M I N A R Y

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The

FLTSEL

bit in this register allows software selection of the RESET pin. The pin func-

tion is selected by writing the unlock sequence followed by the mode to this register. A
software write to the

FLTSEL

bit will override the value set by the

FLTSEL

user option bit.

0 =

RESET/Fault0 pin is configured as RESET input.

RESET/Fault0 pin is configured as Fault0 input.

Table 9. Reset Status and Control Register (RSTSCR)

BITS

FIELD

POR

STOP

WDT

EXT

FLT

Reserved

FLTSEL

RESET

See Table 10 below

R/W

R/W

ADDR

FF0H

Table 10. Reset Status Register Values Following Reset

Reset or Stop-Mode Recovery Event

POR

STOP

WDT

EXT

FLT

Power-On Reset

Reset using RESET pin assertion

Reset using Watch-Dog Timer time-out

Reset by OCD writing OCDCTL[0] to 1

Reset from Fault Detect Logic

Stop-Mode Recovery using GPIO pin transition

Stop-Mode Recovery using Watch-Dog Timer time-out

Note: Additional bits may be set depending on the number of resets simultaneously occurring.

PS024604-1005

P R E L I M I N A R Y Stop

Mode

Z8FMC16100 Series Flash MCU

Product Specification

Low-Power Modes

The Z8FMC16100 Series Flash MCU products contain power-saving features. The high-
est level of power reduction is provided by STOP mode. The next level of power reduction
is provided by the HALT mode.

Stop Mode

Execution of the eZ8 CPU's STOP instruction places the Z8FMC16100 Series Flash MCU
into STOP mode. In STOP mode, the operating characteristics are:

�

Primary crystal oscillator and IPO are stopped; XIN and XOUT pins are driven to V

�

System clock is stopped

�

eZ8 CPU is stopped

�

Program counter (PC) stops incrementing

�

If enabled for operation during STOP mode, the Watch-Dog Timer and its internal RC
oscillator continue to operate.

�

If enabled for operation in STOP mode through the associated Option Bit, the Voltage
Brown-Out protection circuit continues to operate.

�

Comparators and voltage reference operate unless disabled.

�

All other on-chip peripherals are idle

To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (V

or GND), the Voltage Brown-Out protection

and the Watch-Dog Timer must be disabled. The device can be brought out of STOP mode
using Stop-Mode Recovery. For more information refer to the

Reset and Stop-Mode

Recovery

chapter on page 23.

To prevent excess current consumption, STOP mode must not be used if the device is
driven with an external clock source.

Halt Mode

Execution of the eZ8 CPU's HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:

�

Primary crystal oscillator is enabled and continues to operate

Caution:

Low-Power Modes

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Product Specification

�

System clock is enabled and continues to operate

�

eZ8 CPU is stopped

�

Program counter (PC) stops incrementing

�

Watch-Dog Timer's internal RC oscillator continues to operate

�

If enabled, the Watch-Dog Timer continues to operate

�

All other on-chip peripherals continue to operate

The eZ8 CPU can be brought out of HALT mode by any of the following operations:

�

Interrupt or System Exception

�

Watch-Dog Timer time-out (System Exception or reset)

�

Power-on reset

�

Voltage-brown out reset

�

External RESET pin assertion

�

Halt Mode Recovery time is less than 5 �s.

To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (V

or GND).

Peripheral-Level Power Control

In addition to the STOP and HALT modes, it is possible to disable unused on-chip analog
peripherals of the Z8FMC16100 Series Flash MCU device during operation. Disabling an
unused analog peripheral minimizes power consumption. Power consumption of the
unused on-chip digital peripherals is automatically minimized when not in use.

PS024604-1005

P R E L I M I N A R Y

GPIO Port Availability By Device

Z8FMC16100 Series Flash MCU

Product Specification

General-Purpose I/O

The Z8FMC16100 Series Flash MCU contains general-purpose input/output pins (GPIO)
arranged as Ports A�C. Each port contains control and data registers. The GPIO control
registers are used to determine data direction, open-drain, output drive current, pull-up,
and alternate pin functions. Each port pin is individually programmable.

GPIO Port Availability By Device

Table 12 lists the port pins available with each device and package type.

Architecture

Figure 5 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength are not
illustrated.

Table 12. Port Availability by Device and Package Type

Package

Port A

Port B

Port C

32-pin

[7:0]

[0]

General-Purpose I/O

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GPIO Alternate Functions

Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions, such as timers and serial communication devices. The Port
A-C Alternate Function subregisters configure these pins for either general-purpose I/O or
alternate function operation. When a pin is configured for alternate function, control of the
port pin direction (input/output) is passed from the Port A-C Data Direction registers to
the alternate function assigned to this pin. For peripherals with digital input alternate func-
tions (for example, a Timer input T0IN0), selecting the alternate function is not required.

Table 13 lists the alternate functions associated with each port pin and the required alter-
nate function (AF0 and AF1) subregister settings. In general, enabling an analog alternate

Figure 5. GPIO Port Pin Block Diagram

System Clock

Data Bus

Pull-Up Enable

Schmitt Trigger

Port

GND

Port Input

Data Register

Port Output

Data Register

System Clock

Port Output Control

Port Data Direction

Analog In/Out

On-Chip

Peripheral

Alternate Function

Digital Input

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P R E L I M I N A R Y

GPIO Alternate Functions

Z8FMC16100 Series Flash MCU

Product Specification

function automatically disables the digital Schmitt-trigger input for the associated port
input.

Table 13. Port Alternate Function Mapping

Port

Pin

Mnemonic

AF0

AF1 Alternate Function Description

Port A

PA7

GPIO.

T0OUT

Timer 0 output (active Low).

FAULT1

Fault Input.

COMPOUT

Comparator output.

PA6

GPIO.

SPI Slave Select.

CTS

UART Clear to Send.

SDA

C Serial Data.

PA5

GPIO.

MOSI

SPI Master Out Slave In.

TXD

UART Transmit data.

Reserved; do not use.

PA4

GPIO.

MISO

SPI Master In Slave Out.

RXD

UART Receive data.

Reserved; do not use.

PA3

GPIO.

SCK

SPI Serial Clock.

TXDE

UART Driver Enable.

SCL

C serial clock.

PA2

GPIO.

Reserved; do not use.

CINP

Comparator Positive Input.

Reserved; do not use.

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Port A

PA1

GPIO.

Reserved; do not use.

OPINP and CINN

Op amp positive input and comparator negative
input.

Reserved; do not use.

PA0

GPIO.

Reserved; do not use.

OPINN

Op amp negative input.

Reserved; do not use.

Port B

PB7

GPIO.

Reserved; do not use.

ANA7

ADC analog input 7.

Reserved; do not use.

PB6

GPIO.

Reserved; do not use.

ANA6

ADC analog input 6.

Reserved; do not use.

PB5

GPIO.

Reserved; do not use.

ANA5

ADC analog input 5.

Reserved; do not use.

PB4

GPIO.

Reserved; do not use.

ANA4

ADC analog input 4 (also CINN if CPSEL=1).

Reserved; do not use.

PB3

GPIO.

PB3INT

GPIO with edge interrupt.

ANA3 and OPOUT

ADC analog input 3 and op amp output.

Reserved; do not use.

Table 13. Port Alternate Function Mapping (Continued)

Port

Pin

Mnemonic

AF0

AF1 Alternate Function Description

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P R E L I M I N A R Y GPIO

Interrupts

Z8FMC16100 Series Flash MCU

Product Specification

GPIO Interrupts

Many of the GPIO port pins can be used as interrupt sources. The Port A[7:0] pins can be
configured to generate an interrupt request on either the rising edge or falling edge of the
pin input signal. The Port B[3:0] pins can be configured to generate an interrupt request on
both the rising and falling edges of the pin input signal. For Port A, the GPIO interrupt
edge selection is controlled by the Interrupt Edge Select subregister. Enabling and dis-
abling of the Port Interrupts is handled in the Interrupt Controller. Port B[3:0], with dual
edge interrupt capability, is selected by AF1, AF0. Refer to the

Interrupt Controller

chap-

ter on page 51 for more information.

GPIO Control Register Definitions

Four registers for each Port provide access to GPIO control, input data, and output data.
Table 14 lists these Port registers. Use the Port A�C Address and Control registers
together to provide access to subregisters for Port configuration and control.

Port B

PB2

GPIO/Timer 0 input 2.

PB2INT

GPIO/Timer 0 input 2--edge interrupt enabled.

ANA2

ADC analog input 2.

T0IN2

Timer 0 input 2; dedicated input.

PB1

GPIO/Timer 0 input 1.

PB1INT

GPIO/Timer 0 input 1--edge interrupt enabled.

ANA1

ADC analog input 1.

Reserved; do not use.

PB0

GPIO/Timer 0 input 0.

PB0INT

GPIO/Timer 0 input 0--edge interrupt enabled.

ANA0

ADC analog input 0.

Reserved; do not use.

Port C

PC0

GPIO.

Reserved; do not use.

T0OUT

Timer 0 output.

Reserved; do not use.

Table 13. Port Alternate Function Mapping (Continued)

Port

Pin

Mnemonic

AF0

AF1 Alternate Function Description

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Port A-C Address Registers

The Port A�C Address registers select the GPIO port functionality accessible through the
Port A�C Control registers. The Port A�C Address and Control registers combine to pro-
vide access to all GPIO port control. See Table 15.

Table 16 lists the Port Control subregisters that are accessible via the Port A�C Control
registers.

Table 14. GPIO Port Registers and Subregisters

Port Register Mnemonic

Port Register Name

PxADDR

Port A�C Address Register--selects subregisters.

PxCTL

Port A�C Control Register--provides access to
subregisters.

PxIN

Port A�C Input Data Register.

PxOUT

Port A�C Output Data Register.

Port Subregister Mnemonic

Port Register Name

PxDD

Data Direction

PxAF0

Alternate Function 0

PxAF1

Alternate Function 1--Ports A and B only.

PxOC

Output Control (open-drain).

PxHDE

High Drive Enable.

PxSMRE

Stop-Mode Recovery Source Enable.

PxPUE

Pull-Up Enable.

PxIRQES

Interrupt Edge Select--Ports A and C only.

IRQPSEL

Interrupt Port Select--Port A only.

Table 15. Port A�C GPIO Address Registers (PxADDR)

BITS

FIELD

PADDR[7:0]

RESET

00H

R/W

R/W

ADDR

FD0H, FD4H, FD8H

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P R E L I M I N A R Y

Port A�C Control Registers

Z8FMC16100 Series Flash MCU

Product Specification

Port A�C Control Registers

The Port A�C Control registers set the GPIO port operation. The value in the correspond-
ing Port A�C Address register determines the control subregisters accessible using the
Port A�C Control registers, shown in Table 17. The Port Control registers provide access
to all subregisters that configure GPIO port operation.

Port A�C Data Direction Subregisters

The Port A�C Data Direction subregisters are accessed through the Port A�C Control reg-
isters by writing

01h

to the Port A�C Address registers. See Table 18.

Table 16. Port Control Subregisters by Port Address

Port
Address

Port Control Subregisters

00h

No function; provides some protection against accidental port
reconfiguration.

01h

Data direction.

02h

Alternate Function 0

03h

Output Control (open-drain).

04h

High Drive Enable.

05h

Stop-mode recovery source enable.

06h

Pull-up enable.

07h

Alternate Function 1--ports A and B only.

08h

Interrupt Edge Select - Port A and Port C only

09h

Port Interrupt Select Register - Port A only

0Ah�FFh

No Function

Table 17. Port A�C Control Registers (PxCTL)

BITS

FIELD

PCTL

RESET

00H

R/W

R/W

ADDR

FD1H, FD5H, FD9H

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In each of these three data direction subregisters, bits [7:0] control the direction of the
associated port pin. Port Alternate Function operation overrides the Data Direction Regis-
ter setting.

If the value of the bit is 0, the direction is output, and data in the Port A�C Output Data
registers is driven onto the port pin.

If the value of the bit is 1, the direction is input. The port pin is sampled, the value is writ-
ten into the Port A�C Input Data registers, and the output driver is tristated.

Port A�B Alternate Function 0 Subregisters

The Port A�B Alternate Function subregisters, shown in Table 19, are accessed through
the Port A�B Control registers by writing

02h

to the Port A�B Address registers. The Port

A�B Alternate Function subregisters select the alternate functions for the selected pins.
Refer to the

GPIO Alternate Functions

section on page 36 to determine the alternate func-

tion associated with each port pin.

Do not enable alternate function for GPIO port pins which do not have an associated al-
ternate function. Failure to follow this guideline may result in unpredictable operation.

Table 18. Port A�C Data Direction Sub-Registers

BITS

FIELD

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

RESET

R/W

R/W

ADDR

If 01H in Port A�C Address Register, accessible through the Port A-C Control Register

Bit

Position

Value

(H)

Description

[7:0]
Data
Direction

These bits control the direction of the associated port pin. Port Alternate Function
operation overrides the Data Direction register setting.
Output. Data in the Port A�C Output Data register is driven onto the port pin.

Input. The port pin is sampled and the value written into the Port A�C Input Data
Register. The output driver is tristated

Caution:

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P R E L I M I N A R Y

Port A�C Control Registers

Z8FMC16100 Series Flash MCU

Product Specification

Port A�C Output Control Subregisters

The Port A�C Output Control subregisters, shown in Table 20, are accessed through the
Port A�C Control registers by writing

03h

to the Port A�C Address registers. Setting the

bits in the Port A�C Output Control subregisters to 1 configures the specified port pins for
open-drain operation. These subregisters affect the pins directly and, as a result, alternate
functions are also affected.

Table 19. Port A�B Alternate Function 0 Sub-Registers

BITS

FIELD

AF0_7

AF0_6

AF0_5

AF0_4

AF0_3

AF0_2

AF0_1

AF0_0

RESET

R/W

R/W

ADDR

If 02H in Port A-C Address Register, accessible through the Port A-C Control Register

Bit

Position

Value

(H)

Description

[7:0]

AF0

Port Alternate Function 0 select.
The alternate function 0 function is not selected.

The alternate function 0 function is selected.

Table 20. Port A�C Output Control Sub-Registers

BITS

FIELD

POC7

POC6

POC5

POC4

POC3

POC2

POC1

POC0

RESET

R/W

R/W

ADDR

If 03H in Port A�C Address Register, accessible through the Port A�C Control Register

Bit

Position

Value

(H)

Description

[7:0]

POC

Port Output Control

These bits function independently of the alternate function bit and disable the
drains if set to 1.

The drains are enabled for any output mode.

The drain of the associated pin is disabled (open-drain mode).

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Port A�C High Drive Enable Subregisters

The Port A�C High Drive Enable subregisters, shown in Table 21, are accessed through
the Port A-C Control registers by writing

04h

to the Port A�C Address registers. Setting

the bits in the Port A�C High Drive Enable subregisters to 1 configures the specified port
pins for high current output drive operation. The Port A�C High Drive Enable subregisters
affect the pins directly and, as a result, alternate functions are also affected.

Port A�C Stop-Mode Recovery Source Enable Subregisters

The Port A�C Stop-Mode Recovery Source Enable subregisters, shown in Table 22, are
accessed through the Port A�C Control registers by writing

05h

to the Port A-C Address

registers. Setting the bits in the Port A�C Stop-Mode Recovery Source Enable subregisters
to 1 configures the specified port pins as a Stop-Mode Recovery source. During STOP
mode, any logic transition on a port pin enabled as a Stop-Mode Recovery source initiates
Stop-Mode Recovery.

Table 21. Port A�C High Drive Enable Sub-Registers

BITS

FIELD

PHDE7

PHDE6

PHDE5

PHDE4

PHDE3

PHDE2

PHDE1

PHDE0

RESET

R/W

R/W

ADDR

If 04H in Port A-C Address Register, accessible through the Port A-C Control Register

Bit

Position

Value

(H)

Description

[7:0]

PHDE

Port High Drive Enable

The Port pin is configured for standard output current drive.

The Port pin is configured for high output current drive.

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P R E L I M I N A R Y

Port A�C Control Registers

Z8FMC16100 Series Flash MCU

Product Specification

Port A�C Pull-Up Enable Subregisters

The Port A�C Pull-Up Enable subregisters, shown in Table 23, are accessed through the
Port A�C Control registers by writing

06h

to the Port A�C Address registers. Setting the

bits in the Port A�C Pull-Up Enable subregisters enables a weak internal resistive pull-up
on the specified port pins.

Table 22. Port A�C STOP Mode Recovery Source Enable Sub-Registers

BITS

FIELD

PSMRE7

PSMRE6

PSMRE5

PSMRE4

PSMRE3

PSMRE2

PSMRE1

PSMRE0

RESET

R/W

R/W

ADDR

If 05H in Port A�C Address Register, accessible through the Port A�C Control Register

Bit

Position

Value

(H)

Description

[7:0]

PSMRE

Port STOP Mode Recovery Source Enable

The Port pin is not configured as a STOP Mode Recovery source. Transitions on
this pin during STOP mode do not initiate STOP Mode Recovery.

The Port pin is configured as a STOP Mode Recovery source. Any logic
transition on this pin during STOP mode initiates STOP Mode Recovery.

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Port A Interrupt Edge Select Subregister

The Interrupt Edge Select (IRQES) Subregister, shown in Table 24, determines whether an
interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input
pin.

Table 23. Port A�C Pull-Up Enable Sub-Registers

BITS

FIELD

PPUE7

PPUE6

PPUE5

PPUE4

PPUE3

PPUE2

PPUE1

PPUE0

RESET

R/W

R/W

ADDR

If 06H in Port A�C Address Register, accessible through the Port A�C Control Register

Bit

Position

Value

(H)

Description

[7:0]

PPUE

Port Pull-Up Enable

The weak pull-up on the Port pin is disabled.

The weak pull-up on the Port pin is enabled.

Table 24. Interrupt Edge Select Sub-Register (IRQES)

BITS

FIELD

Reserved

IES3

IES2

IES1

IES0

RESET

R/W

R/W

ADDR

If 08H in Port A Address Register, accessible through the Port A and Port C Control Register

Bit

Position

Value

(H)

Description

[3:0]

IESx

Interrupt Edge Select x

An interrupt request is generated on the falling edge of the PAx input.

An interrupt request is generated on the rising edge of the PAx input,

where x indicates the specific GPIO Port pin number (0 through 7).

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P R E L I M I N A R Y

Port A�C Control Registers

Z8FMC16100 Series Flash MCU

Product Specification

Interrupt Port Select Register

The Interrupt Port Select Register, shown in Table 25, is used to select which Port A pins
are used as interrupts.

Port B Alternate Function 1 Subregisters

The Port B Alternate Function Subregisters, shown in Table 26, is accessed through the
Port B Control Register by writing

08H

to the Port B Address Register. The Port B Alter-

nate Function subregister selects the alternate functions for the selected pins. Refer to the

GPIO Alternate Functions

section on page 36 to determine the alternate function associ-

ated with each port pin.

Do not enable alternate function for GPIO port pins which do not have an associated al-
ternate function. Failure to follow this guideline may result in unpredictable operation.

Table 25. Interrupt Port Select Sub-Register (IRQPS)

BITS

FIELD

Reserved

PA73SEL PA62SEL PA51SEL PA40SEL

RESET

R/W

R/W

ADDR

If 09H in Port A Address Register, accessible through the Port A and Port C Control Register

Bit

Position

Value

(H)

Description

[3:0]

PAxxSEL

Interrupt Port Select x

An interrupt request is generated on PAx, where x indicates (0 through 3)

An interrupt request is generated on PAx, where x indicates (4 through 7)

Caution:

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Port A-C Input Data Registers

Reading from the Port A�C Input Data registers, shown in Table 27, return the sampled
values from the corresponding port pins. The Port A�C Input Data registers are read-only.
Sampled data are from the corresponding port pin input.

Table 26. Port A�B Alternate Function 1 Sub-Registers

BITS

FIELD

AF1_7

AF1_6

AF1_5

AF1_4

AF1_3

AF1_2

AF1_1

AF1_0

RESET

R/W

R/W

ADDR

If 07H in Port A-C Address Register, accessible through the Port A-C Control Register

Bit

Position

Value

(H)

Description

[7:0]

AF1

Port Alternate Function 1 select.
The alternate function 1 function is not selected.

The alternate function 1 function is selected.

Table 27. Port A-C Input Data Registers (PxIN)

BITS

FIELD

PIN7

PIN6

PIN5

PIN4

PIN3

PIN2

PIN1

PIN0

RESET

R/W

ADDR

FD2H, FD6H, FDAH

Bit

Position

Value

(H)

Description

[7:0]

Port Input Data x

Input data is a logical 0 (Low).

Input data is a logical 1 (High).

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P R E L I M I N A R Y

Port A�C Output Data Registers

Z8FMC16100 Series Flash MCU

Product Specification

Port A�C Output Data Registers

The Port A�C Output Data registers, shown in Table 28, write output data to the pins.
These bits contain the data to be driven out from the port pins. The values are only driven
if the corresponding pin is configured as an output and the pin is not configured for alter-
nate function operation.

Table 28. Port A-C Output Data Register (PxOUT)

BITS

FIELD

POUT7

POUT6

POUT5

POUT4

POUT3

POUT2

POUT1

POUT0

RESET

R/W

R/W

ADDR

FD3H, FD7H, FDBH

Bit

Position

Value

(H)

Description

[7:0]

POUT

Port Output Data x

Drive is a logical 0 (Low).

Drive is a logical 1 (High). High value is not driven if the drain has been disabled
by setting the corresponding Port Output Control register bit to 1.

PS024604-1005

P R E L I M I N A R Y Interrupt and System Exception Vector Listing

Z8FMC16100 Series Flash MCU

Product Specification

Interrupt Controller

The interrupt controller on the Z8FMC16100 Series Flash MCU prioritizes the system
exceptions and interrupt requests from the on-chip peripherals and the GPIO port pins.
The features of the interrupt controller include the following:

�

Multiple GPIO interrupts

�

Interrupts for on-chip peripherals

�

Nonmaskable system exceptions

�

Three levels of individually programmable interrupt priority

�

20 sources of interrupts for the interrupt controller, 9 of the sources can be configured
from GPIO pins

System exceptions (SEs) and interrupt requests (IRQs) allow peripheral devices to sus-
pend CPU operation in an orderly manner and force the CPU to start a service routine.
Interrupt service routines are involved with the exchange of data, status information, or
control information between the CPU and the interrupting peripheral. When the service
routine is completed, the CPU returns to the operation from which it was interrupted.

The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual
(UM0128) for more information regarding interrupt servicing by the eZ8 CPU. The eZ8
CPU User Manual is available for download at

www.zilog.com

Interrupt and System Exception Vector Listing

Table 29 lists the system exceptions and the interrupts in order of priority. Reset and sys-
tem exceptions always have priority over interrupts. The system exception and interrupt
vectors are stored with the most significant byte (MSB) at the even Program Memory
address and the least significant byte (LSB) at the following odd Program Memory
address.

Port interrupts are only available in those packages which support the associated port pins.

Note:

Interrupt Controller

P R E L I M I N A R Y

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Table 29. Reset, System Exception, and Interrupt Vectors in Order of Priority

Priority

Program Memory

Vector Base

Address

Programmable

Priority?

Interrupt or Trap Source

Reset and System Exceptions

0002h

Reset

0004h

Watch-Dog Timer (see the

Watch-Dog Timer

chapter on

page 63)

003AH

Primary Oscillator Fail Trap

003CH

Watch-Dog Timer Oscillator Fail Trap

0006h

Illegal Instruction Trap

Interrupts (maskable)

Highest 0008h

Yes

PWM Timer

000Ah

Yes

PWM Fault

000Ch

Yes

ADC

000Eh

Yes

Comparator output rising and falling edge

0010h

Yes

Timer 0

0012H

Yes

UART 0 receiver

0014H

Yes

UART 0 transmitter

0016H

Yes

SPI

0018H

Yes

001AH

Yes

Reserved

001CH

Yes

Port C0 with selectable rising or falling input edge

001EH

Yes

Port B[3:0] rising and fall input edge

0020h

Yes

Port A7/A3 with selectable rising or falling input edge

0022H

Yes

Port A6/A2 with selectable rising or falling input edge

0024H

Yes

Port A5/A1 with selectable rising or falling input edge

0026H

Yes

Port A4/A0 with selectable rising or falling input edge

Lowest

0028H�0039H

N/A

Reserved

PS024604-1005

P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

Architecture

Figure 6 illustrates a block diagram of the interrupt controller.

Master Interrupt Enable

The master interrupt enable bit (

IRQE

) in the Interrupt Control Register globally enables

and disables interrupts.

Interrupts are globally enabled by any of the following actions:

�

Execution of an Enable Interrupt (EI) instruction

�

Execution of a Return from Interrupt (IRET) instruction

�

Writing a 1 to the

IRQE

bit in the Interrupt Control Register

Interrupts are globally disabled by any of the following actions:

�

Execution of a Disable Interrupt (DI) instruction

�

eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller

�

Writing a 0 to the

IRQE

bit in the Interrupt Control Register

�

Reset

Figure 6. Interrupt Controller Block Diagram

Port Interrupts

Vector

Service Request

High

Priority

Medium

Priority

Mix

Low

Priority

Internal Interrupts

System Exceptions

Interrupt Request Latches and Control

Interrupt Controller

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�

Execution of a Trap instruction

�

Illegal Instruction trap

System Exceptions

The Z8FMC16100 Series Flash MCU supports multiple system exceptions. System
exceptions are generated for the following events:

�

Illegal Instruction trap

�

Watch-Dog Timer interrupt

�

Watch-Dog Timer RC oscillator failure

�

Primary oscillator failure

System exceptions, excluding the Watch-Dog Timer interrupt, are nonmaskable and there-
fore cannot be disabled by the interrupt controller (setting

IRQE

to 0 has no effect).

Interrupt Vectors and Priority

The interrupt controller supports three levels of interrupt priority. Level 3 interrupts are
always higher priority than Level 2 interrupts. Level 2 interrupts are always higher priority
than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3),
priority is assigned as specified in Table 29.

Interrupt Assertion

When an interrupt request occurs, the corresponding bit in the Interrupt Request Register
is set. This bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service
Routine (ISR). Writing a 0 to the corresponding bit in the Interrupt Request Register also
clears the interrupt request.

If an interrupt is disabled, software can poll the appropriate interrupt request register bit
and clear the bit directly. The following style of coding to clear bits in the Interrupt Re-
quest registers is not recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.

The following code segment is an example of a poor coding style that can result in lost
interrupt requests:

LDX r0, IRQ0

AND r0, MASK

Q0, r0

Caution:

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P R E L I M I N A R Y Software

Interrupt

Assertion

Z8FMC16100 Series Flash MCU

Product Specification

To avoid missing interrupts, ZiLOG recommends the following style of coding to clear
bits in the Interrupt Request 0 Register:

ANDX IRQ0, MASK

Software Interrupt Assertion

Program code can generate interrupts directly. Writing a 1 to the appropriate bit in the
Interrupt Request Register triggers an interrupt (assuming that interrupt is enabled). This
bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service Routine
(ISR).

The following style of coding to generate software interrupts by setting bits in the Inter-
rupt Request registers is not recommended. All incoming interrupts that are received be-
tween execution of the first LDX command and the last LDX command are lost.

The following code segment is an example of a poor coding style that can result in lost
interrupt requests:

LDX r0, IRQ0

OR r0, MASK

LDX IRQ0, r0

To avoid missing interrupts, ZiLOG recommends the following style of coding to set
bits in the Interrupt Request registers:

ORX IRQ0, MASK

Interrupt Control Register Definitions

The interrupt control registers enable individual interrupts, set interrupt priorities, and
indicate interrupt requests.

Interrupt Request 0 Register

The Interrupt Request 0 (IRQ0) Register, shown in Table 30, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt con-
troller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the
Interrupt Request 0 register to determine if any interrupt requests are pending.

Caution:

Interrupt Controller

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Table 30. Interrupt Request 0 Register (IRQ0)

BITS

FIELD

PWMI

FLTI

ADCI

CMPI

T0I

U0RXI

U0TXI

SPII

RESET

R/W

R/W

ADDR

FC0H

Bit

Position

Value

(H)

Description

[7]

PWMI

PWM Timer Interrupt Request
No interrupt request is pending for the Pulse-Width Modulator.

An interrupt request from the Pulse-Width Modulator is awaiting service.

[6]

FLTI

Fault Interrupt Request. The fault interrupt is generated in the PWM module and
originates from the Fault0 pin, Fault1 pin or the Comparator output. An interrupt
enable for each of these sources exists in the PWM module.
No Fault interrupt request is pending.

A Fault interrupt request is awaiting service.

[5]

ADCI

ADC Interrupt Request
No interrupt request is pending for the Analog to Digital Converter.

An interrupt request from the Analog to Digital Converter is awaiting service.

[4]

CMPI

Comparator Interrupt Request

No interrupt request is pending for the Comparators.

An interrupt request from the Comparators is awaiting service.

[3]

T0I

Timer 0 Interrupt Request
No interrupt request is pending for Timer 0.

An interrupt request from Timer 0 is awaiting service.

[2]

U0RXI

UART 0 Receiver Interrupt Request
No interrupt request is pending for the UART 0 receiver.

An interrupt request from the UART 0 receiver is awaiting service.

[1]

U0TXI

UART 0 Transmitter Interrupt Request
No interrupt request is pending for the UART 0 transmitter.

An interrupt request from the UART 0 transmitter is awaiting service.

[0]

SPII

SPI Interrupt Request
No interrupt request is pending for the SPI.

An interrupt request from the SPI is awaiting service.

PS024604-1005

P R E L I M I N A R Y

Interrupt Request 1 Register

Z8FMC16100 Series Flash MCU

Product Specification

Interrupt Request 1 Register

The Interrupt Request 1 (IRQ1) Register, shown in Table 31, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 Register to determine if any interrupt requests are pending.

Table 31. Interrupt Request 1 Register (IRQ1)

BITS

FIELD

I2CI

Reserved

PC0I

PBI

PA73I

PA62I

PA51I

PA40I

RESET

R/W

R/W

ADDR

FC3H

Bit

Position

Value

(H)

Description

[7]

I2CI

I2C Interrupt Request
No interrupt request is pending for I2C.

An interrupt request from I2C is awaiting service.

[5]

PC0I

PC0 Interrupt Request -- Logic in the Port C GPIO module selects either the
rising or falling edge.
No interrupt request is pending for PC0.

An interrupt request from PC0 is awaiting service.

[4]

PBI

PB3 � PB0 Interrupt Request
No interrupt request is pending for any PB3 � PB0.

An interrupt request from PB3 � PB0 is awaiting service.

[3]
PA73I

PA7 or PA3 Interrupt Request -- Logic in the Port A GPIO module selects either
PA7 or PA3 and either rising or falling edge.
No interrupt request is pending for PA7 or PA3

An interrupt request from PA7 or PA3 is awaiting service.

[2]
PA62I

PA6 or PA2 Interrupt Request -- Logic in the Port A GPIO module selects either
PA6 or PA2 and either rising or falling edge.
No interrupt request is pending for PA6 or PA2

An interrupt request from PA6 or PA2 is awaiting service.

Interrupt Controller

P R E L I M I N A R Y

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Product Specification

IRQ0 Enable High and Low Bit Registers

The IRQ0 Enable High and Low Bit registers, shown in Tables 33 and 34, form a priority
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register. Table 32 describes the priority control for IRQ0.

PWMENH--Pulse-Width Modulator Interrupt Request Enable High Bit

FLTENH--Fault Interrupt Request Enable High Bit

ADCENH--ADC Interrupt Request Enable High Bit

CMPENH--Comparator Interrupt Request Enable High Bit

[1]
PA51I

PA5 or PA1 Interrupt Request -- Logic in the Port A GPIO module selects either
PA5 or PA1 and either rising or falling edge.
No interrupt request is pending for PA5 or PA1

An interrupt request from PA5 or PA1 is awaiting service.

[0]
PA40I

PA4 or PA0 Interrupt Request -- Logic in the Port A GPIO module selects either
PA4 or PA0 and either rising or falling edge.
No interrupt request is pending for PA4 or PA0

An interrupt request from PA4 or PA0 is awaiting service.

Table 32. IRQ0 Enable and Priority Encoding

IRQ0ENH[x] IRQ0ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Nominal

Level 3

High

Note: x indicates the register bits from 0 through 7.

Table 33. IRQ0 Enable High Bit Register (IRQ0ENH)

BITS

FIELD

PWMENH

FLTENH

ADCENH CMPENH

T0ENH

U0RENH

U0TENH

SPIENH

RESET

R/W

R/W

ADDR

FC1H

Bit

Position

Value

(H)

Description

PS024604-1005

P R E L I M I N A R Y

IRQ1 Enable High and Low Bit Registers

Z8FMC16100 Series Flash MCU

Product Specification

T0ENH--Timer 1 Interrupt Request Enable High Bit

U0RENH--UART 0 Receive Interrupt Request Enable High Bit

U0TENH--UART 0 Transmit Interrupt Request Enable High Bit

SPIENH--SPI Interrupt Request Enable High Bit

PWMENL--Pulse-Width Modulator Interrupt Request Enable Low Bit

FLTENL--Fault Interrupt Request Enable Low Bit

ADCENL--ADC Interrupt Request Enable Low Bit

CMPENL--Comparator Interrupt Request Enable Low Bit

T0ENL--Timer 0 Interrupt Request Enable Low Bit

U0RENL--UART 0 Receive Interrupt Request Enable Low Bit

U0TENL--UART 0 Transmit Interrupt Request Enable Low Bit

SPIENL--SPI Interrupt Request Enable Low Bit

IRQ1 Enable High and Low Bit Registers

The IRQ1 Enable High and Low Bit registers, shown in Tables 36 and 37, form a priority
encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by
setting bits in each register. Table 35 describes the priority control for IRQ1.

Table 34. IRQ0 Enable Low Bit Register (IRQ0ENL)

BITS

FIELD

PWMENL

FLTENL

ADCENL

CMPENL

T0ENL

U0RENL

U0TENL

SPIENL

RESET

R/W

R/W

ADDR

FC2H

Table 35. IRQ1 Enable and Priority Encoding

IRQ1ENH[x] IRQ1ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Nominal

Level 3

High

x indicates the register bits from 0 through 7.

Interrupt Controller

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Product Specification

Table 36. IRQ1 Enable High Bit Register (IRQ1ENH)

BITS

FIELD

I2CENH

Reserved

PC0ENH

PBENH

PA73ENH PA62ENH PA51ENH PA40ENH

RESET

R/W

R/W

ADDR

FC4H

Bit

Position

Name

Description

[7]

I2CENH

I2C Interrupt Request Enable High Bit

[5]

PC0ENH Port C0Interrupt Request Enable High Bit

[4]

PBENH

Port B[3:0] Interrupt Request Enable High Bit

[3]

PA73ENH Port A73 Interrupt Request Enable High Bit

[2]

PA62ENH Port A62 Interrupt Request Enable High Bit

[1]

PA51ENH Port A51 Interrupt Request Enable High Bit

[0]

PA40ENH Port A40 Interrupt Request Enable High Bit

Table 37. IRQ1 Enable Low Bit Register (IRQ1ENL)

BITS

FIELD

I2CENL

Reserved

PC0ENL

PBENL

PA73ENL PA62ENL PA51ENL PA40ENL

RESET

R/W

R/W

ADDR

FC5H

Bit

Position

Name

Description

[7]

I2CENL

I2C Interrupt Request Enable Low Bit

[5]

PC0ENL Port C0Interrupt Request Enable Low Bit

[4]

PBENL

Port B[3:0] Interrupt Request Enable Low Bit

PS024604-1005

P R E L I M I N A R Y Interrupt

Control

Z8FMC16100 Series Flash MCU

Product Specification

Interrupt Control Register

The Interrupt Control (IRQCTL) Register, shown in Table 38, contains the Master Enable
Bit (

IRQE

) for all interrupts.

IRQE--Interrupt Request Enable

This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request or system exception,
Reset, or direct register write to 0.

0 = Interrupts are disabled.

1 = Interrupts are enabled.

Reserved--Must be 0.

[3]

PA73ENL Port A73 Interrupt Request Enable Low Bit

[2]

PA62ENL Port A62 Interrupt Request Enable Low Bit

[1]

PA51ENL Port A51 Interrupt Request Enable Low Bit

[0]

PA40ENL Port A40 Interrupt Request Enable Low Bit

Table 38. Interrupt Control Register (IRQCTL)

BITS

FIELD

IRQE

Reserved

RESET

R/W

R/W

ADDR

FCFH

Bit

Position

Name

Description

PS024604-1005

P R E L I M I N A R Y Operation

Z8FMC16100 Series Flash MCU

Product Specification

Watch-Dog Timer

The Watch-Dog Timer (WDT) helps protect against corrupted or unreliable software and
other system-level problems which may place the Z8FMC16100 Series Flash MCU into
unsuitable operating states. The Watch-Dog Timer includes the following features:

�

On-chip RC oscillator

�

A selectable time-out response: Reset or System Exception

�

16-bit programmable time-out value

Operation

The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the
Z8FMC16100 Series Flash MCU when the WDT reaches its terminal count. The Watch-
Dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watch-
Dog Timer has only two modes of operation--on and off. Once enabled, it always counts
and must be refreshed to prevent a time-out. An enable can be performed by executing the
WDT instruction or by setting the

WDT_AO

Option Bit. The

WDT_AO

bit enables the Watch-

Dog Timer to operate all the time, even if a WDT instruction has not been executed.

To minimize power consumption, the RC oscillator can be disabled. The RC oscillator is
disabled by clearing the

WDTEN

bit in the Oscillator Control Register. If the RC oscillator

is disabled, the WDT will not operate.

The Watch-Dog Timer is a 16-bit reloadable downcounter that uses two 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
calculated by the following equation:

where the WDT reload value is assigned by {

WDTH[7:0]

WDTL[7:0]

} and the typical

Watch-Dog Timer RC oscillator frequency is 10 KHz. The user should consider system
requirements when selecting the time out delay. Table 39 provides information on approx-
imate time-out delays for the default and maximum WDT reload values.

WDT Time-Out Period (ms) =

WDT Reload Value

Watch-Dog Timer

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Watch-Dog Timer Refresh

When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to

0000h

unless a

WDT

instruction is executed by the eZ8 CPU. Execution of the

WDT

instruction causes the down-

counter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload
registers. Counting resumes following the reload operation.

When the Z8FMC16100 Series Flash MCU is operating in DEBUG Mode (through the
On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent spurious
Watch-Dog Timer time-outs.

Watch-Dog Timer Time-Out Response

The Watch-Dog Timer times out when the counter reaches

0000h

. A time-out of the

Watch-Dog Timer generates either a system exception or a Reset. The

WDT_RES

Option

Bit determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits
chapter for information regarding programming of the

WDT_RES

Option Bit.

WDT System Exception in Normal Operation

If configured to generate a system exception when a time-out occurs, the Watch-Dog
Timer issues an exception request to the interrupt controller. The eZ8 CPU responds to the
request by fetching the System Exception vector and executing code from the vector
address. After time-out and system exception generation, the Watch-Dog Timer is
reloaded automatically and continues counting.

WDT System Exception in Stop Mode

If configured to generate a system exception when a time-out occurs and the
Z8FMC16100 Series Flash MCU is in STOP mode, the Watch-Dog Timer automatically
initiates a Stop-Mode Recovery and generates a system exception request. Both the WDT
status bit and the

STOP

bit in the

Reset Status and Control Register

section on page 29 are

set to 1 following WDT time-out in STOP mode. Refer to the

Reset and Stop-Mode

Recovery

chapter on page 23 for more information.

Table 39. Watch-Dog Timer Approximate Time-Out Delays

WDT Reload

Value (Hex)

WDT Reload

Value

(Decimal)

Approximate Time-Out Delay

(with 10 KHz Typical WDT Oscillator Frequency)

Typical

Description

0400

1024

102 ms

Reset default value time-out delay.

FFFF

65,536

6.55 s

Maximum time-out delay.

PS024604-1005

P R E L I M I N A R Y

Watch-Dog Timer Reload Unlock Sequence

Z8FMC16100 Series Flash MCU

Product Specification

Following completion of the Stop-Mode Recovery the eZ8 CPU responds to the system
exception request by fetching the System Exception vector and executing code from the
vector address.

WDT Reset in Normal Operation

If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the
device into the Reset state. The

WDT

status bit in the

Reset Status and Control Register

set to 1. Refer to the

Reset and Stop-Mode Recovery

chapter on page 23 for more informa-

tion on Reset and the

WDT

status bit. Following a Reset sequence, the WDT Counter is ini-

tialized with its reset value.

WDT Reset in Stop Mode

If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watch-Dog Timer initiates a Stop-Mode Recovery. Both
the

WDT

status bit and the

STOP

bit in the

Reset Status and Control Register

are set to 1

following WDT time-out in STOP mode. Refer to the

Reset and Stop-Mode Recovery

chapter on page 23 for more information.

Watch-Dog Timer Reload Unlock Sequence

Writing the unlock sequence to the Watch-Dog Timer Reload High (WDTH) Register
address unlocks the two Watch-Dog Timer Reload registers (WDTH and WDTL) to allow
changes to the time-out period. These write operations to the WDTH register address pro-
duce no effect on the bits in the WDTH register. The locking mechanism prevents spurious
writes to the Reload registers. The following sequence is required to unlock the Watch-
Dog Timer Reload registers (WDTH and WDTL) for write access.

1. Write

55H

to the Watch-Dog Timer Reload High register (WDTH).

2. Write

AAH

to the Watch-Dog Timer Reload High register (WDTH).

3. Write the appropriate value to the Watch-Dog Timer Reload High register (WDTH).

4. Write the appropriate value to the Watch-Dog Timer Reload Low register (WDTL).

All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order
just listed. The value in the Watch-Dog Timer Reload registers is loaded into the counter
every time a

WDT

instruction is executed.

Watch-Dog Timer Reload High and Low Byte Registers

The Watch-Dog Timer Reload High and Low Byte (WDTH, WDTL) registers, shown in
Table 40 through Table 41, form the 16-bit reload value that is loaded into the Watch-Dog
Timer when a

WDT

instruction executes. The 16-bit reload value is {WDTH[7:0],

WDTL[7:0]}. Writing to these registers following the unlock sequence sets the appropri-

PS024604-1005

P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

Pulse-Width Modulator

The Z8FMC16100 Series Flash MCU includes a Pulse-Width Modulator (PWM) opti-
mized for Motor Control applications. The PWM features include:

�

6 independent PWM outputs or 3 complementary PWM output pairs

�

Programmable deadband insertion for complementary output pairs

�

Edge-aligned or center-aligned PWM signal generation

�

PWM OFF state is option-bit-programmable

�

PWM outputs driven to OFF state on System Reset

�

Asynchronous disabling of PWM outputs on system fault; outputs are forced to OFF
state

�

FAULT inputs generate pulse-by-pulse or hard shutdown

�

12-bit reload counter with 1-, 2-, 4-, or 8-bit programmable clock prescaler

�

High current source and sink on all PWM outputs

�

PWM pairs can be used as general-purpose inputs when outputs are disabled

�

Analog-to-digital converter synchronized with PWM period

�

Narrow pulse suppression with programmable threshold

Architecture

The PWM unit consists of a master timer to generate the modulator time base and six inde-
pendent compare registers to set the pulse-width modulation for each output. The six out-
puts are designed to provide control signals for inverter drive circuits. As such, the outputs
are grouped into pairs consisting of a High driver and a Low driver output. The output
pairs are programmable to operate independently or as complementary signals. In comple-
mentary output mode, a programmable dead time is inserted to ensure nonoverlapping sig-
nal transitions. The master count and compare values feed into modulator logic that
generates the proper transitions in the output states. Output polarity and fault/OFF state
control logic allows programming of the default OFF states, which forces the outputs to a
safe state in the event a fault in the motor drive is detected.

Figure 7 illustrates the architecture of the PWM modulator.

PS024604-1005

P R E L I M I N A R Y

PWM Off State and Output Polarity

Z8FMC16100 Series Flash MCU

Product Specification

PWM Off State and Output Polarity

The default OFF state and the polarity of the PWM outputs are controlled by the

PWMHI

and

PWMLO

option bits. The

PWMHI

option controls the OFF state and the polarity for the

PWM High outputs 0H, 1H, and 2H. The

PWMLO

option controls the OFF state and the

polarity for the Low outputs 0L, 1L, and 2L.

The OFF state is the value programmed in the option bit. For example, programming

PWMHI

to a 1 sets the OFF state of PWM0H, 1H, and 2H to a High logic value and the

active state a Low logic value. Conversely, programming

PWMHI

to a 0 causes the OFF

state to be a Low logic value.

PWMLO

is programmed in a similar manner.

The relative polarity of the PWM channel pairs is controlled by the

POL

x bits in the PWM

Control 1 Register (PWMCTL1). These bits do not affect the OFF state programmed by
the option bits. Setting these bits inverts the High and Low of the selected channels. The
relative channel polarity controls the order in which the signals of a given PWM pair tog-
gle. If a

POL

x bit is reset to zero, the High will first go active at the start of a PWM period.

Alternately., if the bit is set, the Low will go active first. A switching of the

POL

x bits is

synchronized with the PWM reload event (see below). In complementary mode, the
switch is additionally delayed until the end of the programmed deadband time.

PWM Channel Pair Enable

Following a Power-On Reset (POR), the PWM pins enter a high-impedance state. As the
internal reset proceeds, the PWM outputs are forced to the OFF state as determined by the

PWMHI

and

PWMLO

OFF state option bits.

The

PWM0EN

PWM1EN

, and

PWM2EN

option bits enable the PWM0, PWM1, and PWM2

output pairs, respectively. If a PWM channel pair is not enabled, it remains in a high-
impedance state after reset, and can be used as a general-purpose input.

PWM Reload Event

To prevent erroneous PWM pulse-widths and periods, registers that control the timing of
the output are buffered. Buffering causes all of the PWM compare values to update at the
same time. In other words, the registers that control the duty cycle and clock source pres-
caler only take effect upon a PWM reload event. A PWM reload event can be configured
to occur at the end of each PWM period, or only every 2, 4, or 8 PWM periods by setting
the

RELFREQ

bits in the PWM Control 1 Register (PWMCTL1). The software must indi-

cate that all new values are ready by setting the

READY

bit in the PWM Control 0 Register

(PWMCTL0) to 1. After this

READY

bit has been set to 1, the buffered values take effect

at the next reload event.

Pulse-Width Modulator

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PWM Prescaler

The prescaler allows the PWM clock signal to be decreased by factors of 1, 2, 4, or 8 with
respect to the system clock. The

PRES[1:0]

bit field in the PWM Control 1 Register

(PWMCTL1) controls prescaler operation. This 2-bit

PRES

field is buffered so that the

prescale value only changes upon a PWM reload event.

PWM Period and Count Resolution

The PWM counter operates in two modes to allow edge-aligned outputs and center-
aligned outputs. Figures 8 and 9 illustrate edge- and center-aligned PWM outputs. The
period of the PWM outputs, PERIOD, is determined by which mode the PWM counter is
operating. The active time of a PWM output is determined by the programmed duty cycle,
PWMDC, and the programmed deadband time, PWMDB.

The sections that follow these two figures describe the PWM timer modes and the regis-
ters that control the duty cycle and deadband time.

Figure 8. Edge-Aligned PWM Output

Period

PWMDB

PWMDC

PWMDB

PWMxH

No Deadband

PWMxH

Deadband Insertion

PWMxL

Pulse-Width Modulator

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Product Specification

PWM Duty Cycle Registers

The PWM Duty Cycle registers (PWM0HD, PWM0LD, PWM1HD, PWM1LD,
PWM2HD, PWM2LD) contain a 16-bit signed value, in which bit 15 is the sign bit. The
Duty Cycle value is compared to the current 12-bit unsigned PWM count value. If the
PWM Duty Cycle value is set less than or equal to 0, the PWM output is deasserted for the
full PWM period. If the PWM Duty Cycle value is set to a value greater than the PWM
reload value, the PWM output is asserted for the full PWM period.

Independent and Complementary PWM Outputs

The six PWM outputs are configurable to operate independently, or as three complemen-
tary pairs. Operation as six independent PWM channels is enabled by setting the

INDEN

bit in the PWM Control 1 Register (PWMCTL1). The

PWEN

bit must be cleared to alter

this bit. In independent mode, each PWM output uses its own PWM duty cycle value.

When configured to operate as three complementary pairs, the PWM duty cycle values
PWM0HD, PWM1HD, and PWM2HD control the modulator output. In complementary
output mode, deadband time is also inserted.

The POLx bits in the PWM Control 1 Register (PWMCTL1) select the relative polarity of
the High and Low signals. As illustrated in

Figures 8 and 9

, when the POLx bits are

cleared to 0, the High PWM output will start in the ON state and transition to the OFF
state when the PWM timer count reaches the programmed duty cycle. The Low PWM
value starts in the OFF state and transitions to the ON state as the PWM timer count
reaches the value in the associated duty cycle register. Alternately, setting the POLx
causes the High output to start in the OFF state and the Low output to start in the ON state.

Manual Off-State Control of PWM Output Channels

Each PWM output can be controlled directly by the modulator logic or set to the OFF
state. To manually set the PWM outputs to the OFF state, set the

OUTCTL

bit and the asso-

ciated

OUTx

bits in the PWM Output Control Register (PWMOUT). OFF state control

operates individually by channel. For example, suppressing the single output of a pair
allows the complementary channel to continue operating. Similarly, if the outputs are
operating independently, disabling one output channel has no effect on the other PWM
outputs.

Deadband Insertion

When the PWM outputs are configured to operate as complementary pairs, an 8-bit dead-
band value can be defined in the PWM Deadband Register (PWMDB). Inserting deadband
time causes the modulator to separate the deassertion of one PWM signal from the asser-
tion of its complement. This separation is essential for many motor control applications in
that it prevents simultaneous turn-on of the High and Low drive transistors. The deadband

PS024604-1005

P R E L I M I N A R Y

Minimum PWM Pulse Width Filter

Z8FMC16100 Series Flash MCU

Product Specification

counter directly counts system clock cycles and is unaffected by PWM prescaler settings.
The width of this deadband is attributed to the number of system clock cycles specified in
the PWM Deadband Register (PWMDB). The minimum deadband duration is one system
clock, and the maximum duration is 255 system clocks. During the deadband period, both
PWM outputs of a complementary pair are deasserted. The generation of deadband time
does not alter the PWM period; instead, the deadband time is subtracted from the active
time of the PWM outputs.

Figures 8 and 9

show the effect of deadband insertion on the

PWM output.

Minimum PWM Pulse Width Filter

The PWM modulator is capable of producing pulses as narrow as a single system clock
cycle in width. Because the response time of external drive circuits may be slower than the
period of a system clock, a filter is implemented to enforce a minimum-width pulse on the
PWM output pins. All output pulses, whether High or Low, must be at least the minimum
number of PWM clock cycles (see the

PWM Prescaler

section on page 70 for more infor-

mation) in width as specified in the PWM Minimum Pulse Width Filter (PWMMPF) Reg-
ister. If the expected pulse width is less than the threshold, the associated PWM output
does not change state until the duty cycle value has changed sufficiently to allow pulse
generation of an acceptable width. The minimum pulse width filter also accounts for the
duty cycle variation caused by the deadband insertion. The PWM output pulse is filtered
even if the programmed duty cycle is greater than the threshold, but the pulse width
decrease because of deadband insertion causes the pulse to be too narrow. The pulse width
filter value is calculated as:

where

MINPULSEOUT

is the shortest allowed pulse width on the PWM outputs, in seconds.

The PWM Minimum Pulse Width Filter Register can only be written when the

PWEN

bit is

cleared. Values written to this register when

PWEN

is set will be ignored.

Synchronization of PWM and Analog-to-Digital Converter

The analog-to-digital converter (ADC) on the Z8FMC16100 Series Flash MCU can be
synchronized with the PWM period. Enabling the PWM ADC trigger causes the PWM to
generate an ADC conversion signal at the end of each PWM period. Additionally, in cen-
ter-aligned mode, the PWM will generate a trigger at the center of the period. Setting the
ADCTRIG bit in the PWM Control 0 Register (PWMCTL0) enables ADC synchroniza-
tion.

roundup(PWMMPF) =

MINPULSEOUT

SYSTEMCLOCK

x PWM

PRESCALER

Pulse-Width Modulator

P R E L I M I N A R Y

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Product Specification

PWM Timer and Fault Interrupts

The PWM generates interrupts to the eZ8 CPU upon any of the following events:

PWM Reload.

The interrupt is generated at the end of a PWM period when a PWM regis-

ter reload occurs (the

READY

bit is set).

PWM Fault.

A fault condition is indicated by asserting any of the FAULT pins, or by the

assertion of the comparator.

Fault Detection and Protection

The Z8FMC16100 Series Flash MCU contains hardware and software fault controls that
allow rapid deassertion of all enabled PWM output signals. A logic Low on an external
fault pin (FAULT0 or FAULT1), or the assertion of the overcurrent comparator, forces the
PWM outputs to a predefined OFF state.

Similar deassertion of the PWM outputs can be accomplished in software by writing to the

PWMOFF

bit in the PWM Control 0 Register. The PWM counter continues to operate while

the outputs are deasserted (made inactive) due to one of these fault conditions.

The fault inputs can be individually enabled through the PWM Fault Control Register. If a
fault condition is detected and the source is enabled, a fault interrupt is generated. The
PWM Fault Status Register (PWMFSTAT) is read to determine which fault source has
caused the interrupt.

After a fault has been detected, and after the PWM outputs are disabled, modulator control
of the PWM outputs can be reenabled either by software, or by deassertion of the FAULT
input signal. Selection of either method is made via the PWM Fault Control Register
(PWMFCTL). Configuration of the fault modes and reenable methods allows pulse-by-
pulse limiting and hard shutdown. When configured in automatic restart mode, the PWM
outputs are reengaged at beginning of the next PWM cycle (the master timer value is equal
to 0) if all fault signals are deasserted. In a software-controlled restart, all fault inputs must
be deasserted and all fault flags cleared.

The fault input pin is Schmitt-triggered. The input signal from the pin, as well as the com-
parators, pass though an analog filter to reject high-frequency noise.

The logic path from the fault sources to the PWM outputs is asynchronous, which ensures
that the fault inputs will force the PWM outputs to their OFF state, even if the system
clock is stopped.

PWM Operation in CPU Halt Mode

When the eZ8 CPU is operating in HALT mode, the Pulse-Width Modulator continues to
operate, if enabled. To minimize the current in HALT mode, the Pulse-Width Modulator
must be disabled by clearing the

PWMEN

bit to 0.

PS024604-1005

P R E L I M I N A R Y

PWM Operation in CPU Stop Mode

Z8FMC16100 Series Flash MCU

Product Specification

PWM Operation in CPU Stop Mode

When the eZ8 CPU is operating in STOP mode, the Pulse-Width Modulator is disabled,
because the system clock ceases to operate in STOP mode. The PWM outputs remain in
the same state as they were prior to entering STOP mode. In normal operation, the PWM
outputs must be disabled by the software prior to the CPU entering STOP mode. A fault
condition detected in STOP mode forces the PWM outputs to a predefined OFF state.

Observing the State of PWM Output Channels

The logic value of the PWM outputs can be sampled by reading the PWMIN register. If a
PWM channel pair is disabled (an option bit is not set), the associated PWM outputs are
forced to high-impedance, and can be used as general-purpose inputs.

PWM High and Low Byte Registers

The PWM High and Low Byte (PWMH and PWML) registers, shown in Tables 42 and
43, contain the current 12-bit PWM count value. Reads from PWMH cause the value in
PWML to be stored in a temporary holding register. A read from PWML always returns
this temporary register value.

Writing to the PWM High and Low Byte registers while the PWM is enabled is not rec-
ommended. There are no temporary holding registers for Write operations, so simulta-
neous 12-bit Writes are not possible.

If either the PWM High or Low Byte registers are written during counting, the 8-bit writ-
ten value is placed in the counter (High or Low byte) at the next clock edge. The counter
continues counting from the new value.

Table 42. PWM High Byte Register (PWMH)

BITS

FIELD

Reserved

PWMH

RESET

R/W

R/W

ADDR

F2CH

Caution:

Pulse-Width Modulator

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PWMH and PWML--PWM High and Low Bytes

These 2 bytes, {PWMH[3:0], PWML[7:0]}, contain the current 12-bit PWM count value.

PWM Reload High and Low Byte Registers

The PWM Reload High and Low Byte (PWMRH and PWMRL) registers, shown in Table
44 and Table 45, store a 12-bit reload value, {PWMRH[3:0], PWMRL[7:0]}. The PWM
reload value is held in buffer registers. The PWM reload value written to the buffer regis-
ters is not used by the PWM generator until the next PWM reload event occurs. Reads
from these registers always return the values from the buffer registers.

Table 43. PWM Low Byte Register (PWML)

BITS

FIELD

PWML

RESET

00H

R/W

R/W

ADDR

F2DH

Edge-Aligned PWM Mode Period =

Prescaler x Reload Value

PWMCLK

Center-Aligned PWM Mode Period =

2 x Prescaler x Reload Value

PWMCLK

Table 44. PWM Reload High Byte Register (PWMRH)

BITS

FIELD

Reserved

PWMRH

RESET

R/W

R/W

ADDR

F2EH

PS024604-1005

P R E L I M I N A R Y

PWM 0�2 Duty Cycle High and Low Byte

Z8FMC16100 Series Flash MCU

Product Specification

PWMRH and PWMRL--PWM Reload Register High and Low

These two bytes form the 12-bit Reload value, {PWMRH[3:0], PWMRL[7:0]}. This value
sets the PWM period.

PWM 0�2 Duty Cycle High and Low Byte Registers

The PWM 0�2 H/L Duty Cycle High and Low Byte (PWMxDH and PWMxDL) registers,
shown in Table 46 and Table 47, set the duty cycle of the PWM signal. This 14-bit signed
value is compared to the PWM count value to determine the PWM output. Reads from
these registers always return the values from the temporary holding registers. The PWM
duty cycle value is not used by the PWM generator until the next PWM reload event
occurs.

Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM
period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM
to be ON for the full PWM period.

Table 45. PWM Reload Low Byte Register (PWMRL)

BITS

FIELD

PWMRL

RESET

R/W

R/W

ADDR

F2FH

PWM Duty Cycle =

PWM Duty Cycle Value

PWM Reload Value

Table 46. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)

BITS

FIELD

SIGN

Reserved

DUTYH

RESET

0_0000

R/W

R/W

ADDR

F30H, F32H, F34H, F36H, F38H, F3AH

Pulse-Width Modulator

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PWM Control 0 Register

The PWM Control 0 (PWMCTL0) Register, shown in Table 48, controls PWM operation.

Table 47. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)

BITS

FIELD

DUTYL

RESET

00H

R/W

R/W

ADDR

F31H, F33H, F35H, F37H, F39H, F3BH

Bit

Position

Value

(H)

Description

[7]

SIGN

Duty Cycle Sign
Duty Cycle is a positive two's complement number.

Duty Cycle is a negative two's complement number. Output is forced to the off-
state.

[6:0], [7:0]

DUTYH and
DUTYL

PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.

Table 48. PWM Control 0 Register (PWMCTL0)

BITS

FIELD

PWMOFF

OUTCTL

ALIGN

Reserved ADCTRIG Reserved

READY

PWMEN

RESET

R/W

R/W

ADDR

F20H

PS024604-1005

P R E L I M I N A R Y

PWM Control 0 Register

Z8FMC16100 Series Flash MCU

Product Specification

Bit

Position

Value

(H)

Description

[7]

PWMOFF

Place PWM outputs in off-state

Disable modulator control of PWM pins. Outputs are in predefined off-state. This
is not dependent on the reload event.

Re-enable modulator control of PWM pins at next PWM reload event.

[6]

OUTCTL

PWM Output Control

PWM outputs are controlled by the Pulse-Width Modulator.

PWM outputs selectively disabled (set to off-state) according to values in the
OUTx bits of the PWMOUT register.

[5]

ALIGN

PWM Edge Alignment

PWM outputs are edge aligned.

PWM outputs are center aligned.

[4]

Reserved

[3]

ADCTRIG

ADC Trigger Enable

No ADC trigger pulses.

ADC trigger enabled.

[2]

Reserved

[1]

READY

Values Ready for Next Reload Event

PWM values (pre-scale, period, and duty cycle) are not ready. Do not use

values in holding registers at next PWM reload event

PWM values (pre-scale, period, and duty cycle) are ready. Transfer all values
from temporary holding registers to working registers at next PWM reload event.

[0]

PWMEN

PWM Enable

Pulse-width modulator is disabled and enabled PWM output pins are forced to
default off-state. PWM master counter is stopped. Certain control registers may
only written in this state.

Pulse-width modulator is enabled and PWM output pins are enabled as outputs.

Pulse-Width Modulator

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PWM Control 1 Register

The PWM Control 1 (PWMCTL1) Register, shown in Table 49, controls portions of PWM
operation.

Table 49. PWM Control 1 Register (PWMCTL1)

BITS

FIELD

RLFREQ[1:0]

INDEN

Pol45

Pol23

Pol10

PRES[1:0]

RESET

R/W

R/W

ADDR

F21H

Bit

Position

Value

(H)

Description

[7:6]

RLFREQ[1:0]

Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.

PWM reload event occurs at the end of every PWM period.

PWM reload event occurs once every 2 PWM periods.

PWM reload event occurs once every 4 PWM periods.

PWM reload event occurs once every 8 PWM periods.

[5]

INDEN

Independent PWM Mode Enable
This bit may only be altered when PWEN (PWMCTL0) cleared.

PWM outputs operate as 3 complementary pairs.

PWM outputs operate as 6 independent channels.

[4]

Pol2

Invert Ouput polarity for channel pair PWM2.

Non-inverted polarity for channel pair PWM2.

[3]

Pol1

Invert Ouput polarity for channel pair PWM1.

Non-inverted polarity for channel pair PWM1.

[2]

Pol0

Invert Ouput polarity for channel pair PWM0.

Non-inverted polarity for channel pair PWM0.

PS024604-1005

P R E L I M I N A R Y PWM

Deadband

Z8FMC16100 Series Flash MCU

Product Specification

PWM Deadband Register

The PWM Deadband (PWMDB) Register, shown in Table 50, stores the 8-bit PWM dead-
band value. This register determines the number of system clock cycles inserted as dead-
time in complementary output mode. The minimum deadband value is 1.

[1:0]

PRES

PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or the
PWMIN external input). This field is buffered. Changes to this field take effect at
the next PWM reload event. Reads always return the values from the
temporary holding register.

Divide by 1

Divide by 2

Divide by 4

Divide by 8

Table 50. PWM Dead-Band Register (PWMDB)

BITS

FIELD

PWMDB[7:0]

RESET

01H

R/W

R/W

ADDR

F22H

Bit

Position

Value

(H)

Description

[7:0]

PWMDB

PWM Dead band
Sets the PWM dead band period for which both PWM outputs of a
complementary PWM output pair are deasserted.

Note: This register can only be written when PWEN is cleared.

Bit

Position

Value

(H)

Description

Pulse-Width Modulator

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PWM Minimum Pulse Width Filter

The value in the PWM Minimum Pulse Width Filter (PWMMPF) Register, shown in Table
51, determines the minimum width pulse, either high or low, that can be generated by the
PWM module. The minimum pulse width period is calculated as:

A Value other than 00H must be written to the PWMMPF registor or the PWM output
waveform will be distorted!

PWM Fault Mask Register

The PWM Fault Mask (PWMFM) Register, shown in Table 52, enables individual fault
sources. PWM behaviour when an input is asserted is determined by the PWM Fault Con-
trol Register (PWMFCTL).

MINPULSEOUT

PWMDB + PWMMPF

SYSTEMCLOCK

x PWMPrescale

Table 51. PWM Minimum Pulse Width Filter (PWMMPF)

BITS

FIELD

PWMMPF[7:0]

RESET

00H

R/W

R/W

ADDR

F23H

Bit

Position

Value

(H)

Description

[7:0]

PWMMPF

PWM Minimum Pulse Filter

Sets the minimum allowed output pulse width in PWM clock cycles.

Note: This register can only be written when PWEN is cleared.

Table 52. PWM Fault Mask Register (PWMFM)

BITS

FIELD

Reserved

DBGMSK

Reserved

F1MASK

C0MASK

FMASK

RESET

000

R/W

R/W

ADDR

F24H

Caution:

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P R E L I M I N A R Y

PWM Fault Status Register

Z8FMC16100 Series Flash MCU

Product Specification

PWM Fault Status Register

The PWM Fault Status (PWMFSTA) Register, shown in Table 53, provides status of fault
inputs and timer reload.. The fault flags indicate which fault source is active. If a fault
source is masked the flag in this register will not be set if the source is asserted. The
reload flag is set when the timer compare vaules are updated. Clear flags by writing a 1 to
the flag bits. Fault flag bits can only be cleared if the associated fault source has deas-
serted.

Bit

Position

Value

(H)

Description

[7:6]

Reserved

Must be 0.

[5]
DBGMSK

Debug Entry Fault Mask

Entering CPU DEBUG Mode generates a PWM fault.

Entering CPU DEBUG mode does not generate a PWM fault.

[4:3]

Reserved

Must be 0.

[2]

F1MASK

Fault 1 Fault Mask

Fault 1 generates a PWM fault.

Fault 1 does not generate a PWM fault.

[1]

C0MASK

Comparator Fault Mask

Comparator generates a PWM fault.

Comparator does not generate a PWM fault.

[0]

F0MASK

Fault Pin Mask

Fault0 pin generates a PWM fault.

Fault0 pin does not generate a PWM fault.

Note: This register can only be written when PWEN is cleared.

Pulse-Width Modulator

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Table 53. PWM Fault Status Register (PWMFSTAT)

BITS

FIELD

RLDFlag Reserved

DBGFLAG

Reserved

F1FLAG

C0FLAG

FFLAG

RESET

R/W

R/W1C

ADDR

F25H

Bit

Position

Value

(H)

Description

[7]

RLDFlag

Reload Flag

This bit is set and latched when a PWM timer reload occurs. Writing a 1 to this bit
clears the flag.

[6]

Reserved

Always reads 0.

[5]
DBGFLAG

Debug Flag

This bit is set and latched when DEBUG mode is entered. Writing a 1 to this bit
clears the flag.

[4:3]

Reserved

Always reads 0.

[2]

F1FLAG

Fault1

Flag

This bit is set and latched when Fault1 is asserted. Writing a 1 to this bit clears
the flag.

[1]

C0FLAG

Comparator 0 Flag

This bit is set and latched when Comparator is asserted. Writing a 1 to this bit
clears the flag.

[0]

FFLAG

Fault

Flag

This bit is set and latched when the FAULT0 input is asserted. Writing a 1 to this
bit clears the flag.

Note: For this register, W1C means you must write one to clear the flag.

PS024604-1005

P R E L I M I N A R Y

PWM Fault Control Register

Z8FMC16100 Series Flash MCU

Product Specification

PWM Fault Control Register

The PWM Fault Control (PWMFCTL) Register, shown in Table 54, determines how the
PWM recovers from a fault condition. Settings in this register select automatic or software
controlled PWM restart.

Table 54. PWM Fault Control Register (PWMFCTL)

BITS

FIELD

Reserved DBGRST Fault1INT Fault1RST CMPINT

CMPRST Fault0INT Fault0RST

RESET

R/W

R/W

ADDR

F28H

Bit

Position

Value

(H)

Description

[7]
Reserved

Reserved.

[6]
DBGRST

DebugRestart

Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered and a new PWM period begins.

oftware controlled recovery. PWM resumes control of outputs only after all fault

sources have deasserted and all fault flags are cleared and a PWM reload occurs

[5]
Fault1INT

Fault 1 Interrupt

Interrupt on comparator assertion disabled.

Interrupt on comparator assertion enabled.

[4]
Fault1RST

Fault 1 Restart

Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered.

oftware controlled recovery. PWM resumes control of outputs only after all fault

sources have deasserted and all fault flags are cleared and a PWM reload occurs

[3
CMP0INT

Comparator 0 Interrupt

Interrupt on comparator 0 assertion disabled.

Interrupt on comparator 0 assertion enabled.

[2]
CMP0RST

Comparator 0 Restart

Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered.

oftware controlled recovery. PWM resumes control of outputs only after all fault

sources have deasserted and all fault flags are cleared and a PWM reload occurs

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PWM Input Sample Register

PWM pin values are sampled by reading the PWM Input Sample Register, shown in Table
55.

[1]
Fault0INT

Fault 0 Interrupt

Interrupt on Fault0 pin assertion disabled.

Interrupt on Fault0 pin assertion enabled.

[0]
Fault0RST

Fault 0 Restart

Automatic recovery. PWM resumes control of outputs when all fault sources have
deasstered.

oftware controlled recovery. PWM resumes control of outputs only after all fault

sources have deasserted and all fault flags are cleared and a PWM reload occurs

Note: This register can only be written when PWEN is cleared.

Table 55. PWM Input Sample Register (PWMIN)

BITS

FIELD

Reserved

FAULT

IN2L

IN2H

IN1L

IN1H

IN0L

IN0H

RESET

R/W

R/W

ADDR

F26H

Bit

Position

Value

(H)

Description

[7]

Reserved

Must be 0.

[6]

FAULT

Sample Fault0 pin

A Low level signal was read on the FAULT pin.

A High level signal was read on the FAULT pin.

[5:0]

IN2L/IN2H/

IN1L/IN1H/

IN0L/IN0H

Sample PWM pins
A Low level signal was read on the pins.

A High level signal was read on the pins.

Bit

Position

Value

(H)

Description

PS024604-1005

P R E L I M I N A R Y

PWM Output Control Register

Z8FMC16100 Series Flash MCU

Product Specification

PWM Output Control Register

The PWM Output Control (PWMOUT) Register, shown in Table 56, enables modulator
control of the six PWM output signals. Output control is enabled by the OUTCTL bit in
the PWMCTL0 register. The Pulse-Width Modulator continues to operate, but has no
effect on the disabled PWM pins. If a fault condition is detected all PWM outputs are
forced to their selected OFF state.

Current Sense ADC Trigger Control Register

An ADC trigger is generated when the PWM output signals match the state specified by
the Current-Sense ADC-Trigger control register. The match logic is an AND-OR tree that
will solve to true if based on the register settings. An ADC conversion will be triggered on
the rising edge of this signal. The logic equation for the adc-trigger is:

ADCTRIGGER = CSTPOL ^ (

( HEN & PWM0H &PWM1H & PWM2H) |

( LEN & PWM0L &PWM1L & PWM2L) |

( nHEN & !PWM0H &!PWM1H & !PWM2H) |

( nLEN & !PWM0H & !PWM1H & !PWM2H) )

Table 56. PWM Output Control Register (PWMOUT)

BITS

FIELD

Reserved Reserved

OUT2L

OUT2H

OUT1L

OUT1H

OUT0L

OUT0H

RESET

R/W

R/W

ADDR

F27H

Bit

Position

Value

(H)

Description

[7,6]

Reserved

Must be 0.

[5, 3, 1]

OUT2L/

OUT1L/

OUT0L

PWM 2L/1L/0L Output Configuration

PWM 2L/1L/0L output signal is enabled and controlled by PWM.

PWM

2L/1L/0L

output signal is in low-side off-state.

[4, 2, 0]

OUT2H/

OUT1H/

OUT0H

PWM 2H/1H/0H Output Configuration

PWM 2H/1H/0H output signal is enabled and controlled by PWM.

PWM 2H/1H/0H output signal is in high-side off-state.

Pulse-Width Modulator

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where

�

the ^ symbol indicates a logical exclusive OR (XOR) function

�

the & symbol indicates a logical AND function

�

the | symbol indicates a logical OR function

�

the ! symbol indicates a logical NOT function

The combinations of polarity, enable, and PWM signals allow the logic to generate a
ADC-trigger under a wide variety of operating conditions. The HEN, LEN, nHEN, and
nLEN bits enable a group in the or logic. The CSTWMx bits allow the level of the PWM
output signals to control the equation. If a CSTPWMx bit is cleared, the value of the asso-
ciated PWMx output will always evaluate to a TRUE condition in the equation. Note that
these bits DO NOT affect the actual PWM outputs.

Table 57. Current-Sense Trigger Control Register (PWMSHC)

BITS

FIELD

CSTPOL

HEN

NHEN

LEN

NLEN

CSTPWM2 CSTPWM1 CSTPWM0

RESET

R/W

R/W

ADDR

F29H

Bit

Position

Value

(H)

Description

[7]

CSTPOL

Sample Hold Polarity
Hold when terms are active

Hold when terms are not active

[6]

HEN

High Side Active enable

Ignore Product of PWM0H, PWM1H, PWM2H in Sample/Hold equation

Hold when PWM0H, PWM1H, PWM2H are all active

[5]

NHEN

High Side inactive enable

Ignore Product of

PWM0H

PWM1H

PWM2H

in Sample/Hold equation

Hold when are all active

[4]

LEN

Low Side Active enable

Ignore Product of PWM0L, PWM1L, PWM2L in Sample/Hold equation

Hold when PWM0L, PWM1L, PWM2L are all active

General-Purpose Timer

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Operation

The general-purpose timer is a 16-bit up-counter. In normal operation, the timer is initial-
ized to

0001h

. After it is enabled, the timer counts up to the value contained in the Reload

High and Low Byte registers, then resets to

0001h

. The counter either halts or continues,

depending on its current mode of operation.

Minimum time-out delay (1 system clock in duration) is set by loading the value

0001h

into the Timer Reload High and Low Byte registers and setting the prescale value to 1.

Maximum time-out delay (2

x 2

system clocks) is set by loading the value

0000h

into

the Timer Reload High and Low Byte registers and setting the prescale value to 128.
When the timer reaches

FFFFh

, the timer rolls over to

0000h

If the reload register is set to a value less than the current counter value, the counter con-
tinues counting until reaching

FFFFh

, rolls over to

0000h

, and continues counting until

reaching the reload value, then resets to

0001h

Figure 10. Timer Block Diagram

Data

Bus

Block

Control

System

Clock

Timer

Input

Gate Input

Capture Input

Timer

Interrupt

Interrupt,

PWM, and

Timer Output

Control

Timer Control

16-Bit

Reload Register

16-Bit Counter

with Prescaler

16-Bit

PWM/Compare

OUT

Timer Block

Compare

PS024604-1005

P R E L I M I N A R Y Timer

Operating

Modes

Z8FMC16100 Series Flash MCU

Product Specification

Timer Operating Modes

The timers can be configured to operate in the following eleven modes, each of which is
described in this section:

�

ONE-SHOT mode

�

TRIGGERED ONE-SHOT mode

�

CONTINUOUS mode

�

COUNTER mode

�

COMPARATOR COUNTER mode

�

PWM SINGLE OUTPUT mode

�

PWM DUAL OUTPUT mode

�

CAPTURE RESTART mode

�

CAPTURE COMPARE mode

�

COMPARE mode

�

GATED mode

One-Shot Mode

In ONE-SHOT mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The Timer Input is the system clock. After reaching
this reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to

0001h

. The timer is automatically disabled and stops

counting.

If the Timer Output alternate function is enabled, the Timer Output pin changes state for
one system clock cycle (from Low to High, then back to Low if

TPOL

= 0) at timer reload.

If the user chooses, the Timer Output can undergo a permanent state change upon One-
Shot time-out, as follows:

1. Set the

TPOL

bit in the Timer Control 1 Register to the start value before beginning

ONE-SHOT mode.

2. After starting the timer, set

TPOL

to the opposite value.

The steps for configuring a timer for ONE-SHOT mode and initiating a count are as fol-
lows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for ONE-SHOT mode.
c. Set the prescale value.

General-Purpose Timer

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d. If using the Timer Output alternate function, set the initial output level (High or

Low) using the

TPOL

bit.

e. Set the interrupt mode.

2. Write to the Timer High and Low Byte registers to set the starting count value.

3. Write to the Timer Reload High and Low Byte registers to set the reload value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

6. Write to the Timer Control 1 Register to enable the timer and initiate counting.

The timer period is calculated by the following equation (Start Value is typically = 1):

Triggered One-Shot Mode

In TRIGGERED ONE-SHOT mode, the timer operates as follows:

1. The Timer idles until a trigger is received. The timer trigger is taken from the Timer

Input pin. The

TPOL

bit in the Timer Control 1 Register selects whether the trigger

occurs on the rising edge or the falling edge of the Timer Input signal.

2. Following the trigger event, the timer counts system clocks up to the 16-bit reload

value stored in the Timer Reload High and Low Byte registers.

3. Upon reaching the reload value, the timer outputs a pulse on the Timer Output pin,

generates an interrupt, and resets the count value in the Timer High and Low Byte reg-
isters to

0001h

. The duration of the output pulse is a single system clock. The

TPOL

bit also sets the polarity of the output pulse.

4. The timer idles until the next trigger event. Trigger events that occur while the timer is

responding to a previous trigger are ignored.

The steps for configuring Timer 0 in TRIGGERED ONE-SHOT mode and initiating oper-
ation are as follows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for TRIGGERED ONE-SHOT mode.

One-Shot Mode Time-Out Period(s) =

(Reload Value � Start Value + 1) x Prescaler

System Clock Frequency (Hz)

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c. Set the prescale value.
d. If using the Timer Output alternate function, set the initial output level (High or

Low) via the

TPOL

bit.

e. Set the INTERRUPT mode.

2. Write to the Timer High and Low Byte registers to set the starting count value.

3. Write to the Timer Reload High and Low Byte registers to set the reload value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

6. Write to the Timer Control 1 Register to enable the timer. Counting does not start until

the appropriate input transition occurs.

The timer period is calculated by the following equation (Start Value is typically = 1):

The one-shot delay from input trigger to output includes the above-defined time-out
period, plus an additional delay of 2�3 system clock cycles, due to the synchronization of
the input trigger.

Continuous Mode

In CONTINUOUS mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. After reaching the reload value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to

0001h

and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer
Output pin changes state (from Low to High or from High to Low) after timer reload.

The steps for configuring a timer for CONTINUOUS mode and initiating the count are as
follows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for CONTINUOUS mode.
c. Set the prescale value.

Triggered One-Shot Mode Time-Out Period(s) =

(Reload Value � Start Value + 1) x Prescaler

System Clock Frequency (Hz)

Note:

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d. If using the Timer Output alternate function, set the initial output level (High or

Low) via

TPOL

2. Write to the Timer High and Low Byte registers to set the starting count value (usually

0001h

). This setting only affects the first pass in CONTINUOUS mode. After the first

timer reload in CONTINUOUS mode, counting begins at the reset value of

0001h

3. Write to the Timer Reload High and Low Byte registers to set the reload period.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

6. Write to the Timer Control 1 Register to enable the timer and initiate counting.

The timer period is calculated by the following equation:

If an initial starting value other than

0001h

is loaded into the Timer High and Low Byte

registers, use the ONE-SHOT mode equation to determine the first time-out period.

Counter and Comparator Counter Modes

In COUNTER mode, the timer counts input transitions from a GPIO port pin. The Timer
Input is taken from the associated GPIO port pin. The

TPOL

bit in the Timer Control 1

Register selects whether the count occurs on the rising edge or the falling edge of the
Timer Input signal. In COUNTER mode, the prescaler is disabled.

The input frequency of the Timer Input signal must not exceed one-fourth the system
clock frequency.

In COMPARATOR COUNTER mode, the timer counts output transitions from an analog
comparator output. Timer 0 takes its input from the output of the comparator. The

TPOL

bit

in the Timer Control 1 Register selects whether the count occurs on the rising edge or the
falling edge of the comparator output signal. In COMPARATOR COUNTER mode, the
prescaler is disabled.

The frequency of the comparator output signal must not exceed one-fourth the system
clock frequency.

Continuous Mode Time-Out Period(s) =

Reload Value x Prescaler

System Clock Frequency (Hz)

Caution:

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After reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to

0001h

, and counting resumes.

If the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reload.

The steps for configuring a timer for COUNTER and COMPARATOR COUNTER modes
and initiating the count are as follows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for COUNTER or COMPARATOR COUNTER mode.
c. Select either the rising edge or falling edge of the Timer Input or comparator out-

put signal for the count. This choice also sets the initial logic level (High or Low)
for the Timer Output alternate function. However, the Timer Output function does
not have to be enabled.

2. Write to the Timer High and Low Byte registers to set the starting count value. This

setting only affects the first pass in the counter modes. After the first timer reload,
counting begins at the reset value of

0001h

3. Write to the Timer Reload High and Low Byte registers to set the reload value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. Configure the associated GPIO port pin for the Timer Input alternate function

(COUNTER mode).

6. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

7. Write to the Timer Control 1 Register to enable the timer.

PWM Single and Dual Output Modes

In PWM SINGLE OUTPUT mode, the timer outputs a Pulse-Width Modulator (PWM)
output signal through a GPIO port pin. In PWM DUAL OUTPUT mode, the timer outputs
a Pulse-Width Modulator (PWM) output signal and also its complement through two
GPIO port pins. The timer first counts up to the 16-bit PWM match value stored in the
Timer PWM High and Low Byte registers. When the timer count value matches the PWM
value, the Timer Output toggles. The timer continues counting until it reaches the reload
value stored in the Timer Reload High and Low Byte registers. Upon reaching the reload
value, the timer generates an interrupt, the count value in the Timer High and Low Byte
registers is reset to

0001h

, and counting resumes.

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The Timer Output signal begins with a value equal to

TPOL

and then transitions to

TPOL

when the timer value matches the PWM value. The Timer Output signal returns to

TPOL

after the timer reaches the reload value, and is reset to

0001h

In PWM DUAL OUTPUT mode, the timer also generates a second PWM output signal,
Timer Output Complement (T

OUT

). A programmable deadband can be configured (

PWMD

field) to delay (0�128 system clock cycles) the Low to a High (inactive to active) output
transitions on these two pins. This configuration ensures a time gap between the deasser-
tion of one PWM output to the assertion of its complement.

The steps for configuring a timer for either PWM SINGLE or DUAL OUTPUT mode and
initiating PWM operation are as follows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for the selected PWM mode.
c. Set the prescale value.
d. Set the initial logic level (High or Low) and PWM High/Low transition for the

Timer Output alternate function with the

TPOL

bit.

e. Set the deadband delay (DUAL OUTPUT mode) with the

PWMD

field.

2. Write to the Timer High and Low Byte registers to set the starting count value (typi-

cally

0001h

). The starting count value only affects the first pass in PWM mode. After

the first timer reset in PWM mode, counting begins at the reset value of

0001h

3. Write to the PWM High and Low Byte registers to set the PWM value.

4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM

period). The reload value must be greater than the PWM value.

5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

6. Configure the associated GPIO port pin(s) for the Timer Output alternate function.

7. Write to the Timer Control 1 Register to enable the timer and initiate counting.

The PWM period is determined by the following equation:

If an initial starting value other than

0001h

is loaded into the Timer High and Low Byte

registers, use the ONE-SHOT mode equation to determine the first PWM time-out period.

PWM Period(s) =

Reload Value x Prescaler

System Clock Frequency (Hz)

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TPOL

is set to 0, the ratio of the PWM output High time to the total period is determined

by the equation:

TPOL

is set to 1, the ratio of the PWM output High time to the total period is determined

by the equation:

Capture Modes

There are three capture modes that provide slightly different methods for recording the
time of, or time interval between, Timer Input events. These modes are CAPTURE mode,
CAPTURE RESTART mode, and CAPTURE COMPARE mode. In all three modes, when
the appropriate Timer Input transition (capture event) occurs, the timer counter value is
captured and stored in the PWM High and Low Byte registers. The

TPOL

bit in the Timer

Control 1 Register determines whether the Capture occurs on a rising edge or a falling
edge of the Timer Input signal. The

TICONFIG

bit determines whether interrupts are gen-

erated on capture events, reload events, or both. The

INCAP

bit in Timer Control 0 Regis-

ter clears to indicate an interrupt caused by a reload event and sets to indicate the timer
interrupt is caused by an input capture event.

There is a delay from the input event to the timer capture of 2�3 system clock cycles, due
to internal synchronization logic.

If the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reload. The initial value is determined
by the

TPOL

bit.

Capture Mode.

In CAPTURE mode, and after it is enabled, the timer counts continuously

and rolls over from

FFFFh

0000h

. When the capture event occurs, the timer counter

value is captured and stored in the PWM High and Low Byte registers, an interrupt is gen-
erated, and the timer continues counting. The timer continues counting up to the 16-bit
reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the
reload value, the timer generates an interrupt and continues counting.

Capture Restart Mode.

In CAPTURE RESTART mode, after it is enabled, the timer

counts continuously until either the capture event occurs or the timer count reaches the 16-
bit compare value stored in the Timer Reload High and Low Byte registers. If the capture
event occurs first, the timer counter value is captured and stored in the PWM High and
Low Byte registers, an interrupt is generated, the count value in the Timer High and Low
Byte registers is reset to

0001h

, and counting resumes. If no capture event occurs, upon

PWM Output High Time Ratio (%) =

Reload Value � PWM Value

x 100

Reload Value

PWM Output High Time Ratio (%) =

PWM Value

x 100

Reload Value

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100

reaching the reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to

0001h

, and counting resumes.

Capture/Compare Mode.

CAPTURE/COMPARE mode is identical to CAPTURE

RESTART mode, except that counting does not start until the first external Timer Input
transition occurs. Every subsequent transition (after the first) of the Timer Input signal
captures the current count value. When the capture event occurs, an interrupt is generated,
the count value in the Timer High and Low Byte registers is reset to

0001h

, and counting

resumes. If no capture event occurs, upon reaching the compare value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to

0001h

and counting resumes.

The steps for configuring a timer for one of these capture modes and initiating the count
are as follows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for the selected capture mode.
c. Set the prescale value.
d. Set the capture edge (rising or falling) for the Timer Input.
e. Configure the timer interrupt to be generated at the input capture event, the reload

event, or both, by setting the

TICONFIG

field.

2. Write to the Timer High and Low Byte registers to set the starting count value (typi-

cally

0001h

3. Write to the Timer Reload High and Low Byte registers to set the reload value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. Configure the associated GPIO port pin for the Timer Input alternate function.

6. Write to the Timer Control 1 Register to enable the timer. In CAPTURE and CAP-

TURE RESTART modes, the timer begins counting. In CAPTURE COMPARE
mode, the timer does not start counting until the first input transition occurs.

In capture modes, the elapsed time from a timer start to a capture event can be calculated
using the following equation (Start Value is typically = 1):

Capture Elapsed Time (s) =

(Capture Value � Start Value +1) x Prescale

System Clock Frequency (Hz)

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101

Compare Mode

In COMPARE mode, the timer counts up to the 16-bit compare value stored in the Timer
Reload High and Low Byte registers. After reaching the compare value, the timer gener-
ates an interrupt and counting continues (the timer value is not reset to

0001h

). If the

Timer Output alternate function is enabled, the Timer Output pin changes state (from Low
to High or from High to Low).

If the timer reaches

FFFFh

, the timer rolls over to

0000h

and continues counting.

The steps for configuring a timer for COMPARE mode and initiating the count are as fol-
lows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for COMPARE mode.
c. Set the prescale value.
d. Set the initial logic level (High or Low) for the Timer Output alternate function, if

appropriate.

2. Write to the Timer High and Low Byte registers to set the starting count value.

3. Write to the Timer Reload High and Low Byte registers to set the Compare value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

6. Write to the Timer Control 1 Register to enable the timer and initiate counting.

The compare time is calculated by the following equation (Start Value is typically = 1):

Gated Mode

In GATED mode, the timer counts only when the Timer Input signal is in its active state,
as determined by the

TPOL

bit in the Timer Control 1 Register. When the Timer Input sig-

nal is active, counting begins. A timer interrupt is generated when the Timer Input signal
transitions from active to inactive state, a timer reload occurs, or both, depending on

TICONFIG[1:0]

. To determine if a Timer Input signal deassertion generated the inter-

rupt, read the associated GPIO input value and compare it to the value stored in the

TPOL

bit.

Compare Mode Time (s) =

(Compare Value � Start Value +1) x Prescale

System Clock Frequency (Hz)

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The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. When reaching the reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to

0001h

, and counting continues

as long as the Timer Input signal is active. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer reload.

The steps for configuring a timer for GATED mode and initiating the count are as follows:

1. Write to the Timer Control registers to:

a. Disable the timer.
b. Configure the timer for GATED mode.
c. Set the prescale value.
d. Select the active state of the Timer Input via the

TPOL

bit.

2. Write to the Timer High and Low Byte registers to set the starting count value. This

setting only affects the first pass in GATED mode. After the first timer reset in
GATED mode, counting begins at the reset value of

0001h

3. Write to the Timer Reload High and Low Byte registers to set the reload value.

4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. Configure the timer interrupt to be generated only at the input deassertion event, the

reload event, or both, by setting the

TICONFIG

field of the Timer Control 0 Register.

6. Configure the associated GPIO port pin for the Timer Input alternate function.

7. Write to the Timer Control 1 Register to enable the timer.

8. The timer counts when the Timer Input is equal to the

TPOL

bit.

Reading the Timer Count Values

The current count value in the timers can be read while counting (enabled). This Read has
no effect on timer operation. When the timer is enabled and the Timer High Byte Register
is read, the contents of the Timer Low Byte Register are placed into a holding register. A
subsequent Read from the Timer Low Byte Register returns the value in the holding regis-
ter. This operation allows accurate Reads of the full 16-bit timer count value while
enabled. When the timer is not enabled, a Read from the Timer Low Byte Register returns
the actual value in the counter.

Timer 0 High and Low Byte Registers

The Timer 0 High and Low Byte (T0H and T0L) registers, shown in Tables 58 and 59,
contain the current 16-bit timer count value. When the timer is enabled, a Read from T0H

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Z8FMC16100 Series Flash MCU

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103

causes the value in T0L to be stored in a temporary holding register. A Read from T0L
always returns this temporary register when the timer is enabled. When the timer is dis-
abled, Reads from the T0L are direct from this temporary register.

Writing to the Timer High and Low Byte registers while the timer is enabled is not rec-
ommended. There are no temporary holding registers available for Write operations;
therefore, simultaneous 16-bit Writes are not possible.

If either the Timer High or Low Byte registers are written during counting, the 8-bit writ-
ten value is placed in the counter (High or Low Byte) at the next clock edge. The counter
continues counting from the new value.

TH and TL--Timer High and Low Bytes

These two bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.

Table 58. Timer 0 High Byte Register (T0H)

BITS

FIELD

RESET

00H

R/W

R/W

ADDR

F00H

Table 59. Timer 0 Low Byte Register (T0L)

BITS

FIELD

RESET

01H

R/W

R/W

ADDR

F01H

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104

Timer 0 Reload High and Low Byte Registers

The Timer 0 Reload High and Low Byte (T0RH and T0RL) registers, shown in Tables 60
and 61, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer
Reload High Byte Register are stored in a temporary holding register. When a Write to the
Timer Reload Low Byte Register occurs, the temporary holding register value is written to
the Timer High Byte Register. This operation allows simultaneous updates of the 16-bit
timer reload value.

TRH and TRL--Timer Reload Register High and Low

These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to

0001H

Table 60. Timer 0 Reload High Byte Register (T0RH)

BITS

FIELD

TRH

RESET

FFH

R/W

R/W

ADDR

F02H

Table 61. Timer 0 Reload Low Byte Register (T0RL)

BITS

FIELD

TRL

RESET

R/W

R/W

ADDR

F03H

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105

Timer 0 PWM High and Low Byte Registers

The Timer 0 PWM High and Low Byte (T0PWMH and T0PWML) registers, shown in
Tables 62 and 63, define Pulse-Width Modulator (PWM) operations. These registers also
store the timer counter values for the Capture modes.

The two bytes {PWMH[7:0], PWML[7:0]} form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control 1 Register (T0CTL1).

The T0PWMH and T0PWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.

PWMH and PWML--Pulse-Width Modulator High and Low Bytes

These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the

TPOL

bit in the Timer Control 1 register (T0CTL1).

The T0PWMH and T0PWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.

Table 62. Timer 0 PWM High Byte Register (T0PWMH)

BITS

FIELD

PWMH

RESET

00H

R/W

R/W

ADDR

F04H

Table 63. Timer 0 PWM Low Byte Register (T0PWML)

BITS

FIELD

PWML

RESET

00H

R/W

R/W

ADDR

F05H

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Timer 0 Control Registers

Two Timer 0 control registers determine timer configuration (T0CTL0) and operation
(T0CTL1).

Timer 0 Control 0 Register

The Timer 0 Control 0 (T0CTL0) Register together with the Timer 0 Control 1 (T0CTL1)
Register, determines the timer configuration and operation. See Table 64.

Table 64. Timer 0 Control 0 Register (T0CTL0)

BITS

FIELD

TMODE[3]

TICONFIG

TINSEL

PWMD

INCAP

RESET

000

R/W

R/W

ADDR

F06H

Bit

Position

Value

(H)

Description

[7]

TMODE[3]

Timer Mode High Bit
This bit along with the TMODE[2:0] field in the T0CTL1 register determines the
operating mode of the timer. This is the most significant bit of the Timer mode
selection value. See the T0CTL1 register description for additional details.

[6�5]

TICONFIG

Timer Interrupt Configuration--This field configures timer interrupt definitions.
These bits affect all modes. The effect per mode is explained below:

ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM,
TRIGGERED ONE-SHOT, COMPARATOR COUNTER:
0x Timer interrupt occurs on reload.
10 Timer interrupts are disabled.
11 Timer Interrupt occurs on reload.

GATED:
0x Timer interrupt occurs on reload or inactive gate edge.
10 Timer interrupt occurs on inactive gate edge.
11 Timer interrupt occurs on reload.

CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART:
0x Timer interrupt occurs on reload and capture.
10 Timer interrupt occurs on capture only.
11 Timer interrupt occurs on reload only

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107

Timer 0 Control 1 Register

The Timer 0 Control 1 (T0CTL1) Register, shown in Table 65, enables/disables the timer,
sets the prescaler value, and determines the timer operating mode.

[4]

TINSEL

Timer Input Select

Timer input is the Timer input pin.

Timer input is the comparator output.

[3�1]
PWMD

000

001

010

011

100

101

110

111

PWM Delay Value
This field is a programmable delay to control the number of additional system
clock cycles following a PWM or Reload compare before the Timer Output or the
Timer Output Complement is switched to the active state. This field ensures a
time gap between the deassertion of one PWM output to the assertion of its
complement.

No delay

2 cycles delay

4 cycles delay

8 cycles delay

16 cycles delay

32 cycles delay

64 cycles delay

128 cycles delay

[0]

INCAP

Input Capture Event
Previous timer interrupt is not a result of a Timer Input Capture Event

Previous timer interrupt is a result of a Timer Input Capture Event.

Table 65. Timer 0 Control 1 Register (T0CTL1)

BITS

FIELD

TEN

TPOL

PRES

TMODE

RESET

000

R/W

R/W

ADDR

F07H

Bit

Position

Value

(H)

Description

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108

Bit

Position

Value

(H)

Description

[7]

TEN

Timer Enable
Timer is disabled.

Timer enabled.

[6]

TPOL

Timer Input/Output Polarity
This bit is a function of the current operating mode of the timer. It determines the
polarity of the input and/or output signal. When the timer is disabled, the Timer
Output signal is set to the value of this bit.

ONE-SHOT mode�If the timer is enabled the Timer Output signal pulses
(changes state) for one system clock cycle after timer Reload.

CONTINUOUS mode�If the timer is enabled the Timer Output signal is
complemented after timer Reload.

COUNTER mode�If the timer is enabled the Timer Output signal is
complemented after timer reload.

0 = Count occurs on the rising edge of the Timer Input signal.

1 = Count occurs on the falling edge of the Timer Input signal.

PWM SINGLE OUTPUT mode�When enabled, the Timer Output is forced to
TPOL after PWM count match and forced back to TPOL after Reload.

CAPTURE mode�If the timer is enabled the Timer Output signal is
complemented after timer Reload.

0 = Count is captured on the rising edge of the Timer Input signal.

1 = Count is captured on the falling edge of the Timer Input signal.

COMPARE mode�The Timer Output signal is complemented after timer
Reload.

GATED mode�The Timer Output signal is complemented after timer Reload.

0 = Timer counts when the Timer Input signal is High and interrupts are
generated on the falling edge of the Timer Input.

1 = Timer counts when the Timer Input signal is Low and interrupts are
generated on the rising edge of the Timer Input.

CAPTURE/COMPARE mode�If the timer is enabled, the Timer Output signal is
complemented after timer Reload

0 = Counting starts on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.

1 = Counting starts on the first falling edge of the Timer Input signal. The
current count is captured on subsequent falling edges of the Timer Input signal.

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109

PWM DUAL OUTPUT mode�If enabled, the Timer Output is set=TPOL after
PWM match and set=TPOL after Reload. If enabled the Timer Output
Complement takes on the opposite value of the Timer Output. The PWMD field
in the T0CTL1 register determines an optional added delay on the assertion
(Low to High) transition of both Timer Output and the Timer Output
Complement for deadband generation.

CAPTURE RESTART mode�If the timer is enabled the Timer Output signal is
complemented after timer Reload.

0 = Count is captured on the rising edge of the Timer Input signal.

1 = Count is captured on the falling edge of the Timer Input signal.

COMPARATOR COUNTER mode�If the timer is enabled the Timer Output
signal is complemented after timer Reload.

0 = Count is captured on the rising edge of the Timer Input signal.

1 = Count is captured on the falling edge of the Timer Input signal.

TRIGGERED ONE-SHOT mode�If the timer is enabled the Timer Output signal
is complemented after timer Reload.

0 = The timer triggers on a Low to High transition on the input.

1 = The timer triggers on a High to Low transition on the input.

[5�3]

PRES

000

001

010

011

100

101

110

111

The timer input clock is divided by 2

PRES

, where PRES can be set from 0 to 7.

The prescaler is reset each time the Timer is disabled. This insures proper clock
division each time the Timer is restarted.

Divide by 1

Divide by 2

Divide by 4

Divide by 8

Divide by 16

Divide by 32

Divide by 64

Divide by 128

Bit

Position

Value

(H)

Description

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P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

111

LIN-UART

The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (LIN-
UART) is a full-duplex communication channel capable of handling asynchronous data
transfers in standard UART applications as well as providing LIN protocol support.

Features of the LIN-UART include:

�

8-bit asynchronous data transfer

�

Selectable even and odd-parity generation and checking

�

Option of one or two

Stop

bits

�

Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes

�

Separate transmit and receive interrupts

�

Framing, parity, overrun and break detection

�

16-bit Baud Rate Generator (BRG) which may function as a general purpose timer with
interrupt.

�

Driver Enable output for external bus transceivers

�

LIN protocol support for both master and slave modes

�

Break generation and detection

�

Selectable Slave Autobaud

�

Check Tx vs. Rx data when sending

�

Configurable digital noise filter on Receive Data line.

Architecture

The LIN-UART consists of three primary functional blocks: transmitter, receiver, and
baud rate generator. The LIN-UART's transmitter and receiver function independently, but
employ the same baud rate and data format. The basic UART operation is enhanced by the
Noise Filter and IrDA blocks. Figure 11 illustrates the LIN-UART architecture.

LIN-UART

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Data Format for Standard UART Modes

The LIN-UART always transmits and receives data in an 8-bit data format, least-signifi-
cant bit first. An even or odd parity bit or multiprocessor address/data bit can be optionally
added to the data stream. Each character begins with an active low Start bit and ends with
either 1 or 2 active high Stop bits. Figures 12 and 13 illustrate the asynchronous data for-
mat employed by the LIN-UART without parity and with parity, respectively.

Figure 11. LIN-UART Block Diagram

RxD

IrDA

Noise Filter

TxD

Parity Checker

System Bus

Receive Shifter

Parity Generator

Status Registers

Baud Rate

Generator

Control Registers

Rx IRQ

Tx IRQ

Transmitter Control

Receiver Control

with Address Compare

Receive Data

Transmit Data

Transmit Shift

CTS

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Transmitting Data using the Polled Method

Z8FMC16100 Series Flash MCU

Product Specification

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Transmitting Data using the Polled Method

Follow these steps to transmit data using the polled operating method:

1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate

baud rate.

2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for

alternate function operation.

3. If MULTIPROCESSOR mode is appropriate, write to the LIN-UART Control 1 Reg-

ister to enable MULTIPROCESSOR (9-bit) mode functions.

Set the MULTIPROCESSOR Mode Select (

MPEN

) to Enable MULTIPROCESSOR

mode.

4. Write to the LIN-UART Control 0 Register to:

a. Set the transmit enable bit (

TEN

) to enable the LIN-UART for data transmission

b. If parity is appropriate and multiprocessor mode is not enabled, set the parity

enable bit (

PEN

) and select either even or odd parity (

PSEL

c. Set or clear the

CTSE

bit to enable or disable control from the remote receiver

using the CTS pin.

Figure 12. LIN-UART Asynchronous Data Format without Parity

Figure 13. LIN-UART Asynchronous Data Format with Parity

Data Field

Start

Idle State

of Line

Stop Bit(s)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

lsb

msb

Data Field

Start

Idle State

of Line

Stop Bit(s)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Parity

lsb

msb

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5. Check the

TDRE

bit in the LIN-UART Status 0 register to determine if the Transmit

Data Register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit
Data Register is full (indicated by a 0), continue to monitor the

TDRE

bit until the

Transmit Data Register becomes available to receive new data.

6. If in MULTIPROCESSOR mode, write the LIN-UART Control 1 Register to select

the outgoing address bit.

Set the Multiprocessor Bit Transmitter (

MPBT

) if sending an address byte; clear it if

sending a data byte.

7. Write the data byte to the LIN-UART Transmit Data Register. The transmitter auto-

matically transfers the data to the Transmit Shift register and transmits the data.

8. If appropriate, and if MULTIPROCESSOR mode is enabled, make any changes to the

Multiprocessor Bit Transmitter (

MPBT

) value.

9. To transmit additional bytes, return to Step 5.

Transmitting Data using the Interrupt-Driven Method

The LIN-UART Transmitter interrupt indicates the availability of the Transmit Data Reg-
ister to accept new data for transmission. Follow these steps to configure the LIN-UART
for interrupt-driven data transmission:

1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate

baud rate.

2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for

alternate function operation.

3. Execute a DI instruction to disable interrupts.

4. Write to the Interrupt control registers to enable the LIN-UART Transmitter interrupt

and set the appropriate priority.

5. If multiprocessor mode is appropriate, write to the LIN-UART Control 1 Register to

enable Multiprocessor (9-bit) mode functions.

Set the MULTIPROCESSOR Mode Select (

MPEN

) to Enable MULTIPROCESSOR

mode.

6. Write to the LIN-UART Control 0 Register to:

a. Set the transmit enable bit (

TEN

) to enable the LIN-UART for data transmission

b. If multiprocessor mode is not enabled, enable parity, if appropriate, and select

either even or odd parity.

c. Set or clear the

CTSE

bit to enable or disable control from the remote receiver via

the CTS pin.

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P R E L I M I N A R Y

Receiving Data using the Polled Method

Z8FMC16100 Series Flash MCU

Product Specification

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7. Execute an EI instruction to enable interrupts.

The LIN-UART is now configured for interrupt-driven data transmission. Because the
LIN-UART Transmit Data Register is empty, an interrupt is generated immediately. When
the LIN-UART Transmit interrupt is detected, and there is transmit data ready to send, the
associated interrupt service routine (ISR) performs the following:

1. If in MULTIPROCESSOR mode, write the LIN-UART Control 1 Register to select

the outgoing address bit:

Set the Multiprocessor Bit Transmitter (

MPBT

) if sending an address byte, clear it if

sending a data byte.

2. Write the data byte to the LIN-UART Transmit Data Register. The transmitter auto-

matically transfers the data to the Transmit Shift register and transmits the data.

3. Execute the IRET instruction to return from the interrupt-service routine and wait for

the Transmit Data Register to again become empty.

If a transmit interrupt occurs and there is no transmit data ready to send the interrupt-ser-
vice routine will execute the IRET instruction. When the application does have data to
transmit, software can set the appropriate interrupt request bit in the Interrupt Controller to
initiate a new transmit interrupt. Another alternative would be for software to write the
data to the Transmit Data Register instead of invoking the interrupt-service routine.

Receiving Data using the Polled Method

Follow these steps to configure the LIN-UART for polled data reception:

1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate

baud rate.

2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for

alternate function operation.

3. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR mode

functions, if appropriate.

4. Write to the LIN-UART Control 0 Register to:

a. Set the receive enable bit (

REN

) to enable the LIN-UART for data reception

b. If multiprocessor mode is not enabled, enable parity, if appropriate, and select

either even or odd parity.

5. Check the

RDA

bit in the LIN-UART Status 0 register to determine if the Receive Data

RDA

is set to 1 to indicate

available data, continue to Step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.

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6. Read data from the LIN-UART Receive Data Register. If operating in MULTIPRO-

CESSOR (9-bit) mode, further actions may be required depending on the Multiproces-
sor Mode bits

MPMD

[1:0].

7. Return to Step 5 to receive additional data.

Receiving Data using the Interrupt-Driven Method

The LIN-UART Receiver interrupt indicates the availability of new data (as well as error
conditions). Follow these steps to configure the LIN-UART receiver for interrupt-driven
operation:

1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate

baud rate.

2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for

alternate function operation.

3. Execute a DI instruction to disable interrupts.

4. Write to the Interrupt control registers to enable the LIN-UART Receiver interrupt and

set the appropriate priority.

5. Clear the LIN-UART Receiver interrupt in the applicable Interrupt Request Register.

6. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR (9-bit)

mode functions, if appropriate.
a. Set the MULTIPROCESSOR Mode Select (

MPEN

) to Enable Multiprocessor

mode.

b. Set the MULTIPROCESSOR Mode Bits,

MPMD[1:0],

to select the appropriate

address matching scheme.

c. Configure the LIN-UART to interrupt on received data and errors or errors only

(interrupt on errors only is unlikely to be useful for Z8FMC16100 Series Flash
MCU devices without a DMA block),

7. Write the device address to the Address Compare Register (automatic multiprocessor

modes only).

8. Write to the LIN-UART Control 0 Register to:

a. Set the receive enable bit (

REN

) to enable the LIN-UART for data reception

b. If MULTIPROCESSOR mode is not enabled, enable parity, if appropriate, and

select either even or odd parity.

9. Execute an EI instruction to enable interrupts.

The LIN-UART is now configured for interrupt-driven data reception. When the LIN-
UART Receiver interrupt is detected, the associated interrupt service routine (ISR) per-
forms the following:

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P R E L I M I N A R Y

Clear To Send Operation

Z8FMC16100 Series Flash MCU

Product Specification

117

1. Check the LIN-UART Status 0 register to determine the source of the interrupt - error,

break, or received data.

2. If the interrupt was due to data available, read the data from the LIN-UART Receive

Data Register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the multiprocessor mode bits

MPMD

[1:0].

3. Execute the IRET instruction to return from the interrupt-service routine and await

more data.

Clear To Send Operation

The Clear To Send (CTS) pin, if enabled by the

CTSE

bit of the LIN-UART Control 0 Reg-

ister, performs flow control on the outgoing transmit data stream. The Clear To Send
(CTS) input pin is sampled one system clock before beginning any new character trans-
mission. To delay transmission of the next data character, an external receiver must deas-
sert CTS at least one system clock cycle before a new data transmission begins. For
multiple character transmissions, this operation is typically performed during the Stop Bit
transmission. If CTS deasserts in the middle of a character transmission, the current char-
acter is sent completely.

External Driver Enable

The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multitransceiver bus, such as RS-485.

Driver Enable is a programmable polarity signal that envelopes the entire transmitted data
frame including parity and Stop bits as illustrated in Figure 14. The Driver Enable signal
asserts when a byte is written to the LIN-UART Transmit Data Register. The Driver
Enable signal asserts at least one bit period and no greater than two bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the last

Stop

bit is transmitted. This

one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data Regis-
ter before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The

DEPOL

bit in the LIN-UART Control Register 1 sets the polarity

of the Driver Enable signal.

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The Driver Enable to

START

bit set-up time is calculated as follows:

LIN-UART Special Modes

The special modes of the LIN-UART are:

�

Multiprocessor Mode

�

LIN Mode

The LIN-UART features a common control register (Control 0) that contains a unique reg-
ister address and several mode-specific control registers (Multiprocessor Control, Noise
Filter Control, and LIN Control) that share a common register address (Control 1). When
the Control 1 address is read or written, the

MSEL[2:0]

(Mode Select) field of the Mode

Select and Status Register determines which physical register is accessed. Similarly, there
are mode-specific status registers, one of which is returned when the Status 0 Register is
read, depending on the

MSEL

field.

Multiprocessor Mode

The LIN-UART features a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit
for selective communication when a number of processors share a common UART bus. In
MULTIPROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (

) is

transmitted immediately following the 8-bits of data and immediately preceding the

Stop

bit(s) as illustrated in Figure 15. The character format is:

Figure 14. LIN-UART Driver Enable Signal Timing

(shown with 1 Stop Bit and Parity)

� DE to Start Bit Setup Time(s) �

Baud Rate (Hz)

Data Field

Start

Idle State

of Line

Stop Bit(s)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Parity

lsb

msb

PS024604-1005

P R E L I M I N A R Y Multiprocessor

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Z8FMC16100 Series Flash MCU

Product Specification

119

In Multiprocessor (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPRO-
CESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide MULTI-
PROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the LIN-UART Address Compare register holds the network
address of the device.

Multiprocessor Mode Receive Interrupts

When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only
frames addressed to it. The determination of whether a frame of data is addressed to the
LIN-UART can be made in hardware, software or a combination of the two, depending on
the multiprocessor configuration bits. In general, the address compare feature reduces the
load on the CPU, because it does not need to access the LIN-UART when it receives data
directed to other devices on the multinode network. The following three MULTIPROCES-
SOR modes are available in hardware:

�

Interrupt on all address bytes

�

Interrupt on matched address bytes and correctly framed data bytes

�

Interrupt only on correctly framed data bytes

These modes are selected with

MPMD[1:0]

in the LIN-UART Control 1 Register. For all

multiprocessor modes, bit

MPEN

of the LIN-UART Control 1 Register must be set to 1.

The first scheme is enabled by writing

01b

MPMD[1:0]

. In this mode, all incoming

address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine checks the address byte that triggered the interrupt. If it matches the LIN-
UART address, the software clears

MPMD[0]

. At this point, each new incoming byte

interrupts the CPU. The software determines the end of the frame and checks for it by
reading the

MPRX

bit of the LIN-UART Status 1 Register for each incoming byte. If

MPRX

=1, a new frame has begun. If the address of this new frame is different from the

LIN-UART's address, then

MPMD[0]

must be set to 1 by software, causing the LIN-

UART interrupts to go inactive until the next address byte. If the new frame's address
matches the LIN-UART's, then the data in the new frame is processed as well.

Figure 15. LIN-UART Asynchronous Multiprocessor Mode Data Format

Data Field

Start

Idle State

of Line

Stop Bit(s)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

lsb

msb

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The second scheme is enabled by setting MPMD[1:0] to 10B and writing the LIN-UART's
address into the LIN-UART Address Compare Register. This mode introduces more hard-
ware control, interrupting only on frames that match the LIN-UART's address. When an
incoming address byte does not match the LIN-UART's address, it is ignored. All succes-
sive data bytes in this frame are also ignored. When a matching address byte occurs, an
interrupt is issued and further interrupts occur on each successive data byte. The first data
byte in the frame has

NEWFRM

=1 in the LIN-UART Status 1 Register. When the next

address byte occurs, the hardware compares it to the LIN-UART's address. If there is a
match, the interrupt occurs and the

NEWFRM

bit is set for the first byte of the new frame. If

there is no match, the LIN-UART ignores all incoming bytes until the next address match.

The third scheme is enabled by setting

MPMD

[1:0] to

11B

and by writing the LIN-UART's

address into the LIN-UART Address Compare Register. This mode is identical to the sec-
ond scheme, except that there are no interrupts on address bytes. The first data byte of
each frame remains accompanied by a

NEWFRM

assertion.

LIN Protocol Mode

The LIN (Local Interconnect Network) protocol as supported by the LIN-UART module is
defined in rev 2.0 of the LIN Specification Package. The LIN protocol specification cov-
ers all aspects of transferring information between LIN Master and Slave devices using
message frames including error detection and recovery, sleep mode and wake up from
sleep mode. The LIN-UART hardware in LIN mode provides character transfers to sup-
port the LIN protocol including BREAK transmission and detection, WAKE-UP transmis-
sion and detection, and slave autobauding. Part of the error detection of the LIN protocol
is for both master and slave devices to monitor their receive data when transmitting. If the
receive and transmit data streams do not match, the LIN-UART asserts the

PLE

bit (phys-

ical layer error bit in Status0 register). The message frame time-out aspect of the protocol
is left to software, requiring the use of an additional general purpose timer. The LIN mode
of the LIN-UART does not provide any hardware support for computing/verifying the
checksum field or verifying the contents of the Identifier field. These fields are treated as
data and are not interpreted by hardware. The checksum calculation/verification can easily
be implemented in software via the ADC (Add with Carry) instruction.

The LIN bus contains a single master and one or more slaves. The LIN master is responsi-
ble for transmitting the message frame header which consists of the Break, Synch and
Identifier fields. Either the master or one of the slaves transmits the associated response
section of the message which consists of data characters followed by a checksum charac-
ter.

In LIN mode, the interrupts defined for normal UART operation still apply with the fol-
lowing changes.

�

Parity Error (

bit in Status0 register) is redefined as the Physical Layer Error (

PLE

)

bit. The

PLE

bit indicates that receive data does not match transmit data when the LIN-

UART is transmitting. This applies to both Master and Slave operating modes.

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LIN Protocol Mode

Z8FMC16100 Series Flash MCU

Product Specification

121

�

The Break Detect interrupt (

BRKD

bit in Status0 register) indicates when a Break is de-

tected by the slave (break condition for at least 11 bit times). Software can use this in-
terrupt to start a timer checking for message frame time-out. The duration of the break
can be read in the

RxBreakLength[3:0]

field of the Mode Status Register.

�

The Break Detect interrupt (

BRKD

bit in Status0 register) indicates when a Wake-up

message has been received if the LIN-UART is in LinSleep state.

�

In LIN slave mode, if the BRG counter overflows while measuring the autobaud period
(Start bit to beginning of bit 7 of autobaud character) an Overrun Error is indicated (

bit in the Status0 register). In this case, software sets the LinState field back to

10b

where the Slave ignores the current message and waits for the next Break. The Baud
Reload High and Low registers are not updated by hardware if this autobaud error oc-
curs. The

bit is also set if a data overrun error occurs.

LIN System Clock Requirements

The LIN master provides the timing reference for the LIN network and is required to have
a clock source with a tolerance of �0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within �14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of �2%. If a Slave does not con-
tain autobaud capability it must include a baud clock which deviates from the masters by
no more than �1.5%. These accuracy requirements must include affects such as voltage
and temperature drift during operation.

Before sending/receiving messages, the Baud Reload High/Low registers must be initial-
ized. Unlike standard UART modes, the Baud Reload High/Low registers must be loaded
with the baud interval rather than 1/16 of the baud interval.

In order to autobaud with the required accuracy, the LIN slave system clock must be at
least 100 times the baud rate.

LIN Mode Initialization and Operation

The LIN protocol mode is selected by setting either the

LMST

(LIN Master) or

LSLV

(LIN

Slave), and optionally (for LIN slave) the

ABEN

(Autobaud Enable) bits in the LIN Control

MSEL

(Mode Select) field of the LIN-

UART Mode Select/Status register must be = 010B. The LIN-UART Control0 register
must be initialized with

TEN

= 1,

REN

= 1, all other bits = 0.

In addition to the

LMST

LSLV

and

ABEN

bits in the LIN Control Register, a

Lin-

State

[1:0] field exists that defines the current state of the LIN logic. This field is initially

set by software. In the LIN Slave mode, the

LinState

field is updated by hardware as the

Slave moves through the Wait For Break, AutoBaud, and Active states.

The Noise Filter may also need to be enabled and configured when interfacing to a LIN
bus.

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LIN MASTER Mode Operation

LIN MASTER mode is selected by setting

LMST

= 1,

LSLV

= 0,

ABEN

= 0,

LinState

[1:0]

11B.

If the LIN bus protocol indicates the bus is required go into the LIN sleep state, the

LinState

[1:0] bits must be set =

00B

by software.

The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the

TxBreakLength

field of the LIN

Control Register. The transmission of the Break is performed by setting the

SBRK

bit in the

Control 0 Register. The LIN-UART starts the Break once the

SBRK

bit is set and any char-

acter transmission currently underway has completed. The

SBRK

bit is deasserted by hard-

ware once the break is completed.

The Synch character is transmitted by writing a

55H

to the Transmit Data Register (

TDRE

must = 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.

The Identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (

TDRE

must = 1 before writing).

If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the

TDRE

bit asserts. If the trans-

mit data register is written after

TDRE

asserts, but before

TXE

asserts, the hardware inserts

one or two stop bits between each character as determined by the

Stop

bit in the Control0

TXE

asserts before the next

character is written.

If the selected slave is sending the response portion of the frame to the master, each
receive byte will be signalled by the receive data interrupt (

RDA

bit will be set in the

Status0 register).

If the selected slave is sending the response to a different slave, the master can ignore the
response characters by deasserting the

REN

bit in the Control0 register until the frame time

slot has completed.

LIN Sleep Mode

While the LIN bus is in the sleep state, the CPU can be in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus may issue a Wake-
up message if it requires the master to initiate a LIN message frame. Following the Wake-
up message, the master wakes up and initiates a new message. A Wake-up message is
accomplished by pulling the bus low for at least 250 �s but less than 5 ms. Transmitting a

00h

character is one way to transmit the wake-up message.

If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up mes-
sage duration.

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LIN Protocol Mode

Z8FMC16100 Series Flash MCU

Product Specification

123

If the CPU is in HALT or operational mode, the LIN-UART (if enabled) times the duration
of the Wake-up and provides an interrupt following the end of the break sequence if the
duration is

3 bit times. The total duration of the Wake-up message in bit times may be

obtained by reading the

RxBreakLength

field in the Mode Status register. After a Wake-

up message has been detected, the LIN-UART can be placed (by software) into either LIN
Master or LIN Slave Wait for Break states as appropriate. If the break duration exceeds 15
bit times, the

RxBreakLength

field contains the value

. If the LIN-UART is disabled,

the Wake-up message can be detected via a port pin interrupt and timed by software. If the
device is in STOP mode, the high to low transition on the port pin will bring the device out
of STOP mode.

The LIN Sleep state is selected by software setting

LinState

[1:0] = 00. The decision to

move from an active state to sleep state is based on the LIN messages as interpreted by
software.

LIN Slave Operation

LIN Slave mode is selected by setting

LMST

= 0,

LSLV

= 1,

ABEN

= 1 or 0 and

Lin-

State

[1:0] =

01b

(Wait for Break State). The LIN slave detects the start of a new mes-

sage by the Break which appears to the Slave as a break of at least 11 bit times in duration.
The LIN-UART detects the Break and generates an interrupt to the CPU. The duration of
the Break is observable in the

RxBreakLength

field of the Mode Status register. A Break

of less than 11 bit times in duration does not generate a break interrupt when the LIN-
UART is in Wait for Break state. If the Break duration exceeds 15 bit times, the

RxBreak-

Length

field contains the value

Following the Break the LIN-UART hardware automatically transitions to the Autobaud
state, where it autobauds by timing the duration of the first 8 bit times of the Synch charac-
ter as defined in the standard. At the end of the autobaud period, the duration measured by
the BRG counter (auto baud period divided by 8) is automatically transferred to the Baud
Reload High and Low registers if the

ABEN

bit of the LIN control register is set. If the

BRG Counter overflows before reaching the start of bit 7 in the autobaud sequence the
Autobaud Overrun Error interrupt occurs, the

bit in the Status0 register is set and the

Baud Reload registers are not updated. To autobaud within 2% of the master's baud rate,
the slave system clock must be a minimum of 100 times the baud rate. To avoid an auto-
baud overrun error, the system clock must not be greater than 2

times the baud rate (16

bit counter following 3-bit prescaler when counting the 8 bit times of the Autobaud
sequence).

Following the Synch character, the LIN-UART hardware transitions to the Active state
where the Identifier character is received and the characters of the Response section of the
message are sent or received. The Slave remains in the Active state until a Break is
received or software forces a state change. Once in Active State (autobaud has completed),
a Break of 10 or more bit times is recognized and will cause a transition to the Autobaud
state.

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If the Identifier character indicates that this slave device is not participating in the mes-
sage, software can set the

LinState[1:0]

01b

(Wait for Break State) to ignore the rest

of the message. No further receive interrupts will occur until the next Break.

LIN-UART Interrupts

The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.

Transmitter Interrupts

The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(

TDRE

) is set to 1. This indicates that the transmitter is ready to accept new data for trans-

mission. The TDRE interrupt occurs when the transmitter is initially enabled and after the
Transmit shift register has shifted the first bit of a character out. At this point, the Transmit
Data Register may be written with the next character to send. This provides 7 bit periods
of latency to load the Transmit Data Register before the Transmit shift register completes
shifting the current character. Writing to the LIN-UART Transmit Data Register clears the

TDRE

bit to 0.

Receiver Interrupts

The receiver generates an interrupt when any of the following occurs:

�

A data byte has been received and is available in the LIN-UART Receive Data Regis-
ter. This interrupt can be disabled independent of the other receiver interrupt sources
via the

RDAIRQ

bit (this feature is useful in devices which support DMA). The received

data interrupt occurs once the receive character has been placed in the Receive Data
Register. Software must respond to this received data available condition before the
next character is completely received to avoid an overrun error.

In MULTIPROCESSOR mode (

MPEN

= 1), the receive data interrupts are dependent on

the multiprocessor configuration and the most recent address byte

�

A break is received

�

A receive data overrun or LIN slave autobaud overrun error is detected.

�

A data framing error is detected

�

A parity error is detected (physical layer error in LIN mode)

LIN-UART Overrun Errors

When an overrun error condition occurs the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The Break Detect and Overrun status bits are
not displayed until after the valid data has been read.

Note:

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P R E L I M I N A R Y LIN-UART

Interrupts

Z8FMC16100 Series Flash MCU

Product Specification

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After the valid data has been read, the

bit of the Status 0 register is updated to indicate

the overrun condition (and Break Detect, if applicable). The

RDA

bit is set to 1 to indicate

that the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The

BRKD

bit indicates

if the overrun was caused by a break condition on the line. After reading the status byte
indicating an overrun error, the Receive Data Register must be read again to clear the error
bits in the LIN-UART Status 0 register.

In LIN mode, an Overrun Error is signaled for receive data overruns as described above
and in the LIN Slave if the BRG Counter overflows during the autobaud sequence (the

ATB

bit will also be set in this case). There is no data associated with the autobaud over-

flow interrupt, however the Receive Data Register must be read to clear the

bit. In this

case software must write a 10B to the

LinState

field, forcing the LIN slave back to a

Wait for Break state.

LIN-UART Data- and Error-Handling Procedure

Figure 16 illustrates the recommended procedure for use in LIN-UART receiver interrupt
service routines.

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LIN-UART Baud Rate Generator

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Product Specification

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The transmitter can be enabled in this mode.

LIN-UART Baud Rate Generator

The LIN-UART Baud Rate Generator creates a lower frequency baud rate clock for data
transmission. The input to the Baud Rate Generator is the system clock. The LIN-UART
Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
(

BRG

[15:0]) that sets the data transmission rate (baud rate) of the LIN-UART. The LIN-

UART data rate is calculated using the following equation for normal UART operation:

The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:

When the LIN-UART is disabled, the Baud Rate Generator can function as a basic 16-bit
timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with
interrupt on time-out, complete the following procedure:

1. Disable the LIN-UART receiver by clearing the

REN

bit in the LIN-UART Control 0

TEN

bit may be asserted, transmit activity may occur).

2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low

Byte registers.

3. Enable the Baud Rate Generator timer function and associated interrupt by setting the

BRGCTL

bit in the LIN-UART Control 1 Register to 1.

Noise Filter

A noise filter circuit is included which filters noise on a digital input signal (such as UART
Receive Data) before the data is sampled by the block. This is likely to be a requirement
for protocols with a noisy environment.

The noise filter contains the following features:

�

Synchronizes the receive input data to the System Clock

�

Noise Filter Enable (

NFEN

) input selects whether the noise filter is bypassed (

NFEN

0) or included (

NFEN = 1

) in the receive data path.

UART Data Rate (bits/s) =

System Clock Frequency (Hz)

16 x UART Baud Rate Divisor Value

UART Data Rate (bits/s) =

System Clock Frequency (Hz)

UART Baud Rate Divisor Value

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�

Noise Filter Control (

NFCTL[2:0]

) input selects the width of the up/down saturating

counter digital filter. The available widths range from 4 bits to 11 bits.

�

The digital filter output features hysteresis

�

Provides an active low Saturated State output (

FiltSatB

) which is used as an indica-

tion of the presence of noise.

Architecture

Figure 17 illustrates how the noise filter is integrated with the LIN-UART for use on a
LIN network.

Operation

The figure below illustrates the operation of the noise filter both with and without noise.
The noise filter in this example is a 2-bit up/down counter which saturates at

00b

and

11b.

A 2-bit counter is shown for convenience, the operation of wider counters is similar.

The output of the filter switches from 1 to 0 when the counter counts down from

01b

00b

and switches from 0 to 1 when the counter counts up from

10b

11b.

The noise

filter delays the receive data by three System Clock cycles.

The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit
time. The presence of noise (

FiltSatB = 1

at center of bit time) does not mean the sam-

pled data is incorrect, just that the filter is not in its "saturated" state of all 1's or all 0's. If
FiltSatB = 1 when RxD is sampled during a receive character, the

bit in the

ModeSta-

tus[4:0]

field is set. By observing this bit, an indication of the level of noise in the net-

work can be obtained.

Figure 17. Noise Filter System Block Diagram

RxD

TxD

RxD

TxD

RxD

LIN Bus

TxD

FiltSatB

NFEN, NFCTL

System

Clock

LIN-UART

Noise

Filter

GPIO

LIN

Transceiver

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LIN-UART Control Register Definitions

The LIN-UART control registers support the LIN-UART, the associated Infrared Encoder/
Decoder and the noise filter. For more information on the infrared operation, refer to the

Infrared Encoder/Decoder

chapter on page 145.

LIN-UART Transmit Data Register

Data bytes written to the LIN-UART Transmit Data Register, shown in Table 66, are
shifted out on the TxD pin. The Write-only LIN-UART Transmit Data Register shares a
Register File address with the read-only LIN-UART Receive Data Register.

TXD--Transmit Data

LIN-UART transmitter data byte to be shifted out through the TXD pin.

LIN-UART Receive Data Register

Data bytes received through the RxD pin are stored in the LIN-UART Receive Data Reg-
ister, shown in Table 67. The read-only LIN-UART Receive Data Register shares a Regis-
ter File address with the Write-only LIN-UART Transmit Data Register.

Table 66. LIN-UART Transmit Data Register (U0TXD)

BITS

FIELD

TXD

RESET

R/W

ADDR

F40H

Table 67. LIN-UART Receive Data Register (U0RXD)

BITS

FIELD

RXD

RESET

R/W

ADDR

F40H

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Z8FMC16100 Series Flash MCU

Product Specification

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RXD--Receive Data

LIN-UART receiver data byte from the RXD pin

LIN-UART Status 0 Register

The LIN-UART Status 0 Register identifies the current LIN-UART operating configura-
tion and status. Table 68 describes the Status 0 Register for standard UART mode.

Table

, which follows on page 132, describes the Status0 Register for LIN mode. A more

detailed discussion of each bit follows each table.

Receive Data Available (RDA).

This bit indicates that the LIN-UART Receive Data Reg-

ister has received data. Reading the LIN-UART Receive Data Register clears this bit.

Parity Error (PE).

This bit indicates that a parity error has occurred. Reading the Receive

Data Register clears this bit.

Overrun Error (OE).

This bit indicates that an overrun error has occurred. An overrun

occurs when new data is received and the Receive Data Register has not been read. Read-
ing the Receive Data Register clears this bit.

Framing Error (FE).

This bit indicates that a framing error (no STOP bit following data

reception) was detected. Reading the Receive Data Register clears this bit.

Break Detect (BRKD).

This bit indicates that a break occurred. If the data bits, parity/

multiprocessor bit, and STOP bit(s) are all zeros then this bit is set to 1. Reading the
Receive Data Register clears this bit.

Transmitter Data Register Empty (TDRE).

This bit indicates that the Transmit Data

Transmitter Empty (TXE).

This bit indicates that the transmit shift register is empty and

character transmission is finished.

Clear To Send Signal (CTS).

When this bit is read it returns the level of the CTS signal.

If LBEN = 1, the CTS input signal is replaced by the internal Receive Data Available sig-

Table 68. LIN-UART Status 0 Register - standard UART mode (U0STAT0)

BITS

FIELD

RDA

BRKD

TDRE

TXE

CTS

RESET

R/W

ADDR

F41H

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nal to provide flow control in loopback mode. CTS only affects transmission if the CTSE
bit = 1.

Receive Data Available (RDA).

This bit indicates that the Receive Data Register has

received data. Reading the Receive Data Register clears this bit.

Physical Layer Error (PLE).

This bit indicates that transmit and receive data do not

match when a LIN slave or master is transmitting. This could be caused by a fault in the
physical layer or multiple devices driving the bus simultaneously. Reading the Status 0
Register or the Receive Data Register clears this bit.

Receive Data and Autobaud Overrun Error (OE).

This bit is set just as in normal UART

operation if a receive data overrun error occurs. This bit is also set during LIN Slave auto-
baud if the BRG counter overflows before the end of the autobaud sequence, indicating
the receive activity was not an autobaud character or the master baud rate is too slow. The
ATB status bit will also be set in this case. This bit is cleared by reading the Receive Data
Register.

Framing Error (FE).

This bit indicates that a framing error (no STOP bit following data

reception) was detected. Reading the Receive Data Register clears this bit.

Break Detect (BRKD).

This bit is set in LIN mode if (a) in LinSleep state and a break of at

least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and a break of
at least 11 bit times occurred (Break event) or (c) in Slave Active state and a break of at
least 10 bit times occurs. Reading the Status 0 Register or the Receive Data Register clears
this bit.

Transmitter Data Register Empty (TDRE).

This bit indicates that the Transmit Data

Transmitter Empty (TXE).

This bit indicates that the transmit shift register is empty and

character transmission is finished.

LIN Slave Autobaud Complete (ATB).

This bit is set in LIN SLAVE mode when an auto-

baud character is received. If the ABIEN bit is set in the LIN Control Register, then a

Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0)

BITS

FIELD

RDA

PLE

ABOE

BRKD

TDRE

TXE

ATB

RESET

R/W

ADDR

F41H

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Mode Select and Status Register

Z8FMC16100 Series Flash MCU

Product Specification

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receive interrupt is generated when this bit is set. Reading the Status 0 Register clears this
bit. This bit will be 0 in LIN MASTER mode.

LIN-UART Mode Select and Status Register

The LIN-UART Mode Select and Status Register, shown in Table 70, contains mode select
and status bits. A more detailed discussion of each bit follows the table.

MSEL--Mode Select.

This R/W field determines which control register is accessed when performing a write or
read to the Uart Control 1 Register address. This field also determines which status is
returned in the ModeStatus field when reading this register.

000 = Multiprocessor and normal UART control/status

001 = Noise Filter control/status

010 = LIN Protocol control/status

011�110: reserved

111 = LIN-UART Hardware Revision (allows hardware revision to be read in the Mode
Status field)

Mode Status. This read-only field returns status corresponding to the mode selected by

MSEL

as follows

000 : Multiprocessor and normal UART mode status = {

, 0, 0,

NEWFRM, MPRX

}

001 : Noise Filter status = {

, 0,0,0,0}

010 : LIN mode status = {

NE, RxBreakLength[3:0

]}

011�110 : reserved = {0, 0, 0, 0, 0}

111 : LIN-UART hardware revision

MULTIPROCESSOR Mode Status field (MSEL = 000B)

NE--Noise Event. This bit is asserted if digital noise is detected on the receive data line
while the data is sampled (center of bit time). If this bit is set, it does not mean that the
receive data is corrupted (though it may be in extreme cases), just that one or more of the
noise filter data samples near the center of the bit time did not match the average data
value.

Table 70. LIN-UART Mode Select and Status Register (U0MDSTAT)

BITS

FIELD

MSEL

Mode Status

RESET

R/W

R/W

ADDR

F44H

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NEWFRM--Status bit denoting the start of a new frame. Reading the LIN-UART Receive
Data register resets this bit to 0.

0 = The current byte is not the first data byte of a new frame.

1 = The current byte is the first data byte of a new frame.

MPRX--Multiprocessor Receive

Returns the value of the last multiprocessor bit received. Reading from the LIN-UART
Receive Data register resets this bit to 0.

Digital Noise Filter Mode Status Field (MSEL =

001B

)

LIN Mode Status Field (MSEL =

010B

)

NE--Noise Event. This bit is asserted if some noise level is detected on the receive data
line while the data is sampled (center of bit time). If this bit is set, it does not indicate that
the receive data is corrupt (though it may be in extreme cases), just that one or more of the
16x data samples near the center of the bit time did not match the average data value.

RxBreakLength--LIN mode received break length. This field may be read following a
break (LIN WAKE-UP or BREAK) so software can determine the measured duration of
the break. If the break exceeds 15 bit times the value saturates at

1111B

Hardware Revision Mode Status Field (MSEL =

111B

)

This field indicates the hardware revision of the LIN-UART block.

00_xxx LIN UART hardware rev

01_xxx reserved

10_xxx reserved

11_xxx reserved

LIN-UART Control 0 Register

The LIN-UART Control 0 Register, shown in Table 71, configures the basic properties of
the LIN-UART's transmit and receive operations. A more detailed discussion of each bit
follows the table.

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TEN--Transmit Enable

This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is

enabled.

0 = Transmitter disabled.

1 = Transmitter enabled.

REN--Receive Enable

This bit enables or disables the receiver.

0 = Receiver disabled.

1 = Receiver enabled.

CTSE--CTS Enable

0 = The CTS signal has no effect on the transmitter.

1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.

PEN--Parity Enable

This bit enables or disables parity. Even or odd is determined by the PSEL bit.

0 = Parity is disabled. This bit is overridden by the

MPEN

bit.

1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.

PSEL--Parity Select

0 = Even parity is transmitted and expected on all received data.

1 = Odd parity is transmitted and expected on all received data.

SBRK--Send Break

This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit. In
standard UART mode, the duration of the break is determined by how long software
leaves this bit asserted. Also the duration of any required Stop bits following the break
must be timed by software before writing a new byte to be transmitted to the transmit data
register. In LIN mode, the master sends a Break character by asserting

SBRK

. The duration

of the break is timed by hardware, and the

SBRK

bit is deasserted by hardware when the

Break is completed. The duration of the Break is determined by the

TxBreakLength

field

Table 71. LIN-UART Control 0 Register (U0CTL0)

BITS

FIELD

TEN

REN

CTSE

PEN

PSEL

SBRK

STOP

LBEN

RESET

R/W

R/W

ADDR

F42H

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of the LIN Control register. One or two stop bits are automatically provided by the hard-
ware in LIN mode as defined by the

STOP

bit.

0 = No break is sent.

1 = The output of the transmitter is 0.

STOP--Stop Bit Select

0 = The transmitter sends one stop bit.

1 = The transmitter sends two stop bits.

LBEN--Loop Back Enable

0 = Normal operation.

1 = All transmitted data is looped back to the receiver within the IrDA module.

LIN-UART Control 1 Registers

Multiple registers, shown in Tables 72 through 74) are accessible by a single bus address.
The register selected is determined by the Mode Select (MSEL) field. These registers pro-
vide additional control over LIN-UART operation.

Multiprocessor Control Register

When MSEL =

000b

, the Multiprocessor Control Register, shown in Table 72, provides

control for UART multiprocessor mode, IRDA mode, baud rate timer mode as well as other
features that may apply to multiple modes. A more detailed discussion of each bit follows
the table.

MPMD[1:0]--Multiprocessor Mode

If MULTIPROCESSOR (9-bit) mode is enabled,

00 = The LIN-UART generates an interrupt request on all received bytes (data and
address).

01 = The LIN-UART generates an interrupt request only on received address bytes.

10 = The LIN-UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs.

Table 72. MultiProcessor Control Register (U0CTL1 with MSEL = 000b)

BITS

FIELD

MPMD[1]

MPEN

MPMD[0]

MPBT

DEPOL

BRGCTL

RDAIRQ

IREN

RESET

R/W

R/W

ADDR

F43H with MSEL = 000b

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Z8FMC16100 Series Flash MCU

Product Specification

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11 = The LIN-UART generates an interrupt request on all received data bytes for which
the most recent address byte matched the value in the Address Compare Register.

MPEN--MULTIPROCESSOR (9-bit) Enable

This bit is used to enable MULTIPROCESSOR (9-bit) mode.

0 = Disable Multiprocessor (9-bit) mode.

1 = Enable Multiprocessor (9-bit) mode.

MPBT--Multiprocessor Bit Transmit

This bit is applicable only when Multiprocessor (9-bit) mode is enabled.

0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).

1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).

DEPOL--Driver Enable Polarity

0 = DE signal is Active High.

1 = DE signal is Active Low.

BRGCTL--Baud Rate Generator Control

This bit causes different LIN-UART behavior depending on whether the LIN-UART
receiver is enabled (

REN

= 1 in the LIN-UART Control 0 Register).

When the LIN-UART receiver is not enabled, this bit determines whether the Baud Rate
Generator issues interrupts.

0 = BRG is disabled. Reads from the Baud Rate High and Low Byte registers return the
BRG Reload Value

1 = BRG is enabled and counting. The Baud Rate Generator generates a receive interrupt
when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return
the current BRG count value.

When the LIN-UART receiver is enabled, this bit allows reads from the Baud Rate Regis-
ters to return the BRG count value instead of the Reload Value.

0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.

1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low
Byte is read.

RDAIRQ--Receive Data Interrupt Enable

0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.

1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.

IREN--Infrared Encoder/Decoder Enable

0 = Infrared Encoder/Decoder is disabled. LIN-UART operates normally.

1 = Infrared Encoder/Decoder is enabled. The LIN-UART transmits and receives data
through the Infrared Encoder/Decoder.

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Noise Filter Control Register

When MSEL =

001b

, the Noise Filter Control Register, shown in Table , provides control

for the digital noise filter. A more detailed discussion of each bit follows the table.

NFEN--Noise Filter Enable

0 = Noise filter is disabled.

1 = Noise filter is enabled. Receive data is preprocessed by the noise filter.

NFCTL--Noise Filter Control

This field controls the delay and noise rejection characteristics of the noise filter. The
wider the counter the more delay that is introduced by the filter and the wider the noise
event that is filtered.

000 = 4-bit up/down counter

001 = 5-bit up/down counter

010 = 6-bit up/down counter

011 = 7-bit up/down counter

100 = 8-bit up/down counter

101 = 9-bit up/down counter

110 = 10-bit up/down counter

111 = 11-bit up/down counter

LIN Control Register

When

MSEL

010b

, the LIN Control Register provides control for the LIN mode of oper-

ation. A more detailed discussion of each bit follows the table.

Table 73. Noise Filter Control Register (U0CTL1 with MSEL = 001b)

BITS

FIELD

NFEN

NFCTL

Reserved

RESET

R/W

R/W

ADDR

F43H with MSEL = 001b

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Z8FMC16100 Series Flash MCU

Product Specification

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LMST--LIN Master Mode

0 = LIN Master Mode not selected

1 = LIN Master Mode selected (if

MPEN, PEN, LSLV

= 0)

LSLV--LIN Slave Mode

0 = LIN Slave Mode not selected

1 = LIN Slave Mode selected (if

MPEN, PEN, LMST

= 0)

ABEN--Autobaud Enable

0 = Autobaud not enabled

1 = Autobaud enabled if in LIN Slave mode.

ABIEN--Autobaud Interrupt Enable

0 = Interrupt following Autobaud does not occur

1 = Interrupt WILL follow Autobaud if in LIN Slave mode and

ABEN

= 1. When the Auto-

baud character is received, a receive interrupt is generated and the

ATB

bit is set in the

Status0 register. There is no receive data associated with this interrupt. The Baud Reload
registers will be updated by hardware with the new bit period value.

LinState[1:0]--LIN State Machine

The LinState is controlled by both hardware and software. Software can force a state
change at any time if necessary. In normal operation, software moves the state in and out
of Sleep state. For a LIN Slave, software changes the state from Sleep to Wait for Break
after which hardware cycles through the Wait for Break, Autobaud and Active states. Soft-
ware changes the state from one of the active states to Sleep state if the LIN bus goes into
Sleep mode. For a LIN Master, software changes the state from Sleep to Active where it
remains until software sets it back to the Sleep state. After configuration software does not
alter the

LinState

field during operation.

00 = Sleep State (either LMST or LSLV may be set)

01 = Wait for Break state (only valid for LSLV = 1)

10 = Autobaud state (only valid for LSLV = 1)

11 = Active state (either LMST or LSLV may be set)

TxBreakLength --Used in LIN mode by the master to control the duration of the transmit-
ted Break.

Table 74. LIN Control Register (U0CTL1 with MSEL = 010b)

BITS

FIELD

LMST

LSLV

ABEN

ABIEN

LinState[1:0]

TxBreakLength

RESET

R/W

R/W

ADDR

F43H with MSEL = 010b

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00 = 13 bit times

01 = 14 bit times

10 = 15 bit times

11 = 16 bit times

LIN-UART Address Compare Register

The LIN-UART Address Compare Register stores the multinode network address of the
LIN-UART. When the MPMD[1] bit of the LIN-UART Control Register 0 is set, all incom-
ing address bytes are compared to the value stored in this Address Compare Register.
Receive interrupts and RDA assertions only occur in the event of a match. See Table 75.

COMP_ADDR--Compare Address

This 8-bit value is compared to the incoming address bytes.

LIN-UART Baud Rate High and Low Byte Registers

The LIN-UART Baud Rate High and Low Byte registers, shown in Tables 76 and 77)
combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmis-
sion rate (baud rate) of the LIN-UART.

Table 75. LIN-UART Address Compare Register (U0ADDR)

BITS

FIELD

COMP_ADDR

RESET

00H

R/W

R/W

ADDR

F45H

Table 76. LIN-UART Baud Rate High Byte Register (U0BRH)

BITS

FIELD

BRH

RESET

FFH

R/W

R/W

ADDR

F46H

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141

The LIN-UART data rate is calculated using the following equation for standard UART
modes. For LIN protocol, the Baud Rate registers must be programmed with the baud
period rather than 1/16 baud period.

The UART must be disabled when updating the Baud Rate registers because the high and
low registers must be written independently.

The LIN-UART data rate is calculated using the following equation for standard UART
operation:

The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:

For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the
following equation for standard UART operation:

For a given LIN-UART data rate, the integer baud rate divisor value is calculated using the
following equation for LIN mode UART operation:

Table 77. LIN-UART Baud Rate Low Byte Register (U0BRL)

BITS

FIELD

BRL

RESET

FFH

R/W

R/W

ADDR

F47H

UART Data Rate (bits per second) =

System Clock Frequency (Hz)

16 x UART Baud Rate Divisor Value

UART Data Rate (bits per second) =

System Clock Frequency (Hz)

UART Baud Rate Divisor Value

Note:

UART Baud Rate Divisor Value (BRG)

Round

System Clock Frequency (Hz)

UART Data Rate (bits/s)

-------------------------------------------------------------------------------

UART Baud Rate Divisor Value (BRG)

Round

System Clock Frequency (Hz)

UART Data Rate (bits/s)

-------------------------------------------------------------------------------

LIN-UART

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The baud rate error relative to the appropriate baud rate is calculated using the following
equation:

For reliable communication, the LIN-UART baud rate error must never exceed 5 percent.
Tables 78 through 82 provide error data for popular baud rates and commonly-used crystal
oscillator frequencies for normal UART modes of operation.

Table 78. LIN-UART Baud Rates, 20.0 MHz System Clock

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

1250.0

0.00

9.60

130

9.62

0.16

625.0

0.00

4.80

260

4.81

0.16

250.0

0.00

2.40

521

2.399

�0.03

115.2

113.64

�1.19

1.20

1042

1.199

�0.03

57.6

56.82

�1.36

0.60

2083

0.60

0.02

38.4

37.88

�1.36

0.30

4167

0.299

�0.01

19.2

19.23

0.16

Table 79. LIN-UART Baud Rates, 10.0 MHz System Clock

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

1250.0

N/A

9.60

9.62

0.16

625.0

0.00

4.80

130

4.81

0.16

250.0

208.33

�16.67

2.40

260

2.40

�0.03

115.2

125.0

8.51

1.20

521

1.20

�0.03

57.6

56.8

�1.36

0.60

1042

0.60

�0.03

38.4

39.1

1.73

0.30

2083

0.30

0.2

19.2

18.9

0.16

UART Baud Rate Error (%)

100

Actual Data Rate Desired Data Rate

�

Desired Data Rate

----------------------------------------------------------------------------------------------------

�

PS024604-1005

P R E L I M I N A R Y

LIN-UART Baud Rate High and Low Byte

Z8FMC16100 Series Flash MCU

Product Specification

143

Table 80. LIN-UART Baud Rates, 5.5296 MHz System Clock

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

1250.0

N/A

9.60

0.00

625.0

N/A

4.80

0.00

250.0

345.6

38.24

2.40

144

2.40

0.00

115.2

0.00

1.20

288

1.20

0.00

57.6

0.00

0.60

576

0.60

0.00

38.4

0.00

0.30

1152

0.30

0.00

19.2

0.00

Table 81. LIN-UART Baud Rates, 3.579545 MHz System Clock

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

1250.0

N/A

9.60

9.73

1.32

625.0

N/A

4.80

4.76

�0.83

250.0

223.72

�10.51

2.40

2.41

0.23

115.2

111.9

�2.90

1.20

186

1.20

0.23

57.6

55.9

�2.90

0.60

373

0.60

�0.04

38.4

37.3

�2.90

0.30

746

0.30

�0.04

19.2

18.6

�2.90

Table 82. LIN-UART Baud Rates, 1.8432 MHz System Clock

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

Applicable

Rate (kHz)

BRG

Divisor

(Decimal)

Actual Rate

(kHz)

Error(

1250.0

N/A

9.60

0.00

625.0

N/A

4.80

0.00

250.0

N/A

2.40

0.00

115.2

0.00

1.20

0.00

PS024604-1005

P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

145

Infrared Encoder/Decoder

The Z8FMC16100 Series Flash MCU contains two fully-functional, high-performance
UART to Infrared Encoder/Decoders (endecs). Each infrared endec is integrated with an
on-chip UART to allow easy communication between the Z8FMC16100 Series Flash
MCU and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers.
Infrared communication provides secure, reliable, low-cost, point-to-point communication
between PCs, PDAs, cell phones, printers and other infrared enabled devices.

Architecture

Figure 19 illustrates the architecture of the infrared endec.

Operation

When the infrared endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver using the

TXD

pin. Likewise, data received from the infrared transceiver is

passed to the infrared endec using the

RXD

pin, decoded by the infrared endec, and passed

Figure 19. Infrared Data Communication System Block Diagram

Baud Rate

Clock

TxD

RxD

Data

I/O

Address

Interrupt

Signal

TxD

RxD

Infrared

Encoder/Decoder

(endec)

UART

System

Clock

TxD

RxD

ZiLOG

ZHX1810

Infrared

Transceiver

Infrared Encoder/Decoder

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to the UART. Communication is half-duplex, which means simultaneous data transmis-
sion and reception is not allowed.

The baud rate is set by the UART's Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the infrared endec. The infrared
endec data rate is calculated using the following equation:

Transmitting IrDA Data

The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART's transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
Low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is
output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is
output to complete the full 16-clock data period. Figure 20 illustrates IrDA data transmis-
sion. When the infrared endec is enabled, the UART's TXD signal is internal to the
Z8FMC16100 Series Flash MCU while the IR_TXD signal is output through the

TXD

pin.

Infrared Data Rate (bits/s) =

System Clock Frequency (Hz)

16 x UART Baud Rate Divisor Value

Figure 20. Infrared Data Transmission

16-Clock

Period

3-Clock

Pulse

7-Clock

Delay

Data Bit 0 = 1

Data Bit 1 = 0

Start Bit = 0

Data Bit 2 = 1

Data Bit 3 = 1

Baud Rate

Clock

UART's

TxD

IR_TxD

PS024604-1005

P R E L I M I N A R Y

Receiving IrDA Data

Z8FMC16100 Series Flash MCU

Product Specification

147

Receiving IrDA Data

Data received from the infrared transceiver via the IR_RXD

signal through the

RXD

pin is

decoded by the infrared endec and passed to the UART. The UART's baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 illustrates data recep-
tion. When the infrared endec is enabled, the UART's RXD signal is internal to the
Z8FMC16100 Series Flash MCU while the IR_RXD signal is received through the

RXD

pin.

The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.6 �s minimum-width pulses allowed by the IrDA standard.

Endec Receiver Synchronization

The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected) giving the endec a sampling window of
minus four baud rate clocks to plus eight baud rate clocks around the expected time of an

Figure 21. Infrared Data Reception

16-Clock

Period

16-Clock

Period

Start Bit = 0

Data Bit 0 = 1

Data Bit 1 = 0

Data Bit 2 = 1

Data Bit 3 = 1

Start Bit = 0

Data Bit 0 = 1

Data Bit 1 = 0

Data Bit 2 = 1

Data Bit 3 = 1

16-Clock

Period

16-Clock

Period

16-Clock

Period

Baud Rate

Clock

Min. 1.6 s

Pulse

8-Clock

Delay

UART's

RxD

IR_RxD

Caution:

Infrared Encoder/Decoder

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incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the endec clock
counter is reset, resynchronizing the endec to the incoming signal. This allows the endec
to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing the
endec does not alter the operation of the UART, which ultimately receives the data. The
UART is only synchronized to the incoming data stream when a Start bit is received.

Infrared Encoder/Decoder Control Register Definitions

All infrared endec configuration and status information is set by the UART control regis-
ters as defined in

LIN-UART Control Register Definitions

section on page 130.

To prevent spurious signals during IrDA data transmission, set the

IREN

bit in the UAR-

Tx Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling the
GPIO Port alternate function for the corresponding pin.

Caution:

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P R E L I M I N A R Y Operation

Z8FMC16100 Series Flash MCU

Product Specification

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Operation

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive, and slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator, and a control unit.

During an SPI transfer, data is sent and received simultaneously by both the master and the
slave SPI devices. Separate signals are required for data and the serial clock. When an SPI
transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and an
multibit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the master and another 8-bit shift register in the slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.

SPI Signals

The four basic SPI signals are:

�

Master-In, Slave-Out (MISO)

�

Master-Out, Slave-In (MOSI)

�

Serial Clock (SCK)

�

Slave Select (SS)

The following paragraphs discuss these SPI signals. Each signal is described in both
MASTER and SLAVE modes.

Master-In, Slave-Out

The Master-In, Slave-Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a slave device is placed in a high-impedance
state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.

Master-Out, Slave-In

The Master-Out, Slave-In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.

Serial Peripheral Interface

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Serial Clock

The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI's Baud Rate Generator cre-
ates the serial clock. The master drives the serial clock through its own serial clock (SCK)
pin to the slave's SCK pin. When the SPI is configured as a slave, the SCK pin is an input
and the clock signal from the master synchronizes the data transfer between the master and
slave devices. These slave devices ignore the SCK signal unless the SS pin is asserted.
When configured as a slave, the SPI block requires a minimum SCK period of greater than
or equal to 8 times the system (X

) clock period.

The master and slave are each capable of exchanging a character of data during a sequence
of

NUMBITS

clock cycles (refer to the

NUMBITS

field in the SPIMODE Register). In both

master and slave SPI devices, data is shifted on one edge of the SCK and is sampled on the
opposite edge, where data is stable. Edge polarity is determined by the SPI phase and
polarity control.

Slave Select

The active Low Slave Select (SS) input signal selects a slave SPI device. SS must be Low
prior to all data communication to and from the slave device. SS must remain Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters, or may deassert between each character.

When the SPI is configured as the only master in an SPI system, the SS pin can be set as
either an input or an output. For communication between the Z8 Encore!

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8K Series

device's SPI master and external slave devices, the SS signal, as an output, can assert the
SS input pin on one of the slave devices. Other GPIO output pins can also be employed to
select external SPI slave devices.

When the SPI is configured as one master in a multimaster SPI system, the SS pin should
be set as an input. The SS input signal on the master must be High. If the SS signal goes
Low (indicating that another master is driving the SPI bus), a collision error flag is set in
the SPI Status Register.

SPI Clock Phase and Polarity Control

The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control Register. The clock polarity bit,

CLKPOL

, selects an active High or active

Low clock and has no effect on the transfer format. Table 83 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit,

PHASE

, selects one of two fundamen-

tally different transfer formats. For proper data transmission, clock phase and polarity
must be identical for the SPI master and the SPI slave. The master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal) for the slave to
latch the data.

PS024604-1005

P R E L I M I N A R Y

SPI Clock Phase and Polarity Control

Z8FMC16100 Series Flash MCU

Product Specification

153

Transfer Format Phase Equals Zero

Figure 25 illustrates the timing diagram for an SPI transfer in which

PHASE

is cleared to 0.

The two SCK waveforms show polarity with

CLKPOL

reset to 0 and with

CLKPOL

set to

1. The diagram can be interpreted as either a master or slave timing diagram because the
SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly con-
nected between the master and the slave.

Table 83. SPI Clock Phase and Clock Polarity Operation

PHASE

CLKPOL

SCK Transmit

Edge

SCK Receive

Edge

SCK Idle

State

Falling

Rising

Low

Rising

Falling

High

Rising

Falling

Low

Falling

Rising

High

Figure 25. SPI Timing When Phase is 0

MOSI

SCK

(CLKPOL = 1)

SCK

(CLKPOL = 0)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MISO

Input Sample Time

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Serial Peripheral Interface

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Transfer Format Phase Equals One

Figure 26 illustrates the timing diagram for an SPI transfer in which

PHASE

is 1. Two

waveforms are depicted for SCK, one for

CLKPOL

reset to 0, and another for

CLKPOL

set

to 1.

Multimaster Operation

In a multimaster SPI system, all SCK pins are tied together, all MOSI pins are tied
together, and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any time, only one SPI device is con-
figured as the master and all other SPI devices on the bus are configured as slaves. The
master enables a single slave by asserting the SS pin on that slave only. Then, the single
master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the slaves
(including those which are not enabled). The enabled slave drives data out its MISO pin to
the MISO master pin.

For a master device operating in a multimaster system, if the SS pin is configured as an
input and is driven Low by another master, the

COL

bit is set to 1 in the SPI Status Regis-

ter. The

COL

bit indicates the occurrence of a multimaster collision (mode fault error con-

dition).

Figure 26. SPI Timing When Phase is 1

MOSI

SCK

(CLKPOL = 1)

SCK

(CLKPOL = 0)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MISO

Input Sample Time

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PS024604-1005

P R E L I M I N A R Y Slave

Operation

Z8FMC16100 Series Flash MCU

Product Specification

155

Slave Operation

The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The

IRQE

PHASE

CLKPOL

, and

WOR

bits in the SPICTL Register and the

NUM-

BITS

field in the SPIMODE Register must be set to be consistent with the other SPI

devices. The STR bit in the SPICTL Register can be used, if appropriate, to force a start-
up interrupt. The

BIRQ

bit in the SPICTL Register and the

SSV

bit in the SPIMODE Reg-

ister are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE
mode; therefore, the SPIBRH and SPIBRL registers do not require initialization.

If the slave contains data to send to the master, the data should be written to the SPIDAT
Register before the transaction starts (first edge of SCK when SS is asserted). If the SPI-
DAT Register is not written prior to the slave transaction, the MISO pin outputs the value
that is currently in the SPIDAT Register.

Due to the delay resulting from synchronization of the SPI input signals to the internal sys-
tem clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is the
system clock frequency (X

) divided by 8. This rate is controlled by the SPI master.

Error Detection

The SPI contains error detection logic that supports SPI communication protocols and rec-
ognizes when communication errors have occurred. The SPI Status Register indicates
when a data transmission error has been detected.

Overrun

An overrun error (write collision) indicates that a Write to the SPI Data Register was
attempted while a data transfer is in progress (in either MASTER or SLAVE modes). An
overrun sets the

OVR

bit in the SPI Status Register to 1. Writing a 1 to OVR clears this

error flag. The SPI Data Register is not altered when a Write occurs while a data transfer is
in progress.

Mode Fault

A mode fault indicates when more than one master is trying to communicate at the same
time (a multimaster collision). The mode fault is detected when the enabled master's SS
pin is asserted. A mode fault sets the

COL

bit in the SPI Status Register to 1. Writing a 1 to

COL

clears this error flag.

Slave Mode Abort

In SLAVE mode, if the SS pin deasserts before all bits in a character have been trans-
ferred, the transaction aborts. When this condition occurs, the

ABT

bit is set in the

SPISTAT Register as well as the

IRQ

bit (which indicates that the transaction is complete).

Serial Peripheral Interface

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The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previ-
ous transaction suspended. Writing a 1 to

ABT

clears this error flag.

SPI Interrupts

When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception is completed in both MASTER and SLAVE modes. A character can be
defined to be 1�8 bits by the

NUMBITS

field in the SPI Mode Register. In SLAVE mode, it

is not necessary for SS to deassert between characters to generate an interrupt. The SPI in
SLAVE mode can also generate an interrupt if the SS signal deasserts prior to transfer of
all the bits in a character (see description of slave abort error above). Writing a 1 to the

IRQ

bit in the SPI Status Register clears the pending SPI interrupt request. The

IRQ

bit

must be cleared to 0 by the interrupt service routine to generate future interrupts. To start
the transfer process, an SPI interrupt can be forced by software to write a 1 to the STR bit
in the SPICTL Register.

If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time-
out. This timer function must be enabled by setting the

BIRQ

bit in the SPICTL Register.

This Baud Rate Generator time-out does not set the

IRQ

bit in the SPISTAT Register, just

the SPI interrupt bit in the interrupt controller.

SPI Baud Rate Generator

In SPI MASTER mode, the Baud Rate Generator creates a lower-frequency serial clock
(SCK) for data transmission synchronization between the master and the external slave.
The input to the Baud Rate Generator is from the system clock. The SPI Baud Rate High
and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI
Baud Rate Generator. The SPI baud rate is calculated using the following equation:

Minimum baud rate is obtained by setting BRG[15:0] to

0000h

for a clock divisor value

of (2 x 65536 = 131072).

When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with an interrupt upon time-out. To configure the Baud Rate Generator as a timer with an
interrupt upon time-out, complete the following procedure:

1. Disable the SPI by clearing the

SPIEN

bit in the SPI Control Register to 0.

2. Load the appropriate 16-bit count value into the SPI Baud Rate High and Low Byte

registers.

3. Enable the Baud Rate Generator timer function and the associated interrupt by setting

the

BIRQ

bit in the SPI Control Register to 1.

SPI Baud Rate (bits/s) =

System Clock Frequency (Hz)

2 x BRG[15:0]

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P R E L I M I N A R Y

SPI Data Register

Z8FMC16100 Series Flash MCU

Product Specification

157

SPI Data Register

The SPI Data Register stores both the outgoing (transmit) data and the incoming (receive)
data. Reads from the SPI Data Register always return the current contents of the 8-bit shift
register. Data is shifted out starting with bit 7. The last bit received resides in bit position 0.

With the SPI configured as a master, writing a data byte to this register initiates data trans-
mission. With the SPI configured as a slave, writing a data byte to this register loads the
shift register in preparation for the next data transfer with the external master. In either
MASTER or SLAVE mode, if a transmission is already in progress, Writes to this register
are ignored and the overrun error flag,

OVR

, is set in the SPI Status Register.

When character length is less than 8 bits (as set by the

NUMBITS

field in the SPI Mode Reg-

ister), the transmit character must be left-justified in the SPI Data Register. A received char-
acter of less than 8 bits is right-justified (the final bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be written
to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0]. See Table 84.

DATA--Data

Transmit and/or receive data.

Table 84. SPI Data Register (SPIDATA)

BITS

FIELD

DATA

RESET

R/W

R/W

ADDR

F60H

Serial Peripheral Interface

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SPI Control Register

The SPI Control Register configures the SPI for transmit and receive operations.

IRQE--Interrupt Request Enable

0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.

1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.

STR--Start an SPI Interrupt Request

0 = No effect.

1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit

forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the
IRQ bit in the SPI Status register clears this bit to 0.
BIRQ--BRG Timer Interrupt Request

If the SPI is enabled, this bit has no effect. If the SPI is disabled:

0 = The Baud Rate Generator timer function is disabled.

1 = The Baud Rate Generator timer function and time-out interrupt are enabled.

PHASE--Phase Select

Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and
Polarity Control section for more information on operation of the PHASE bit.
CLKPOL--Clock Polarity

0 = SCK idles Low (0).

1 = SCK idle High (1).

WOR--Wire-OR (Open-Drain) Mode Enabled

0 = SPI signal pins not configured for open-drain.

1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.

MMEN--SPI MASTER Mode Enable

0 = SPI configured in SLAVE mode.

1 = SPI configured in MASTER mode.

Table 85. SPI Control Register (SPICTL)

BITS

FIELD

IRQE

STR

BIRQ

PHASE

CLKPOL

WOR

MMEN

SPIEN

RESET

00H

R/W

R/W

ADDR

F61H

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P R E L I M I N A R Y SPI

Status

Z8FMC16100 Series Flash MCU

Product Specification

159

SPIEN--SPI Enable

0 = SPI disabled.

1 = SPI enabled.

SPI Status Register

The SPI Status Register indicates the current state of the SPI. All bits revert to their reset
state if the SPIEN bit in the SPICTL Register = 0.

IRQ--Interrupt Request

If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.

0 = No SPI interrupt request pending.

1 = SPI interrupt request is pending.

OVR--Overrun

0 = An overrun error has not occurred.

1 = An overrun error has been detected.

COL--Collision

0 = A multi-master collision (mode fault) has not occurred.

1 = A multi-master collision (mode fault) has been detected.

ABT--SLAVE mode transaction abort

This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
pleted.

0 = A SLAVE mode transaction abort has not occurred.

1 = A SLAVE mode transaction abort has been detected.

Reserved--Must be 0.

Table 86. SPI Status Register (SPISTAT)

BITS

FIELD

IRQ

OVR

COL

ABT

Reserved

TXST

SLAS

RESET

R/W

R/W*

ADDR

F62H

R/W* = Read access. Write a 1 to clear the bit to 0.

Serial Peripheral Interface

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TXST--Transmit Status

0 = No data transmission currently in progress.

1 = Data transmission currently in progress.

SLAS--Slave Select

If SPI enabled as a Slave,

0 = SS input pin is asserted (Low)

1 = SS input is not asserted (High).

If SPI enabled as a Master, this bit is not applicable.

SPI Mode Register

The SPI Mode Register configures the character bit width and the direction and value of
the SS pin.

Reserved--Must be 0.

DIAG - Diagnostic Mode Control bit

This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL register locations.

0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers

1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPI-
BRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and
Low byte values are not buffered.

Exercise caution if reading the values while the BRG is counting.

NUMBITS[2:0]--Number of Data Bits Per Character to Transfer

This field contains the number of bits to shift for each character transfer. Refer to the SPI
Data Register description for information on valid bit positions when the character length
is less than 8-bits.

Table 87. SPI Mode Register (SPIMODE)

BITS

FIELD

Reserved

DIAG

NUMBITS[2:0]

SSIO

SSV

RESET

00H

R/W

R/W

ADDR

F63H

Caution:

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P R E L I M I N A R Y

SPI Diagnostic State Register

Z8FMC16100 Series Flash MCU

Product Specification

161

000 = 8 bits

001 = 1 bit

010 = 2 bits

011 = 3 bits

100 = 4 bits

101 = 5 bits

110 = 6 bits

111 = 7 bits

SSIO--Slave Select I/O

0 = SS pin configured as an input.

1 = SS pin configured as an output (MASTER mode only).

SSV--Slave Select Value

If SSIO = 1 and SPI configured as a Master:

0 = SS pin driven Low (0).

1 = SS pin driven High (1).

This bit has no effect if SSIO = 0 or SPI configured as a Slave

SPI Diagnostic State Register

The SPI Diagnostic State Register provides observability of internal state. It is a read-only
register used for SPI diagnostics. More detail about each bit follows the table.

SCKEN - Shift Clock Enable

0 = The internal Shift Clock Enable signal is deasserted

1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-
tem clock)

TCKEN - Transmit Clock Enable

0 = The internal Transmit Clock Enable signal is deasserted.

1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).

Table 88. SPI Diagnostic State Register (SPIDST)

BITS

FIELD

SCKEN

TCKEN

SPISTATE

RESET

00H

R/W

ADDR

F64H

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SPISTATE - SPI State Machine

Defines the current state of the internal SPI State Machine.

SPI Baud Rate High and Low Byte Registers

The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value,
BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the
following equation:

Minimum baud rate is obtained by setting BRG[15:0] to

0000h

for a clock divisor value

of (2 X 65536 = 131072).

BRH = SPI Baud Rate High Byte

Most significant byte, BRG[15:8], of the SPI Baud Rate Generator's reload value.

BRL = SPI Baud Rate Low Byte

Least significant byte, BRG[7:0], of the SPI Baud Rate Generator's reload value.

SPI Baud Rate (bits/s) =

System Clock Frequency (Hz)

2 x BRG[15:0]

Table 89. SPI Baud Rate High Byte Register (SPIBRH)

BITS

FIELD

BRH

RESET

FFH

R/W

R/W

ADDR

F66H

Table 90. SPI Baud Rate Low Byte Register (SPIBRL)

BITS

FIELD

BRL

RESET

FFH

R/W

R/W

ADDR

F67H

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P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

163

C Master/Slave Controller

The I

C Master/Slave Controller ensures that the Z8FMC16100 Series Flash MCU

devices are bus-compatible with the I

C protocol. The I

C bus consists of the serial data

signal (SDA) and a serial clock signal (SCL) bidirectional lines. Features of the I

C con-

troller include:

�

Operates in MASTER/SLAVE or SLAVE ONLY modes

�

Supports arbitration in a multimaster environment (MASTER/SLAVE mode)

�

Supports data rates up to 400 Kbps

�

7- or 10-bit slave address recognition (interrupt only on address match)

�

Optional general call address recognition

�

Optional digital filter on receive SDA, SCL lines

�

Optional interactive receive mode allows software interpretation of each received ad-
dress and/or data byte before acknowledging

�

Unrestricted number of data bytes per transfer

�

Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I

controller is disabled.

Architecture

Figure 27 illustrates the architecture of the I

C controller.

PS024604-1005

P R E L I M I N A R Y I2C

Master/Slave Controller Registers

Z8FMC16100 Series Flash MCU

Product Specification

165

C Master/Slave Controller Registers

Table 91 summarizes the I

C master/slave controller's software-accessible registers.

Comparison with the Master Mode Only I

C Controller

Porting code written for the MASTER ONLY I

C controller found on other Z8 Encore!

�

parts to the I

C Master/Slave Controller is straightforward. The I2CDATA, I2CCTL,

I2CBRH and I2CBRL Register definitions have not changed. The following bullets high-
light the differences between these two designs.

�

The Status (I2CSTATE) Register from the MASTER ONLY I

C controller is split into

the Interrupt Status (I2CISTAT) Register and the State (I2CSTATE) Register because
more interrupt sources are available. The

ACK

10B

TAS

(now called

), and

DSS

(now called

) bits, formerly part of the Status Register, are now part of the State Reg-

ister.

�

The I2CSTATE Register was called the Diagnostic State (I2CDST) Register in the
MASTER-mode-only version. The I2CDST Register provided diagnostic information.
The I2CSTATE Register contains status and state information that may be useful to
software in an operational mode.

�

The I2CMODE Register was called the Diagnostic Control (I2CDIAG) Register in the
MASTER-mode-only version. The I2CMODE Register provides control for the
SLAVE modes of operation, as well as the most significant two bits of the 10-bit slave
address.

Table 91. I

C Master/Slave Controller Registers

Name

Abbreviation Description

C Data

I2CDATA

Transmit/receive data register.

C Interrupt Status I2CISTAT

Interrupt status register.

C Control

I2CCTL

Control register--basic control functions.

C Baud Rate High I2CBRH

High byte of baud rate generator initialization
value.

C Baud Rate Low I2CBRL

Low byte of baud rate generator initialization
value.

C State

I2CSTATE

State register.

C Mode

I2CMODE

Selects MASTER or SLAVE modes, 7- or 10-bit
addressing; configure address recognition, define
slave address bits [9:8].

C Slave Address

I2CSLVAD

Defines slave address bits [7:0].

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�

The I2CSLVAD Register is added to provide programming capabilities for the slave
address.

�

The ACKV bit in the I2CSTATE Register enables the master to check the Acknowl-
edge from the slave before sending the next byte.

�

Support for multimaster environments--if arbitration is lost when operating as a mas-
ter, the ARBLST bit in the I2CISTAT Register is set and the mode automatically
switches to SLAVE mode.

Operation

The I

C Master/Slave Controller operates in MASTER/SLAVE mode, SLAVE ONLY

mode, or with master arbitration. In MASTER/SLAVE mode, it can be used as the only
master on the bus or as one of several masters on the bus, with arbitration. In a multimaster
environment, the controller switches from MASTER to SLAVE mode upon losing arbitra-
tion.

Though slave operation is fully supported in MASTER/SLAVE mode, if a device is
intended to operate only as a slave, then SLAVE ONLY mode can be selected. In SLAVE
ONLY mode, the device will not initiate a transaction, even if the software inadvertently
sets the START bit.

SDA and SCL Signals

The I

C circuit sends all addresses, data, and Acknowledge signals over the SDA line,

most-significant bit first. SCL is the clock for the I

C bus. When the SDA and SCL pin

alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.

The master is responsible for driving the SCL clock signal. During the Low period of the
clock, a slave can hold the SCL signal Low to suspend the transaction if it is not ready to
proceed. The master releases the clock at the end of the Low period and notices that the
clock remains Low instead of returning to a High level. When the slave releases the clock,
the I

C master continues the transaction. All data is transferred in bytes; there is no limit to

the amount of data transferred in one operation. When transmitting address, data, or an
Acknowledge, the SDA signal changes in the middle of the Low period of SCL

When

receiving address, Data or an Acknowledge, the SDA signal is sampled in the middle of
the High period of SCL.

A low-pass digital filter can be applied to the SDA and SCL receive signals by setting the
Filter Enable (

FILTEN

) bit in the I

C Control Register. When the filter is enabled, any

glitch that is less than a system clock period in width will be rejected. This filter should be
enabled when running in I

C FAST mode (400 kbps), and can also be used at lower data

rates.

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P R E L I M I N A R Y I

C Interrupts

Z8FMC16100 Series Flash MCU

Product Specification

167

C Interrupts

The I

C controller contains multiple interrupt sources that are combined into one interrupt

request signal to the interrupt controller. If the I

C controller is enabled, the source of the

interrupt is determined by which bits are set in the I2CISTAT Register. If the I

C control-

ler is disabled, the BRG controller can be used to generate general-purpose timer inter-
rupts.

Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the data register.

Transmit Interrupts

Transmit interrupts (

TDRE

bit = 1 in I2CISTAT) occur under the following conditions, both

of which must be true.

�

The transmit data register is empty and the

TXI

bit = 1 in the I

C Control Register

�

The I

C controller is enabled, with one of the following:

�

The first bit of a 10-bit address is shifted out

�

The first bit of the final byte of an address is shifted out and the

bit is deas-

serted

�

The first bit of a data byte is shifted out

Writing to the I

C Data Register always clears the

TRDE

bit to 0.

Receive Interrupts

Receive interrupts (

RDRF

bit = 1 in I2CISTAT) occur when a byte of data has been

received by the I

C controller. The

RDRF

bit is cleared by reading from the I

C Data Reg-

ister. If the RDRF interrupt is not serviced prior to the completion of the next Receive
byte, the I

C controller holds SCL Low during the final data bit of the next byte until

RDRF

is cleared, to prevent receive overruns. A receive interrupt does not occur when a

slave receives an address byte or for data bytes following a slave address that did not
match. An exception is if the Interactive Receive Mode (

IRM

) bit is set in the I2CMODE

Slave Address Match Interrupts

Slave address match interrupts (

SAM

bit = 1 in I2CISTAT) occur when the I

C controller is

in SLAVE mode and an address is received that matches the unique slave address. The
General Call Address (

0000_0000

) and STARTBYTE (

0000_0001

) are recognized if the

GCE

bit = 1 in the I2CMODE Register. The software checks the

bit in the I2CISTAT

Register to determine if the transaction is a Read or Write transaction. The General Call
Address and STARTBYTE address are also distinguished by the

bit. The General Call

I2C Master/Slave Controller

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Address (

GCA

) bit of the I2CISTAT Register indicates whether the address match occurred

on the unique slave address or the General Call/STARTBYTE address. The

SAM

bit clears

automatically when the I2CISTAT Register is read.

If configured via the

MODE[1:0]

field of the I

C Mode Register for 7-bit slave address-

ing, the most significant 7 bits of the first byte of the transaction are compared against the

SLA[6:0]

bits of the Slave Address Register. If configured for 10-bit slave addressing,

the first byte of the transaction is compared against {

11110

SLA[9:8]

,R/W} and the sec-

ond byte is compared against

SLA[7:0]

Arbitration Lost Interrupts

Arbitration Lost interrupts (

ARBLST

bit = 1 in I2CISTAT) occur when the I

C controller is

in MASTER mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).
The I

C controller switches to SLAVE mode when this instance occurs. This bit clears

automatically when the I2CISTAT Register is read.

Stop/Restart Interrupts

A Stop/Restart event interrupt (

SPRS

bit = 1 in I2CISTAT) occurs when the I

C controller

is in SLAVE mode and a

STOP

RESTART

condition is received, indicating the end of the

transaction. The

RSTR

bit in the I2C State Register indicates whether the bit was set due to

STOP

RESTART

condition. When a restart occurs, a new transaction by the same mas-

ter is expected to follow. This bit is cleared automatically when the I2CISTAT Register is
read. The STOP/RESTART interrupt only occurs on a selected (address match) slave.

Not Acknowledge Interrupts

Not Acknowledge interrupts (

NCKI

bit = 1 in I2CISTAT) occur in MASTER mode when a

Not Acknowledge is received or sent by the I

C controller and the

START

STOP

bit is

not set in the I

C Control Register. In MASTER mode, the Not Acknowledge interrupt

clears by setting the

START

STOP

bit. When this interrupt occurs in MASTER mode,

the I

C controller waits until it is cleared before performing any action. In SLAVE mode,

the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to
data sent. The

NCKI

bit clears in SLAVE mode when software reads the I2CISTAT Regis-

ter.

General Purpose Timer Interrupt from Baud Rate Generator

If the I

C controller is disabled (

IEN

bit in the I2CCTL Register = 0) and the

BIRQ

bit in

the I2CCTL Register = 1, an interrupt is generated when the baud rate generator (BRG)
counts down to 1. The baud rate generator reloads and continues counting, providing a
periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in
the I

C controller to be used as a general-purpose timer when the I

C controller is dis-

abled.

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Start and Stop Conditions

Z8FMC16100 Series Flash MCU

Product Specification

169

Start and Stop Conditions

The master generates the START and STOP conditions to start or end a transaction. To
start a transaction, the I

C controller generates a

START

condition by pulling the SDA sig-

nal Low while SCL is High. To complete a transaction, the I

C controller generates a

STOP

condition by creating a Low-to-High transition of the SDA signal while the SCL

signal is High. These START

and STOP events occur when the

START

and

STOP

bits in

the I

C Control Register are written by software to begin or end a transaction. Any byte

transfer currently under way, including the Acknowledge phase, finishes before the
START or

STOP

condition occurs.

Software Control of I

C Transactions

The I

C controller is configured via the I

C Control and I

C Mode registers. The

MODE[1:0]

field of the I

C Mode Register allows the configuration of the I

C controller

for MASTER/SLAVE or SLAVE ONLY mode, and configures the slave for 7- or 10-bit
addressing recognition.

MASTER/SLAVE mode can be used for:

�

MASTER ONLY operation in a single master/one or more slave I

C system

�

MASTER/SLAVE in a multimaster/multislave I

C system

�

SLAVE ONLY operation in an I

C system

In SLAVE ONLY mode, the START bit of the I

C Control Register is ignored (software

cannot initiate a master transaction by accident), and operation to SLAVE ONLY mode is
restricted, thereby preventing accidental operation in MASTER mode.

The software can control I

C transactions by enabling the I

C controller interrupt in the

interrupt controller or by polling the I

C Status Register.

To use interrupts, the I

C interrupt must be enabled in the interrupt controller and followed

by executing an EI instruction. The

TXI

bit in the I

C Control Register must be set to

enable transmit interrupts. An I

C interrupt service routine then checks the I

C Status

To control transactions by polling, the

TDRE

RDRF

SAM

ARBLST

SPRS

, and

NCKI

inter-

rupt bits in the I

C Status Register should be polled. The

TDRE

bit asserts regardless of the

state of the

TXI

bit.

Master Transactions

The following sections describe master Read and Write transactions to both 7- and 10-bit
slaves.

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Master Arbitration

If a master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a slave. If a master
loses arbitration during the transmission of a data byte, it releases the SDA line and waits
for the next

STOP

START

condition.

The master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one master is simultaneously
accessing the bus. Loss of arbitration can occur during the address phase (two or more
masters accessing different slaves) or during the data phase, when the masters are attempt-
ing to write different data to the same slave.

When a master loses arbitration, the software is informed by means of the Arbitration Lost
interrupt. The software can repeat the same transaction at a later time.

A special case can occur when a slave transaction starts just before the software attempts
to start a new master transaction by setting the

START

bit. In this case, the state machine

enters its slave states before the

START

bit is set, and as a result, the I

C controller will not

arbitrate. If a slave address match occurs and the I

C controller receives/transmits data, the

START

bit is cleared and an Arbitration Lost interrupt is asserted. The software can mini-

mize the chance of this instance occurring by checking the

BUSY

bit in the I2CSTATE

Register before initiating a master transaction. If a slave address match does not occur, the
Arbitration Lost interrupt will not occur, and the

START

bit will not be cleared. The I

controller will initiate the master transaction after the I

C bus is no longer busy.

Master Address-Only Transactions

It is sometimes preferable to perform an address-only transaction to determine if a particu-
lar slave device is able to respond. This transaction can be performed by monitoring the

ACKV

bit in the I2CSTATE Register after the address has been written to the I2CDATA

START

bit has been set. After the

ACKV

bit is set, the

ACK

bit in the

I2CSTATE Register determines if the slave is able to communicate. The

STOP

bit must be

set in the I2CCTL Register to terminate the transaction without transferring data. For a 10-
bit slave address, if the first address byte is acknowledged, the second address byte should
also be sent to determine if the preferred slave is responding.

Another approach is to set both the

STOP

and

START

bits (for sending a 7-bit address).

After both bits have cleared (7-bit address has been sent and transaction is complete), the

ACK

bit can be read to determine if the slave has acknowledged. For a 10-bit slave, set the

STOP

bit after the second TDRE interrupt (which indicates that the second address byte is

being sent).

Master Transaction Diagrams

In the following transaction diagrams, the shaded regions indicate the data that is trans-
ferred from the master to the slave, and the unshaded regions indicate the data that is trans-
ferred from the slave to the master. The transaction field labels are defined as follows:

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P R E L I M I N A R Y Master

Transactions

Z8FMC16100 Series Flash MCU

Product Specification

171

Master Write Transaction with a 7-Bit Address

Figure 28 illustrates the data transfer format from a master to a 7-bit addressed slave

The procedure for a master transmit operation to a 7-bit addressed slave is as follows:

1. The software initializes the

MODE

field in the I

C Mode Register for MASTER/

SLAVE mode with either a 7- or 10-bit slave address. The

MODE

field selects the

address width for this mode when addressed as a slave (but not for the remote slave).
The software asserts the

IEN

bit in the I

C Control Register.

2. The software asserts the

TXI

bit of the I

C Control Register to enable transmit inter-

rupts.

3. The I

C interrupt asserts, because the I

C Data Register is empty.

4. The software responds to the

TDRE

bit by writing a 7-bit slave address plus the Write

bit (which is cleared to 0) to the I

C Data Register.

5. The software sets the

START

bit of the I

C Control Register.

6. The I

C controller sends a

START

condition to the I

C slave.

7. The I

C controller loads the I

C Shift Register with the contents of the I

C Data Reg-

ister.

8. After one bit of the address has been shifted out by the SDA signal, the transmit inter-

rupt asserts.

9. The software responds by writing the transmit data into the I

C Data Register.

10. The I

C controller shifts the remainder of the address and the Write bit out via the

SDA signal.

11. The I

C slave sends an Acknowledge (by pulling the SDA signal Low) during the next

high period of SCL. The I

C controller sets the

ACK

bit in the I

C Status Register.

Start

Write

Acknowledge

Not Acknowledge

Stop

Slave

Address

W = 0

Data

A/A

P/S

Figure 28. Data Transfer Format--Master Write Transaction with a 7-Bit Address

I2C Master/Slave Controller

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If the slave does not acknowledge the address byte, the I

C controller sets the

NCKI

bit in the I

C Status Register, sets the

ACKV

bit, and clears the

ACK

bit in the I

C State

STOP

bit and clearing the

TXI

bit. The I

C controller flushes the Transmit Data Register,

sends a

STOP

condition on the bus, and clears the

STOP

and

NCKI

bits. The transaction

is complete, and the following steps can be ignored.

12. The I

C controller loads the contents of the I

C Shift Register with the contents of the

C Data Register.

13. The I

C controller shifts the data out via the SDA signal. After the first bit is sent, the

transmit interrupt asserts.

14. If more bytes remain to be sent, return to Step 9.

15. When there is no more data to be sent, the software responds by setting the

STOP

bit of

the I

C Control Register (or the

START

bit to initiate a new transaction).

16. If no additional transaction is queued by the master, the software can clear the

TXI

bit

of the I

C Control Register.

17. The I

C controller completes transmission of the data on the SDA signal.

18. The I

C controller sends a

STOP

condition to the I

C bus.

If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I

C controller asserts the

NCKI

interrupt and halts. The software must ter-

minate the transaction by setting either the

STOP

bit (end transaction) or the

START

bit

(end this transaction, start a new one). In this case, it is not necessary for software to set
the

FLUSH

bit of the I2CCTL Register to flush the data that was previously written but not

transmitted. The I

C controller hardware automatically flushes transmit data in this not

acknowledge case.

Master Write Transaction with a 10-Bit Address

Figure 29 illustrates the data transfer format from a master to a 10-bit addressed slave.

The first seven bits transmitted in the first byte are

11110XX

. The two

bits are the two

most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.

The procedure for a master transmit operation to a 10-bit addressed slave is as follows:

Slave Address

1st Byte

W=0

Slave Address

2nd Byte

Data

A/A

F/S

Figure 29. Data Transfer Format--Master Write Transaction with a 10-Bit Address

Note:

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1. The software initializes the

MODE

field in the I

C Mode Register for MASTER/

SLAVE mode with 7- or 10-bit addressing (the I

C bus protocol allows the mixing of

slave address types). The

MODE

field selects the address width for this mode when

addressed as a slave (but not for the remote slave). The software asserts the

IEN

bit in

the I

C Control Register.

2. The software asserts the

TXI

bit of the I

C Control Register to enable transmit inter-

rupts.

3. The I

C interrupt asserts because the I

C Data Register is empty.

4. The software responds to the

TDRE

interrupt by writing the first slave address byte

(

11110xx0

). The least-significant bit must be 0 for the write operation.

5. The software asserts the

START

bit of the I

C Control Register.

6. The I

C controller sends a

START

condition to the I

C slave.

7. The I

C controller loads the I

C Shift Register with the contents of the I

C Data Reg-

ister.

8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt

asserts.

9. The software responds by writing the second byte of address into the contents of the

C Data Register.

10. The I

C controller shifts the remainder of the first byte of the address and the Write bit

out via the SDA signal.

11. The I

C slave sends an Acknowledge by pulling the SDA signal Low during the next

high period of SCL. The I

C controller sets the

ACK

bit in the I

C Status Register.

If the slave does not acknowledge the first address byte, the I

C controller sets the

NCKI

bit in the I

C Status Register, sets the

ACKV

bit, and clears the

ACK

bit in the I

State Register. The software responds to the Not Acknowledge interrupt by setting the

STOP

bit and clearing the

TXI

bit. The I

C controller flushes the second address byte

from the data register, sends a

STOP

condition on the bus, and clears the

STOP

and

NCKI

bits. The transaction is complete, and the following steps can be ignored.

12. The I

C controller loads the I

C Shift Register with the contents of the I

C Data Reg-

ister (2nd address byte).

13. The I

C controller shifts the second address byte out via the SDA signal. After the

first bit has been sent, the transmit interrupt asserts.

14. The software responds by writing the data to be written out to the I

C Control Regis-

ter.

15. The I

C controller shifts out the remainder of the second byte of the slave address (or

ensuing data bytes, if looping) via the SDA signal.

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16. The I

C slave sends an Acknowledge by pulling the SDA signal Low during the next

high period of SCL. The I

C controller sets the

ACK

bit in the I

C Status Register.

If the slave does not acknowledge, refer to the second paragraph of Step 11.

17. The I

C controller shifts the data out by the SDA signal. After the first bit is sent, the

transmit interrupt asserts.

18. If more bytes remain to be sent, return to Step 14.

19. The software responds by asserting the

STOP

bit of the I

C Control Register.

20. The I

C controller completes transmission of the data on the SDA signal.

21. The I

C controller sends a

STOP

condition to the I

C bus.

If the slave responds with a Not Acknowledge during the transfer, the I

C controller

asserts the

NCKI

bit, sets the

ACKV

bit, clears the

ACK

bit in the I

C State Register, and

halts. The software terminates the transaction by setting either the

STOP

bit (end transac-

tion) or the

START

bit (end this transaction, start a new one). The Transmit Data Register

is flushed automatically.

Master Read Transaction with a 7-Bit Address

Figure 30 illustrates the data transfer format for a read operation to a 7-bit addressed slave.

The procedure for a master Read operation to a 7-bit addressed slave is as follows:

1. The software initializes the

MODE

field in the I

C Mode Register for MASTER/

SLAVE mode with 7- or 10-bit addressing (the I

C bus protocol allows the mixing of

slave address types). The

MODE

field selects the address width for this mode when

addressed as a slave (but not for the remote slave). The software asserts the

IEN

bit in

the I

C Control Register.

2. The software writes the I

C Data Register with a 7-bit slave address, plus the Read bit

(which is set to 1).

3. The software asserts the

START

bit of the I

C Control Register.

4. If this operation is a single-byte transfer, the software asserts the

NAK

bit of the I

Control Register so that after the first byte of data has been read by the I

C controller,

a Not Acknowledge instruction is sent to the I

C slave.

5. The I

C controller sends a

START

condition.

6. The I

C controller sends the address and Read bit out via the SDA signal.

Slave Address

R = 1

Data

P/S

Figure 30. Data Transfer Format--Master Read Transaction with a 7-Bit Address

Note:

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7. The I

C slave acknowledges the address by pulling the SDA signal Low during the

next high period of SCL.

If the slave does not acknowledge the address byte, the I

C controller sets the

NCKI

bit in the I

C Status Register, sets the

ACKV

bit, and clears the

ACK

bit in the I

C State

STOP

bit and clearing the

TXI

bit. The I

C controller flushes the Transmit Data Register,

sends a

STOP

condition on the bus, and clears the

STOP

and

NCKI

bits. The transaction

is complete, and the following steps can be ignored.

8. The I

C controller shifts in the first byte of data from the I

C slave on the SDA signal.

9. The I

C controller asserts the receive interrupt.

10. The software responds by reading the I

C Data Register. If the next data byte is to be

the final byte, the software must set the

NAK

bit of the I

C Control Register.

11. The I

C controller sends a Not Acknowledge to the I

C slave if the next byte is the

final byte; otherwise, it sends an Acknowledge.

12. If there are more bytes to transfer, the I

C controller returns to Step 7.

13. A NAK interrupt (

NCKI

bit in I2CISTAT) is generated by the I

C controller.

14. The software responds by setting the

STOP

bit of the I

C Control Register.

15. A

STOP

condition is sent to the I

C slave.

Master Read Transaction with a 10-Bit Address

Figure 31 illustrates the read transaction format for a 10-bit addressed slave.

The first seven bits transmitted in the first byte are

11110XX

. The two

bits are the two

most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.

The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:

1. The software initializes the

MODE

field in the I

C Mode Register for MASTER/

SLAVE mode with 7- or 10-bit addressing (the I

C bus protocol allows the mixing of

slave address types). The

MODE

field selects the address width for this mode when

addressed as a slave (but not for the remote slave). The software asserts the

IEN

bit in

the I

C Control Register.

2. The software writes

11110b

, followed by the two most-significant address bits and a

0 (write) to the I

C Data Register.

Slave Address

1st Byte

W=0 A Slave Address

2nd Byte

A S Slave Address

1st Byte

R=1 A

Data A

Data

A P

Figure 31. Data Transfer Format--Master Read Transaction with a 10-Bit Address

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3. The software asserts the

START

bit of the I

C Control Register.

4. The I

C controller sends a

START

condition.

5. The I

C controller loads the I

C Shift Register with the contents of the I

C Data Reg-

ister.

6. After the first bit has been shifted out, a transmit interrupt is asserted.

7. The software responds by writing the least significant eight bits of address to the I

Data Register.

8. The I

C controller completes shifting of the first address byte.

9. The I

C slave sends an Acknowledge by pulling the SDA signal Low during the next

high period of SCL.

If the slave does not acknowledge the address byte, the I

C controller sets the

NCKI

bit in the I

C Status Register, sets the

ACKV

bit and clears the

ACK

bit in the I

C State

STOP

bit and clearing the

TXI

bit. The I

C controller flushes the Transmit Data Register,

sends the

STOP

condition on the bus and clears the

STOP

and

NCKI

bits. The transac-

tion is complete, and the following steps can be ignored.

10. The I

C controller loads the I

C Shift Register with the contents of the I

C Data Reg-

ister (the lower byte of the 10-bit address).

11. The I

C controller shifts out the next eight bits of the address. After the first bit shifts,

the I

C controller generates a transmit interrupt.

12. The software responds by setting the

START

bit of the I

C Control Register to generate

a repeated

START

condition.

13. The software writes

11110b

, followed by the 2-bit slave address and a 1 (Read) to the

C Data Register.

14. If the user chooses to read only one byte, the software responds by setting the

NAK

bit

of the I

C Control Register.

15. After the I

C controller shifts out the address bits listed in Step 9 (the second address

transfer), the I

C slave sends an Acknowledge by pulling the SDA signal Low during

the next High period of SCL.

If the slave does not acknowledge the address byte, the I

C controller sets the

NCKI

bit in the I

C Status Register, sets the

ACKV

bit, and clears the

ACK

bit in the I

C State

STOP

bit and clearing the

TXI

bit. The I

C controller flushes the Transmit Data Register,

sends the

STOP

condition on the bus, and clears the

STOP

and

NCKI

bits. The transac-

tion is complete, and the following steps can be ignored.

16. The I

C controller sends a repeated

START

condition.

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17. The I

C controller loads the I

C Shift Register with the contents of the I

C Data Reg-

ister (the third address transfer).

18. The I

C controller sends

11110b

, followed by the two most-significant bits of the

slave read address and a 1 (Read).

19. The I

C slave sends an Acknowledge by pulling the SDA signal Low during the next

High period of SCL.

20. The I

C controller shifts in a byte of data from the slave.

21. The I

C controller asserts the Receive interrupt.

22. The software responds by reading the I

C Data Register. If the next data byte is to be

the final byte, the software must set the

NAK

bit of the I

C Control Register.

23. The I

C controller sends an Acknowledge or Not Acknowledge to the I

C slave, based

on the value of the

NAK

bit.

24. If there are more bytes to transfer, the I

C controller returns to Step 18.

25. The I

C controller generates a NAK interrupt (the

NCKI

bit in the I2CISTAT Regis-

ter).

26. The software responds by setting the

STOP

bit of the I

C Control Register.

27. A

STOP

condition is sent to the I

C slave.

Slave Transactions

The following sections describe Read and Write transactions to the I

C controller config-

ured for 7- and 10-bit slave modes.

Slave Address Recognition

The following slave address recognition options are supported.

Slave 7-Bit Address Recognition Mode.

IRM

= 0 during the address phase and the

controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the hard-
ware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and
generates the slave address match interrupt (

the

SAM

bit = 1 in the I2CISTAT Register).

The I

C controller automatically responds during the Acknowledge phase with the value

in the

NAK

bit of the I2CCTL Register.

Slave 10-Bit Address Recognition Mode.

IRM

= 0 during the address phase and the

controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hard-
ware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD
registers and generates the slave address match interrupt (the

SAM

bit = 1 in the I2CISTAT

C controller automatically responds during the Acknowledge phase with

the value in the

NAK

bit of the I2CCTL Register.

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General Call and Start Byte Address Recognition.

GCE

= 1 and

IRM

= 0 during the

address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either
7- or 10-bit address modes, the hardware detects a match to the General Call Address or
the START byte and generates the slave address match interrupt. A General Call Address
is a 7-bit address of all 0's with the R/W bit = 0. A START byte is a 7-bit address of all 0's
with the R/W bit = 1. The

SAM

and

GCA

bits are set in the I2CISTAT Register. The

bit in

the I2CISTAT Register distinguishes a General Call Address from a START byte which is
cleared to 0 for a General Call Address). For a General Call Address, the I

C controller

automatically responds during the address acknowledge phase with the value in the

NAK

bit of the I2CCTL Register. If the software is set to process the data bytes associated with
the

GCA

bit, the

IRM

bit can optionally be set following the

SAM

interrupt to allow the soft-

ware to examine each received data byte before deciding to set or clear the

NAK

bit.

A START byte will not be acknowledged--a requirement of the I

C specification.

Software Address Recognition.

To disable hardware address recognition, the

IRM

bit

must be set to 1 prior to the reception of the address byte(s). When

IRM

= 1, each received

byte generates a receive interrupt (

RDRF

= 1 in the I2CISTAT Register). The software must

examine each byte and determine whether to set or clear the

NAK

bit. The slave holds SCL

Low during the Acknowledge phase until the software responds by writing to the I2CCTL
Register. The value written to the

NAK

bit is used by the controller to drive the I

C bus,

then releasing the SCL. The

SAM

and

GCA

bits are not set when

IRM

= 1 during the address

phase, but the

bit is updated based on the first address byte.

Slave Transaction Diagrams

In the following transaction diagrams, the shaded regions indicate data transferred from
the master to the slave, and the unshaded regions indicate the data transferred from the
slave to the master. The transaction field labels are defined as follows:

Slave Receive Transaction with 7-Bit Address

The data transfer format for writing data from a master to a slave in 7-bit address mode is
shown in Figure 32. The procedure that follows describes the I

C Master/Slave Controller

operating as a slave in 7-bit addressing mode and receiving data from the bus master.

Start

Write

Acknowledge

Not Acknowledge

Stop

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1. The software configures the controller for operation as a slave in 7-bit addressing

mode, as follows.
a. Initialize the

MODE

field in the I

C Mode Register for either SLAVE ONLY mode

or MASTER/SLAVE mode with 7-bit addressing.

b. Optionally set the

GCE

bit.

c. Initialize the

SLA[6:0]

bits in the I

C Slave Address Register.

d. Set

IEN

= 1 in the I

C Control Register. Set

NAK

= 0 in the I

C Control Register.

2. The bus master initiates a transfer, sending the address byte. In SLAVE mode, the I

controller recognizes its own address and detects that the R/W bit = 0 (written from
the master to the slave). The I

C controller acknowledges, indicating it is available to

accept the transaction. The

SAM

bit in the I2CISTAT Register is set to 1, causing an

interrupt. The

bit in the I2CISTAT Register is cleared to 0, indicating a Write to the

slave. The I

C controller holds the SCL signal Low, waiting for the software to load

the first data byte.

3. The software responds to the interrupt by reading the I2CISTAT Register (which

clears the

SAM

bit). After seeing the

SAM

bit to 1, the software checks the

bit.

Because

= 0, no immediate action is required until the first byte of data is received.

If software is only able to accept a single byte it sets the

NAK

bit in the I2CCTL Regis-

ter at this time.

4. The master detects the Acknowledge and sends the byte of data.

5. The I

C controller receives the data byte and responds with Acknowledge or Not

Acknowledge depending on the state of the

NAK

bit in the I2CCTL Register. The I

controller generates the receive data interrupt by setting the

RDRF

bit in the I2CISTAT

6. The software responds by reading the I2CISTAT Register, finding the

RDRF

bit = 1

and reading the I2CDATA Register clearing the

RDRF

bit. If software can accept only

one more data byte it sets the

NAK

bit in the I2CCTL Register.

7. The master and slave loops through steps 4 to 6 until the master detects a Not

Acknowledge instruction or runs out of data to send.

8. The master sends the

STOP

RESTART

signal on the bus. Either of these signals can

cause the I

C controller to assert a STOP interrupt (the

STOP

bit = 1 in the I2CISTAT

Register). Because the slave received data from the master, the software takes no
action in response to the STOP interrupt other than reading the I2CISTAT Register to
clear the

STOP

bit in the I2CISTAT Register.

Slave Address

W=0

Data

A/A

P/S

Figure 32. Data Transfer Format--Slave Receive Transaction with 7-Bit Address

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Slave Receive Transaction with 10-Bit Address

The data transfer format for writing data from a master to a slave with 10-bit addressing is
shown in Figure 33. The procedure that follows describes the I

C Master/Slave Controller

operating as a slave in 10-bit addressing mode and receiving data from the bus master.

1. The software configures the controller for operation as a slave in 10-bit addressing

mode, as follows.
a. Initialize the

MODE

field in the I2CMODE Register for either SLAVE ONLY

mode or MASTER/SLAVE mode with 10-bit addressing.

b. Optionally set the

GCE

bit.

c. Initialize the

SLA[7:0]

bits in the I2CSLVAD Register and the

SLA[9:8]

bits in

the I2CMODE Register.

d. Set

IEN

= 1 in the I2CCTL Register. Set

NAK

= 0 in the I

C Control Register.

2. The master initiates a transfer, sending the first address byte. The I

C controller recog-

nizes the start of a 10-bit address with a match to

SLA[9:8]

and detects the R/W bit =

0 (a Write from the master to the slave). The I

C controller acknowledges, indicating

it is available to accept the transaction.

3. The master sends the second address byte. The SLAVE mode I

C controller detects an

address match between the second address byte and

SLA[7:0]

. The

SAM

bit in the

I2CISTAT Register is set to 1, thereby causing an interrupt. The

bit is cleared to 0,

indicating a Write to the slave. The I

C controller acknowledges, indicating it is avail-

able to accept the data.

4. The software responds to the interrupt by reading the I2CISTAT Register, which clears

the

SAM

bit. Because

= 0, no immediate action is taken by the software until the

first byte of data is received. If the software is only able to accept a single byte, it sets
the

NAK

bit in the I2CCTL Register.

5. The master detects the Acknowledge and sends the first byte of data.

6. The I

C controller receives the first byte and responds with Acknowledge or Not

Acknowledge, depending on the state of the

NAK

bit in the I2CCTL Register. The I

controller generates the receive data interrupt by setting the

RDRF

bit in the I2CISTAT

Slave Address

1st Byte

W=0

Slave Address

2nd Byte

Data

A/A

P/S

Figure 33. Data Transfer Format--Slave Receive Transaction with 10-Bit Address

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7. The software responds by reading the I2CISTAT Register, finding the

RDRF

bit = 1,

and then reading the I2CDATA Register, which clears the

RDRF

bit. If the software can

accept only one more data byte, it sets the

NAK

bit in the I2CCTL Register.

8. The master and slave loops through steps 5 to 7 until the master detects a Not

Acknowledge instruction or runs out of data to send.

9. The master sends the

STOP

RESTART

signal on the bus. Either of these signals can

cause the I

C controller to assert the STOP interrupt (the

STOP

bit = 1 in the

I2CISTAT Register). Because the slave received data from the master, the software
takes no action in response to the STOP interrupt other than reading the I2CISTAT
Register to clear the

STOP

bit.

Slave Transmit Transaction with 7-bit Address

The data transfer format for a master reading data from a slave in 7-bit address mode is
shown in Figure 37. The procedure that follows describes the I

C Master/Slave Controller

operating as a slave in 7-bit addressing mode and transmitting data to the bus master.

1. The software configures the controller for operation as a slave in 7-bit addressing

mode, as follows.
a. Initialize the

MODE

field in the I

C Mode Register for either SLAVE ONLY mode

or MASTER/SLAVE mode with 7-bit addressing.

b. Optionally set the

GCE

bit.

c. Initialize the

SLA[6:0]

bits in the I

C Slave Address Register.

d. Set

IEN

= 1 in the I

C Control Register. Set

NAK

= 0 in the I

C Control Register.

2. The master initiates a transfer, sending the address byte. The SLAVE mode I

C con-

troller finds an address match and detects that the R/W bit = 1 (read by the master
from the slave). The I

C controller acknowledges, indicating that it is ready to accept

the transaction. The

SAM

bit in the I2CISTAT Register is set to 1, causing an interrupt.

The

bit is set to 1, indicating a Read from the slave.

3. The software responds to the interrupt by reading the I2CISTAT Register, thereby

clearing the

SAM

bit. Because

= 1, the software responds by loading the first data

byte into the I2CDATA Register. The software sets the

TXI

bit in the I2CCTL Register

to enable transmit interrupts. When the master initiates the data transfer, the I

C con-

troller holds SCL Low until the software has written the first data byte to the
I2CDATA Register.

4. SCL is released and the first data byte is shifted out.

Slave Address

R = 1

Data

P/S

Figure 34. Data Transfer Format--Slave Transmit Transaction with 7-bit Address

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5. After the first bit of the first data byte has been transferred, the I

C controller sets the

TDRE

bit, which asserts the transmit data interrupt.

6. The software responds to the transmit data interrupt (

TDRE

= 1) by loading the next

data byte into the I2CDATA Register, which clears

TDRE

7. After the data byte has been received by the master, the master transmits an Acknowl-

edge instruction (or Not Acknowledge instruction if this byte is the final data byte).

8. The bus cycles through steps 5 to 7 until the final byte has been transferred. If the soft-

ware has not yet loaded the next data byte when the master brings SCL Low to trans-
fer the most significant data bit, the slave I

C controller holds SCL Low until the data

C controller sets the

NCKI

bit in the I2CISTAT Register, causing the Not

Acknowledge interrupt to be generated.

9. The software responds to the Not Acknowledge interrupt by clearing the

TXI

bit in the

I2CCTL Register and by asserting the

FLUSH

bit of the I2CCTL Register to empty the

data register.

10. When the master has completed the final acknowledge cycle, it asserts a

STOP

RESTART

condition on the bus.

11. The slave I

C controller asserts the

STOP/RESTART

interrupt (set

SPRS

bit in

I2CISTAT Register).

12. The software responds to the

STOP/RESTART

interrupt by reading the I2CISTAT Reg-

ister, which clears the

SPRS

bit.

Slave Transmit Transaction with 10-Bit Address

The data transfer format for a master reading data from a slave with 10-bit addressing is
shown in Figure 35. The following procedure describes the I

C Master/Slave Controller

operating as a slave in 10-bit addressing mode, transmitting data to the bus master.

1. The software configures the controller for operation as a slave in 10-bit addressing

mode.
a. Initialize the

MODE

field in the I

C Mode Register for either SLAVE ONLY mode

or MASTER/SLAVE mode with 10-bit addressing.

b. Optionally set the

GCE

bit.

c. Initialize the

SLA[7:0]

bits in the I2CSLVAD Register and

SLA[9:8]

in the

I2CMODE Register.

S Slave Address

1st Byte

W = 0 A Slave Address

2nd Byte

S Slave Address

1st Byte

R = 1 A Data A Data A

Figure 35. Data Transfer Format--Slave Transmit Transaction with 10-Bit Address

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d. Set

IEN

= 1,

NAK

= 0 in the I

C Control Register.

2. The master initiates a transfer, sending the first address byte. The SLAVE mode I

controller recognizes the start of a 10-bit address with a match to

SLA[9:8]

and

detects the R/W bit = 0 (a Write from the master to the slave). The I

C controller

acknowledges, indicating it is available to accept the transaction.

3. The master sends the second address byte. The SLAVE mode I

C controller compares

the second address byte with the value in

SLA[7:0]

. If there is a match, the

SAM

bit in

the I2CISTAT Register is set = 1, causing a slave address match interrupt. The

bit

is set = 0, indicating a write to the slave. If a match occurs, the I

C controller acknowl-

edges on the I

C bus, indicating it is available to accept the data.

4. The software responds to the slave address match interrupt by reading the I2CISTAT

SAM

bit. Because the

bit = 0, no further action is

required.

5. The master sees the Acknowledge and sends a

RESTART

instruction, followed by the

first address byte with the R/W set to 1. The SLAVE mode I

C controller recognizes

the

RESTART

instruction followed by the first address byte with a match to

SLA[9:8]

, and detects the R/W = 1 (the master reads from the slave). The slave I

controller sets the

SAM

bit in the I2CISTAT Register, which causes the slave address

match interrupt. The

bit is set = 1. The SLAVE mode I

C controller acknowledges

on the bus.

6. The software responds to the interrupt by reading the I2CISTAT Register, clearing the

SAM

bit. The software loads the initial data byte into the I2CDATA Register and sets

the

TXI

bit in the I2CCTL Register.

7. The master starts the data transfer by asserting SCL Low. After the I

C controller has

data available to transmit, the SCL is released, and the master proceeds to shift the
first data byte.

8. After the first bit of the first data byte has been transferred, the I

C controller sets the

TDRE

bit which asserts the transmit data interrupt.

9. The software responds to the transmit data interrupt by loading the next data byte into

the I2CDATA Register.

10. The I

C master shifts in the remainder of the data byte. The master transmits the

Acknowledge (or Not Acknowledge, if this byte is the final data byte).

11. The bus cycles through steps 7 to 10 until the final byte has been transferred. If the

software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I

C controller holds SCL Low until the

data register is written.

When a Not Acknowledge is received by the slave, the I

C controller sets the

NCKI

bit

in the I2CISTAT Register, causing the NAK interrupt to be generated.

I2C Master/Slave Controller

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12. The software responds to the

NAK

interrupt by clearing the

TXI

bit in the I2CCTL

FLUSH

bit of the I2CCTL Register.

13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a

STOP

RESTART

condition on the bus.

14. The slave I

C controller asserts the

STOP/RESTART

interrupt (sets the

SPRS

bit in the

I2CISTAT Register).

15. The software responds to the

STOP

interrupt by reading the I2CISTAT Register and

clearing the

SPRS

bit.

C Data Register

The I

C Data Register, shown in Table 92, contains the data that is to be loaded into the

Shift Register to transmit onto the I

C bus. This register also contains data that is loaded

from the Shift Register after it is received from the I

C bus. The I

C Shift Register is not

accessible in the Register File address space, but is used only to buffer incoming and out-
going data.

Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I

C controller is in SLAVE mode, and data is being received).

C Interrupt Status Register

The read-only I

C Interrupt Status Register, shown in Table 93, indicates the cause of any

current I

C interrupt and provides status of the I

C controller

. When an interrupt occurs,

one or more of the

TDRE

RDRF

SAM

ARBLST

SPRS

NCKI

bits is set. The

GCA

and

bits do not generate an interrupt but rather provide status associated with the

SAM

bit interrupt.

Table 92. I

C Data Register (I2CDATA)

BITS

FIELD

DATA

RESET

R/W

R/W

ADDR

F50H

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I2C Interrupt Status Register

Z8FMC16100 Series Flash MCU

Product Specification

185

TDRE--Transmit Data Register Empty

When the I

C Controller is enabled, this bit is 1 when the I

C Data register is empty.

When set, this bit causes the I

C Controller to generate an interrupt, except when the I

Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA register.
RDRF--Receive Data Register Full

This bit is set = 1 when the I

C Controller is enabled and the I

C Controller has received a

byte of data. When asserted, this bit causes the I

C Controller to generate an interrupt.

This bit clears by reading the I2CDATA register.

SAM--Slave Address Match

This bit is set = 1 if the I

C Controller is enabled in Slave mode and an address is received

which matches the unique Slave address or General Call Address (if enabled by the

GCE

bit in the I

C Mode register). In 10-bit addressing mode, this bit is not set until a match is

achieved on both address bytes. When this bit is set, the

and

GCA

bits are also valid.

This bit clears by reading the I2CISTAT register.

GCA--General Call Address

This bit is set in Slave mode when the General Call Address or START byte is recognized
(in either 7 or 10 bit Slave mode). The

GCE

bit in the I

C Mode register must be set to

enable recognition of the General Call Address and START byte. This bit clears when

IEN

= 0 and is updated following the first address byte of each Slave mode transaction. A Gen-
eral Call Address is distinguished from a START byte by the value of the RD bit (RD = 0
for General Call Address, 1 for START byte).

RD--Read

This bit indicates the direction of transfer of the data. It is set when the Master is reading
data from the Slave. This bit matches the least-significant bit of the address byte after the
START condition occurs (for both Master and Slave modes). This bit clears when IEN = 0
and is updated following the first address byte of each transaction.

ARBLST--Arbitration Lost

This bit is set when the I

C Controller is enabled in Master mode and loses arbitration

(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT register is read.

Table 93. I

C Interrupt Status Register (I2CISTAT)

BITS

FIELD

TDRE

RDRF

SAM

GCA

ARBLST

SPRS

NCKI

RESET

R/W

ADDR

F51H

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SPRS--Stop/Restart Condition Interrupt

This bit is set when the I

C Controller is enabled in Slave mode and detects a STOP or

RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the

RSTR

bit of the I2CSTATE register to determine

whether the interrupt was caused by a STOP or RESTART condition.

NCKI--NAK Interrupt

In Master mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the

START

nor the

STOP

bit is active. In Master mode, this bit can only be cleared

by setting the

START

STOP

bits.

In Slave mode, this bit is set when a Not Acknowledge condition is received (Master read-
ing data from Slave), indicating the Master is finished reading. A STOP or RESTART con-
dition follows. In Slave mode this bit clears when the I2CISTAT register is read.

C Control Register

The I

C Control Register, shown in Table 94, enables and configures I

C operation.

NOTE: R/W1 - bit may be set (write 1) but not cleared.

IEN--I

C Enable

This bit enables the I

C Controller.

START--Send Start Condition

When set, this bit causes the I

C Controller (when configured as the Master) to send the

Start condition. Once asserted, it is cleared by the I

C Controller after it sends the Start

condition or by deasserting the

IEN

bit. If this bit is 1, it cannot be cleared by writing to

the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or
I2CSHIFT register. If there is no data in one of these registers, the I

C Controller waits

until data is loaded. If this bit is set while the I

C Controller is shifting out data, it gener-

ates a RESTART condition after the byte shifts and the acknowledge phase completes. If
the

STOP

bit is also set, it also waits until the STOP condition is sent before the START

condition.

If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status register will be set.

Table 94. I

C Control Register (I2CCTL)

BITS

FIELD

IEN

START

STOP

BIRQ

TXI

NAK

FLUSH

FILTEN

RESET

R/W

R/W

R/W1

R/W

R/W1

R/W

ADDR

F52H

PS024604-1005

P R E L I M I N A R Y

I2C Baud Rate High and Low Byte Registers

Z8FMC16100 Series Flash MCU

Product Specification

187

STOP--Send Stop Condition

When set, this bit causes the I

C Controller (when configured as the Master) to send the

STOP condition after the byte in the I

C Shift register has completed transmission or after

a byte has been received in a receive operation. When set, this bit is reset by the I

C Con-

troller after a STOP condition has been sent or by deasserting the

IEN

bit. If this bit is 1, it

cannot be cleared to 0 by writing to the register.

If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.

BIRQ--Baud Rate Generator Interrupt Request

This bit is ignored when the I

C Controller is enabled. If this bit is set = 1 when the I

Controller is disabled (

IEN

= 0) the baud rate generator is used as an additional timer caus-

ing an interrupt to occur every time the baud rate generator counts down to one. The baud
rate generator runs continuously in this mode, generating periodic interrupts.

TXI--Enable TDRE interrupts

This bit enables interrupts when the I

C Data register is empty.

NAK--Send NAK

Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is

cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.

FLUSH--Flush Data

Setting this bit clears the I

C Data register and sets the

TDRE

bit to 1. This bit allows flush-

ing of the I

C Data register when an NAK condition is received after the next data byte

has been written to the I

C Data register. Reading this bit always returns 0.

FILTEN--I

C Signal Filter Enable

Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This
function provides the spike suppression filter required in I2C Fast Mode. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.

C Baud Rate High and Low Byte Registers

The I

C Baud Rate High and Low Byte registers, shown in Tables 95 and 96, combine to

form a 16-bit reload value,

BRG

[15:0], for the I

C Baud Rate Generator. The I

C baud rate

is calculated using the following equation.

BRG

0000h

, use

10000h

in the equation):

C Baud Rate (bits/s) =

System Clock Frequency (Hz)

4 x BRG[15:0]

Note:

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BRH = I

C Baud Rate High Byte

Most significant byte,

BRG

[15:8], of the I

C Baud Rate Generator's reload value.

If the

DIAG

bit in the I

C Mode Register is set to 1, a read of the I2CBRH register returns

the current value of the I

C Baud Rate Counter[15:8].

BRL = I

C Baud Rate Low Byte

Least significant byte, BRG[7:0], of the I

C Baud Rate Generator's reload value.

If the

DIAG

bit in the I

C Mode Register is set to 1, a read of the I2CBRL register returns

the current value of the I

C Baud Rate Counter[7:0]

C State Register

The read-only I

C State Register provides information about the state of the I

C bus and

the I

C bus controller.

When the

DIAG

bit of the I

C Mode Register is cleared, this register provides information

on the internal state of the I

C controller and I

C bus, as shown in Table 97. A more

detailed discussion of each bit follows this table.

When the

DIAG

bit of the I

C Mode Register is set, this register returns the value of the

C controller state machine, as shown in

Table 98

, which follows on page 190.

Table 95. I

C Baud Rate High Byte Register (I2CBRH)

BITS

FIELD

BRH

RESET

FFH

R/W

R/W

ADDR

F53H

Table 96. I

C Baud Rate Low Byte Register (I2CBRL)

BITS

FIELD

BRL

RESET

FFH

R/W

R/W

ADDR

F54H

Note:

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P R E L I M I N A R Y I2C

State

Z8FMC16100 Series Flash MCU

Product Specification

189

ACKV--ACK Valid

This bit is set if sending data (Master or Slave) and the

ACK

bit in this register is valid for

the byte just transmitted. This bit can be monitored if it is appropriate for software to ver-
ify the

ACK

value before writing the next byte to be sent. To operate in this mode, the data

TDRE

asserts; instead, software waits for

ACKV

to assert.

This bit clears when transmission of the next byte begins or the transaction is ended by a
STOP or RESTART condition.

ACK--Acknowledge

This bit indicates the status of the Acknowledge for the last byte transmitted or received.
This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.

AS--Address State

This bit is active High while the address is being transferred on the I

C bus.

DS--Data State

This bit is active high while the data is being transferred on the I

C bus.

10B--This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a Master. After the

START

bit is set, if the five most-significant bits of the address are

11110B

, this bit is set. When set, it is reset once the address has been sent.

RSTR--RESTART

This bit is updated each time a STOP or RESTART interrupt occurs (

SPRS

bit set in

I2CISTAT register).

0 = Stop condition

1 = Restart condition

SCLOUT--Serial Clock Output

Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I2C bus can be observed via the GPIO Input register.

BUSY--I

C Bus Busy

0 = No activity on the I

C Bus.

1 = A transaction is underway on the I

C bus.

Table 97. I

C State Register (I2CSTATE) - Description when DIAG = 0

BITS

FIELD

ACKV

ACK

10B

RSTR

SCLOUT

BUSY

RESET

R/W

ADDR

F55H

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I2CSTATE_H--I

C State

This field defines the current state of the I

C Controller. It is the most significant nibble of

the internal state machine. Table 99 defines the states for this field.

I2CSTATE_L--Least significant nibble of the I

C state machine. This field defines the

substates for the states defined by I2CSTATE_H. Table 100 defines the values for this
field.

Table 98. I

C State Register (I2CSTATE) - Description when DIAG = 1

BITS

FIELD

I2CSTATE_H

I2CSTATE_L

RESET

R/W

ADDR

F55H

Table 99. I2CSTATE_H

State
Encoding

State Name

State Description

0000

Idle

C bus is idle or I

C controller is disabled.

0001

Slave Start

C controller has received a START condition.

0010

Slave Bystander

Address did not match; ignore remainder of transaction.

0011

Slave Wait

Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.

0100

Master Stop2

Master completing STOP condition (SCL = 1, SDA = 1).

0101

Master Start/Restart

MASTER mode sending START condition (SCL = 1, SDA = 0).

0110

Master Stop1

Master initiating STOP condition (SCL = 1, SDA = 0).

0111

Master Wait

Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.

1000

Slave Transmit Data

9 substates, one for each data bit and one for the Acknowledge.

1001

Slave Receive Data

9 substates, one for each data bit and one for the Acknowledge.

1010

Slave Receive Addr1

Slave receiving first address byte (7- and 10-bit addressing)

9 substates, one for each address bit and one for the
Acknowledge.

1011

Slave Receive Addr2

Slave Receiving second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.

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P R E L I M I N A R Y I2C

State

Z8FMC16100 Series Flash MCU

Product Specification

191

1100

Master Transmit Data 9 substates, one for each data bit and one for the Acknowledge.

1101

Master Receive Data

9 substates, one for each data bit and one for the Acknowledge.

1110

Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing)

9 substates, one for each address bit and one for the
Acknowledge.

1111

Master Transmit Addr2 Master sending second address byte (10-bit addressing)

9 substates, one for each address bit and one for the
Acknowledge.

Table 100. I2CSTATE_L

State

I2CSTATE_H

Substate

I2CSTATE_L Substate Name

State Description

0000�0100

0000

There are no substates for these I2CSTATE_H
values.

0110�0111

0000

There are no substates for these I2CSTATE_H
values.

0101

0000

Master Start

Initiating a new transaction

0001

Master Restart

Master is ending one transaction and starting a
new one without letting the bus go idle.

1000�1111

0111

send/receive bit 7

Sending/Receiving most significant bit

0110

send/receive bit 6

0101

send/receive bit 5

0100

send/receive bit 4

0011

send/receive bit 3

0010

send/receive bit 2

0001

send/receive bit 1

0000

send/receive bit 0

Sending/Receiving least significant bit

1000

send/receive
Acknowledge

Sending/Receiving Acknowledge

Table 99. I2CSTATE_H (Continued)

State
Encoding

State Name

State Description

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C Mode Register

The I

C Mode Register, Table 101, provides control over master versus slave operating

mode, slave address and diagnostic modes.

MODE--Selects the I

C Controller operational mode

00 = Master/Slave capable (supports multi-Master arbitration) with 7-bit Slave address

01 = Master/Slave capable (supports multi-Master arbitration) with 10-bit Slave address

10 = Slave Only capable with 7-bit address

11 = Slave Only capable with 10-bit address

IRM--Interactive Receive Mode

Valid in Slave mode when software needs to interpret each received byte before acknowl-
edging. This bit is useful for processing the data bytes following a General Call Address or
if software wants to disable hardware address recognition.

0 = Acknowledge occurs automatically and is determined by the value of the

NAK

bit of

the I2CCTL register.

1 = A receive interrupt is generated for each byte received (address or data). The SCL is
held Low during the acknowledge cycle until software writes to the I2CCTL register. The
value written to the

NAK

bit of the I2CCTL register is output on SDA. This value allows

software to Acknowledge or Not Acknowledge after interpreting the associated address/
data byte.

GCE--General Call Address Enable

Enables reception of messages beginning with the General Call Address or START byte.

0 = Do not accept a message with the General Call Address or START byte.

1 = Do accept a message with the General Call Address or START byte. When an address
match occurs, the GCA and RD bits in the I

C Status register indicates whether the

address matched the General Call Address/START byte or not. Following the General Call
Address byte, software may set the

IRM

bit that allows software to examine the following

data byte(s) before acknowledging.

SLA[9:8]-- Slave Address Bits 9 and 8.

Initialize with the appropriate Slave address value when using 10-bit Slave addressing.
These bits are ignored when using 7-bit Slave addressing.

DIAG--Diagnostic Mode

Selects read back value of the Baud Rate Reload and State registers.

Table 101. I

C Mode Register (I2CMODE)

BITS

FIELD

Reserved

MODE[1:0]

IRM

GCE

SLA[9:8]

DIAG

RESET

R/W

R/W

ADDR

F56H

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P R E L I M I N A R Y Comparator

Operation

Z8FMC16100 Series Flash MCU

Product Specification

195

Comparator and Operational Amplifier

The Z8FMC16100 Series Flash MCU devices feature a general-purpose comparator and
an operational amplifier. The comparator is a moderate speed (200 ns propagation delay)
device that is designed for a maximum input offset of 5 mV. The comparator can be used to
compare two analog input signals. General-purpose input pins (CINP and CINN) provide
the comparator inputs. The output is available as an interrupt source.

The operational amplifier is a two-input, one-output operational amplifier with a typical
open loop gain of 10,000 (80 dB). One general-purpose input pin, OPINP, provides a non-
inverting amplifier input, while another general-purpose input pin, OPINN, provides the
inverting amplifier input. The output is available at the output pin, OPOUT.

The key operating characteristics of the operational amplifier are:

�

Frequency compensated for unity gain stability

�

Input common-mode range from GND (0.0 V) to V

� 1 V

�

Input offset voltage less than 15 mV

�

Output voltage swing from GND + 0.1 V to V

� 0.1 V

�

Input bias current less than 1 nA

�

Operating the operational amplifier open loop (no feedback) effectively provides an-
other on-chip comparator, if appropriate

Comparator Operation

The comparator output reflects the relationship between the noninverting input and the
inverting (reference) input. If the voltage on the noninverting input is higher than the volt-
age on the inverting input, the comparator output is at a high state. If the voltage on the
noninverting input is lower than the voltage on the inverting input, the comparator output
is at a low state.

To operate, the comparator must be enabled by setting the

CMPEN

bit in the Comparator

and Op Amp Register to 1. In addition the CINP and CINN comparator input alternate
functions must be enabled on their respective general-purpose I/O pins. Refer to the

GPIO

Alternate Functions

section on page 36 for more information.

The comparator does not automatically power-down. To reduce operating current when
not in use, the comparator may be disabled by clearing the

CMPEN

bit to 0.

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Operational Amplifier Operation

To operate, the operational amplifier must be enabled by setting the

OPEN

bit in the Com-

parator and Op Amp Register to 1. In addition, the OPINP, OPINN, and OPOUT alternate
functions must be enabled on their respective general-purpose I/O pins. Refer to the

GPIO

Alternate Functions

section on page 36 for more information.

The logical value of the operational amplifier output (OPOUT) can be read from the Port 3
data input register if both the operational amplifier and input pin Schmitt trigger are
enabled. Refer to the

GPIO Alternate Functions

section on page 36 for more information.

The operational amplifier can also generate an interrupt via the GPIO Port B3 input inter-
rupt, if enabled.

The output of the operational amplifier is also connected to an analog input (ANA3) of the
Analog-to-Digital Converter (ADC) multiplexer.

The operational amplifier does not automatically power-down. To reduce operating cur-
rent when not in use, the operational amplifier may be disabled by clearing the

OPEN

bit in

the Comparator and Op Amp Register to 0.

When the operational amplifier is disabled, the output is high impedance.

Interrupts

The comparator will generate an interrupt on any change in the logic output value (from 0
to 1 and from 1 to 0). Refer to the

Interrupt Controller

chapter on page 51 for information

about enabling and prioritization of the comparator interrupt.

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P R E L I M I N A R Y

Comparator and Op Amp Control Register

Z8FMC16100 Series Flash MCU

Product Specification

197

Comparator and Op Amp Control Register

The Comparator and Op Amp Control (CMPOPC) Register, shown in Table 103, enables
the comparator and operational amplifier and provides access to the comparator output.

Table 103. Comparator and Op Amp Control Register (CMPOPC)

BITS

FIELD

OPEN

Reserved

CPSEL

CMPIRQ

CMPIV

CMPOUT

CMPEN

RESET

R/W

R/W

ADDR

F90H

Bit

Position

Value

(H)

Description

[7]

OPEN

Operational Amplifier Disable

Operational amplifier is disabled.

Operational amplifier is enabled.

[6:5]

Reserved

Must be 0.

[3]

CPSEL

Comparator Input Select

Comparator input is PA1

Comparator input is PB4

[3]

CMPIRQ

Comparator Interrupt Edge Select

Interrupt Request on Comparator Rising Edge

Interrupt Request on Comparator Falling Edge

[2]

CMPIV

PWM Fault Comparator Polarity

PWM Fault is active when cp+ > cp-

PWM Fault is active when cp- > cp+

[1]

CMPOUT

Comparator Output Value

Comparator output is logical 0.

Comparator output is logical 1.

[0]

CMPEN

Comparator Enable

Comparator is disabled.

Comparator is enabled.

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P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

199

Analog-to-Digital Converter

The Z8FMC16100 Series Flash MCU includes an eight-channel analog-to-digital con-
verter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The
features of the successive-approximation ADC include:

�

Eight analog input sources multiplexed with general-purpose I/O ports

�

Fast conversion time, less than 5 �s

�

Programmable timing controls

�

Interrupt upon conversion complete

�

Internal voltage reference generator

�

Internal reference voltage available externally

�

Ability to supply external reference voltage

�

Timer count capture on every ADC conversion

Architecture

The ADC architecture, as shown in Figure 36, consists of an 8-input multiplexer, sample-
and-hold amplifier, and 10-bit successive-approximation analog-to-digital converter. The
ADC digitizes the signal on a selected channel and stores the digitized data in the ADC
data registers. In environments with high electrical noise, an external RC filter must be
added at the input pins to reduce high-frequency noise.

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Operation

The ADC converts the analog input, ANA

, to a 10-bit digital representation. The equa-

tion for calculating the digital value is represented by:

Assuming zero gain and offset errors, any voltage outside the ADC input limits of AV

and V

REF

returns all 0s or 1s, respectively.

A new conversion can be initiated by either software write to the ADC Control Register's

START

bit or by PWM trigger. Refer to the

Synchronization of PWM and Analog-to-Digi-

tal Converter

section on page 73 for information about the PWM trigger.

Figure 36. Analog-to-Digital Converter Block Diagram

ADC Output = 1024 x (ANA

� V

REF

)

Internal Voltage

Reference Generator

Sample-and-Hold

Amplifier

Analog-to-Digital

Converter

Reference Input

VR2

RBUF

REFEN

REF

ANA0

ANAIN[2:0]

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

SAMPLE/HOLD

Analog Input

Data

Output

BUSY

ADCLK

ADCEN

START

Analog-to-Digital Converter

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!

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Motor Control Flash MCUs

Product Specification

202

Figure 38 illustrates the timing of an ADC convert period.

ADC Interrupt

The ADC can generate an interrupt request when a conversion has been completed. An
interrupt request that is pending when the ADC is disabled is not automatically cleared.

ADC Timer 0 Capture

The Timer 0 count is captured for every ADC conversion. The capture of the Timer 0
count occurs after the programmed sample time is complete for every conversion and
stored in the ADC Timer Capture Register (ADCTCAP).

Reference Buffer

The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled,
the internal voltage reference generator supplies the ADC and the voltage is available on
the V

REF

pin. When RBUF is disabled, the ADC must have the reference voltage supplied

externally through the V

REF

pin. RBUF is controlled by the

REFEN

bit in the ADC Control

Internal Voltage Reference Generator

The Internal Voltage Reference Generator provides the voltage, VR2, for the RBUF. VR2
is 2 volts.

Figure 38. ADC Convert Timing

13-Clock

Convert Period

ADC Clock

BUSY

Convert msb

Convertbit 8

Convertbit 7

Convertbit 6

Convertbit 5

Convertbit 4

Convertbit 3

Convertbit 2

Convertbit 1

Convertbit 0

Store in Register

PS024604-1005

P R E L I M I N A R Y Calibration

and

Compensation

Z8FMC16100 Series Flash MCU

Product Specification

203

Calibration and Compensation

A user can perform calibration and store the values into Flash, or the user code can per-
form a manual offset calibration. There is no provision for manual gain calibration.

ADC Control Register 0

The ADC Control Register 0 initiates the A/D conversion and provides ADC status infor-
mation. See Table 104.

Table 104. ADC Control Register 0 (ADCCT0)

BITS

FIELD

START

Reserved

REFEN

ADCEN

Reserved

ANAIN[2:0]

RESET

R/W

R/W1

R/W

ADDR

F70H

Bit

Position

Value

(H)

Description

[7]
START

ADC Start / Busy

Writing to 0 has no effect.
Reading a 0 indicates the ADC is available to begin a conversion.

Writing to 1 starts a conversion.
Reading a 1 indicates a conversion is currently in progress.

[6]

Reserved--Must Be 0.

[5]
REFEN

Reference Enable
Internal reference voltage is disabled allowing an external reference voltage to be
used by the ADC.

Internal reference voltage for the ADC is enabled. The internal reference voltage
can be measured on the VREF pin.

[4]
ADCEN

ADC Enable

ADC is disabled for low power operation.

ADC is enabled for normal use.

[3]
Reserved

Reserved--Must Be 0.

Analog-to-Digital Converter

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ADC Raw Data High Byte Register

The ADC Data Raw High Byte Register, shown in Table 105, contains the upper eight bits
of raw data from the ADC output. Access to the ADC Raw Data High Byte register is
Read-Only. This register is used for test only.

ADC Data High Byte Register

The ADC Data High Byte Register, shown in Table 106, contains the upper eight bits of
the ADC output. Access to the ADC Data High Byte Register is Read-Only. Reading the
ADC Data High Byte Register latches data in the ADC Low Bits Register.

[2:0]
ANAIN

000

Analog Input Select
ANA0 input is selected for analog to digital conversion.

001

ANA1 input is selected for analog to digital conversion.

010

ANA2 input is selected for analog to digital conversion.

011

ANA3 input is selected for analog to digital conversion.

100

ANA4 input is selected for analog to digital conversion.

101

ANA5 input is selected for analog to digital conversion.

110

ANA6 input is selected for analog to digital conversion.

111

ANA7 input is selected for analog to digital conversion.

Table 105. ADC Raw Data High Byte Register (ADCRD_H)

BITS

FIELD

ADCRDH

RESET

R/W

ADDR

F71H

Bit

Position

Value

(H)

Description

[7:0]

00H�FFH ADC Raw Data High Byte

The data in this register is the raw data coming from the SAR Block. It will change
as the conversion is in progress. This register is used for testing only.

PS024604-1005

P R E L I M I N A R Y

ADC Data Low Bits Register

Z8FMC16100 Series Flash MCU

Product Specification

205

ADC Data Low Bits Register

The ADC Data Low Bits Register, shown in Table 107, contain the lower bits of the ADC
output as well as an overflow status bit. Access to the ADC Data Low Bits Register is Read-
Only. Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register.

Table 106. ADC Data High Byte Register (ADCD_H)

BITS

FIELD

ADCDH

RESET

R/W

ADDR

F72H

Bit

Position

Value

(H)

Description

[7:0]

00H�FFH ADC High Byte

The last conversion output is held in the data registers until the next ADC
conversion has completed.

Table 107. ADC Data Low Bits Register (ADCD_L)

BITS

FIELD

ADCDL

Reserved

RESET

R/W

ADDR

F73H

Bit

Position

Value

(H)

Description

[7:6]

00�11b

ADC Low Bits
These bits are the 2 least significant bits of the 10-bit ADC output. These bits are
undefined after a Reset. The low bits are latched into this register whenever the
ADC Data High Byte register is read.

[5:0]

Reserved

Reserved--Must Be 0.

Analog-to-Digital Converter

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Sample Settling Time Register

The Sample Settling Time Register, shown in Table 108, is used to program the length of
time from the SAMPLE/HOLD signal to the START signal, when the conversion can
begin. The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this reg-
ister to contain the number of clocks required to meet a 0.5 �s minimum settling time.

Sample Time Register

The Sample Time Register, shown in Table 109, is used to program the length of active
time for the sample after a conversion has begun by setting the

START

bit in the ADC

Control Register or initiated by the PWM. The number of system clock cycles required for
sample time varies from system to system, depending on the clock period used. The sys-
tem designer should program this register to contain the number of system clocks required
to meet a 1 �s minimum sample time.

Table 108. Sample and Settling Time (ADCSST)

BITS

FIELD

Reserved

SST

RESET

R/W

R/W

ADDR

F74H

Bit

Position

Value

(H)

Description

[7:5]

Reserved - Must be 0.

[4:0]

SST

0H - FH

Sample settling time in number of system clock periods to meet 0.5

�

S minimum.

PS024604-1005

P R E L I M I N A R Y

ADC Clock Prescale Register

Z8FMC16100 Series Flash MCU

Product Specification

207

ADC Clock Prescale Register

The ADC Clock Prescale Register, shown in Table 110, is used to provide a divided sys-
tem clock to the ADC. When this register is programmed with

, the System Clock is

used for the ADC Clock.

Table 109. Sample Hold Time (ADCST)

BITS

FIELD

Reserved

RESET

R/W

R/W

ADDR

F75H

Bit

Position

Value

(H)

Description

[7:6]

Reserved - Must be 0.

[5:0]

SHT

0H - FH

Sample Hold time in number of system clock periods to meet 1

�

S minimum.

Table 110. ADC Clock Prescale Register (ADCCP)

BITS

FIELD

Reserved

DIV16

DIV8

DIV4

DIV2

RESET

R/W

R/W

ADDR

F76H

Bit

Position

Value

(H)

Description

[0]
DIV2

DIV2
Clock is not divided

System Clock is divided by 2 for ADC Clock

Analog-to-Digital Converter

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ADC

Timer Capture High Byte Register

The high byte of the ADC Timer Capture Register, shown in Table 111, contains the upper
eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture High Byte Regis-
ter is Read-Only.

ADC

Timer Capture Low Byte Register

The low byte of the ADC Timer Capture Register, shown in Table 112, contains the lower
eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture Low Byte Regis-
ter is Read-Only.

[1]
DIV4

DIV4
Clock is not divided

System Clock is divided by 4 for ADC Clock

[2]
DIV8

DIV8
Clock is not divided

System Clock is divided by 8 for ADC Clock

[3]
DIV16

DIV16
Clock is not divided

System Clock is divided by 16 for ADC Clock

[7:4]

Reserved - must be 0.

Table 111. ADC Timer Capture High Byte Register (ADCTCAP_H)

BITS

FIELD

ADCTCAPH

RESET

R/W

ADDR

F08H

Bit

Position

Value

(H)

Description

[7:0]

00H�FFH ADC Timer Capture Count High Byte

The timer count is held in the data registers until the next ADC conversion is
started.

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P R E L I M I N A R Y

Z8FMC16100 Series Flash MCU

Product Specification

211

Program Memory

The Z8FMC16100 Series Flash MCU products feature up to 16 KB (16,384 bytes) of non-
volatile Flash memory with read/write/erase capability. Flash memory can be programmed
and erased in-circuit by either user code or through the On-Chip Debugger.

The Flash memory array is arranged in 512-byte pages. The 512-byte page is the mini-
mum Flash block size that can be erased. Flash memory is also divided into 8 sectors
which can be protected from programming and erase operations on a per sector basis.

Table 113 describes the Flash memory configuration for each device in the Z8FMC16100
Series Flash MCU. Table 114 lists the sector address ranges. Figure 39 illustrates the Flash
memory arrangement.

Table 113. Flash Memory Configurations

Part
Number

Flash Size

Number of

Pages

Program Memory

Addresses

Sector Size

Number of

Sectors

Pages per

Sector

Z8FMC16

16K (16,384)

0000h�3FFFh

2K (2048)

Z8FMC08

8K (8,192)

0000h�1FFFh

1K (1024)

Z8FMC04

4K (4,096)

0000h�0FFFh

512

Table 114. Flash Memory Sector Addresses

Sector Number

Flash Sector Address Ranges

Z8FMC16

Z8FMC08

Z8FMC04

0000h�07FFh

0000h�03FFh

0000h�01FFh

0800h�0FFFh

0400h�07FFh

0200h�03FFh

1000h�17FFh

0800h�0BFFh

0400h�05FFh

1800h�1FFFh

0C00h�0FFFh

0600h�07FFh

2000h�27FFh

1000h�13FFh

0800h�09FFh

2800h�2FFFh

1400h�17FFh

0A00h�0BFFh

3000h�37FFh

1800h�1BFFh

0C00h�0DFFh

3800h�3FFFh

1C00h�1FFFh

0E00h�0FFFh

PS024604-1005

P R E L I M I N A R Y Operation

Z8FMC16100 Series Flash MCU

Product Specification

213

Operation

The Flash Controller provides the proper signals and timing for the Byte Programming,
Page Erase, and Mass Erase operations in Flash memory. The Flash Controller contains a
protection mechanism, via the Flash Control Register (FCTL), to prevent accidental pro-
gramming or erasure. The following subsections provide details about the Lock, Unlock,
Sector Protect, Byte Programming, Page Erase, and Mass Erase operations.

Timing Using the Flash Frequency Registers

Before performing a program or erase operation on Flash memory, the user must first con-
figure the Flash Frequency High and Low Byte registers. The Flash Frequency registers
allow programming and erasure of Flash with system clock frequencies ranging from
32 KHz through 20 MHz (the valid range is limited to device operating frequencies).

The Flash Frequency High and Low Byte registers combine to form a 16-bit value,

FFREQ

, to control the timing of Flash program and erase operations. The 16-bit Flash Fre-

quency value must contain the system clock frequency in kilohertz. This value is calcu-
lated using the following equation:

Flash programming and erasure are not supported for system clock frequencies below
32 KHz, above 20 MHz, or outside of the device's operating frequency range. The Flash
Frequency High and Low Byte registers must be loaded with the correct value to ensure
proper Flash programming and erase operations.

Flash Read Protection

The user code contained within Flash memory can be protected from external access. Pro-
gramming the Flash Read Protect option bit prevents the reading of user code by the On-

Table 115. Z8FMC16100 Series Flash MCU Information Area Map

Program Memory
Address (Hex)

Function

FE00h�FE3Fh

Reserved.

FE40h�FE53h

Part Number:20-character ASCII alphanumeric
code, left-justified and filled with zeroes.

FE54h�FFFFh

Reserved.

FFREQ[15:0] =

System Clock Frequency (Hz)

1000

Caution:

Program Memory

P R E L I M I N A R Y

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Product Specification

214

Chip Debugger or by using the Flash Controller Bypass mode. Refer to the

Option Bits

chapter on page 223 and the

On-Chip Debugger

chapter on page 241 for more informa-

tion.

Flash Write/Erase Protection

The Z8FMC16100 Series Flash MCU device provides several levels of protection against
accidental program and erasure of the contents of Flash memory. This protection is pro-
vided by the Flash Controller unlock mechanism, the Flash Sector Protect Register, and
the Flash Write Protect option bit.

Flash Controller Unlock Mechanism

At Reset, the Flash Controller locks to prevent accidental program or erasure of Flash
memory. To program or erase Flash memory, the Flash Controller must be unlocked. After
unlocking the Flash Controller, the Flash can be programmed or erased. Any value written
by user code to the Flash Control Register or Page Select Register out of sequence will
lock the Flash Controller.

The proper steps to unlock the Flash Controller from user code are:

1. Write

00h

to the Flash Control Register to reset the Flash Controller.

2. Write the page to be programmed or erased to the Page Select Register.

3. Write the first unlock command

73h

to the Flash Control Register.

4. Write the second unlock command

8Ch

to the Flash Control Register.

5. Rewrite the page written in Step 2 to the Page Select Register.

Flash Sector Protection

The Flash Sector Protect Register can be configured to prevent sectors from being pro-
grammed or erased. After a sector is protected, it cannot be unprotected by user code. The
Flash Sector Protect Register is cleared after reset and any previously written protection
values are lost. User code must write this register in their initialization routine if they want
to enable sector protection.

The Flash Sector Protect Register shares its Register File address with the Page Select
Register. The Flash Sector Protect Register is accessed by writing the Flash Control Regis-
ter with

5EH

. After the Flash Sector Protect Register is selected, it can be accessed at the

Page Select Register address. When user code writes the Flash Sector Protect Register,
bits can only be set to 1. Therefore, sectors can be protected, but not unprotected, via reg-
ister Write operations. The Flash Sector Protect Register is deselected by writing any
value to the Flash Control Register.

The steps to setup the Flash Sector Protect Register from user code are:

1. Write

00h

to the Flash Control Register to reset the Flash Controller.

PS024604-1005

P R E L I M I N A R Y Byte

Programming

Z8FMC16100 Series Flash MCU

Product Specification

215

2. Write

5Eh

to the Flash Control Register to select the Flash Sector Protect Register.

3. Read and/or write the Flash Sector Protect Register, which now resides at Register

File address

FF9h

4. Write

00h

to the Flash Control Register to return the Flash Controller to its reset state.

Flash Write Protection Option Bit

The Flash Write Protect option bit can be enabled to block all program and erase opera-
tions from user code. Refer to the

Option Bits

chapter on page 223 for more information.

Byte Programming

When the Flash Controller is unlocked, Writes to Program Memory from user code will
program a byte into the Flash if the address is located in the unlocked page. An erased
Flash byte contains all ones (

FFh

). The programming operation can only be used to

change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one
requires a Page Erase or Mass Erase operation.

Byte programming can be performed using the eZ8 CPU's LDC or LDCI instructions.
Refer to the eZ8 CPU User Manual (UM0128) for a description of the LDC and LDCI
instructions.

While the Flash Controller programs Flash memory, the eZ8 CPU idles, but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a program-
ming operation is in progress are serviced after the programming operation is complete. To
exit programming mode and lock the Flash Controller, write

00h

to the Flash Control

User code cannot program Flash Memory on a page that lies in a protected sector. When
user code writes memory locations, only addresses located in the unlocked page are pro-
grammed. Memory Writes outside of the unlocked page are ignored.

Each memory location must not be programmed more than twice before an erase is re-
quired.

The proper steps to program Flash memory from user code are:

1. Write

00h

to the Flash Control Register to reset the Flash Controller.

2. Write the page of memory to be programmed to the Page Select Register.

3. Write the first unlock command

73h

to the Flash Control Register.

4. Write the second unlock command

8Ch

to the Flash Control Register.

5. rewrite the page written in Step 2 to the Page Select Register.

6. Write Program Memory using LDC or LDCI instructions to program Flash.

7. Repeat Step 6 to program additional memory locations on the same page.

Caution:

Program Memory

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8. Write

00h

to the Flash Control Register to lock the Flash Controller.

Page Erase

Flash memory can be erased one page (512 bytes) at a time. Page-erasing Flash memory
sets all bytes in that page to the value

FFh

. The Page Select Register identifies the page to

be erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU
idles, but the system clock and on-chip peripherals continue to operate. The eZ8 CPU
resumes operation after the Page Erase operation completes. Interrupts that occur when
the Page Erase operation is in progress are serviced after the Page Erase operation is com-
plete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.

The proper steps to perform a Page Erase operation are:

1. Write

00h

to the Flash Control Register to reset the Flash Controller.

2. Write the page to be erased to the Page Select Register.

3. Write the first unlock command,

73h

, to the Flash Control Register.

4. Write the second unlock command

8Ch

to the Flash Control Register.

5. Rewrite the page written in Step 2 to the Page Select Register.

6. Write the Page Erase command,

95h

, to the Flash Control Register.

Mass Erase

Flash memory cannot be mass-erased by user code.

Flash Controller Bypass

The Flash Controller can be bypassed and the control signals for Flash memory brought
out to the GPIO pins. Bypassing the Flash Controller allows faster programming algo-
rithms by controlling the Flash programming signals directly.

Flash Controller Bypass is recommended for gang-programming applications and large-
volume customers who do not require in-circuit programming of Flash memory.

Refer to the ZiLOG Application Note titled Third-Party Flash Programming Support for
the Z8 Encore!

�

MCU (AN0117) for more information about bypassing the Flash control-

ler. This document is available for download at

www.zilog.com

Flash Controller Behavior in Debug Mode

The following changes in behavior of the Flash Controller occur when the Flash Control-
ler is accessed using the On-Chip Debugger:

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P R E L I M I N A R Y Flash

Control

Z8FMC16100 Series Flash MCU

Product Specification

217

�

The Flash Write Protect option bit is ignored

�

The Flash Sector Protect Register is ignored for programming and erase operations

�

Programming operations are not limited to the page selected in the Page Select Register

�

Bits in the Flash Sector Protect Register can be written to one or zero

�

The second write of the Page Select Register to unlock the Flash Controller is not nec-
essary

�

The Page Select Register can be written when the Flash Controller is unlocked

�

The Mass Erase command is enabled through the Flash Control Register

�

The page erase and programming operations are disabled if the Memory Read Protect
option is enabled

Flash Control Register

The Flash Control Register, shown in Table 116, unlocks the Flash Controller for pro-
gramming and erase operations, or to select the Flash Sector Protect Register.

The Write-Only Flash Control Register shares its Register File address with the Read-
Only Flash Status Register.

Table 116. Flash Control Register (FCTL)

BITS

FIELD

FCMD

RESET

00H

R/W

ADDR

FF8H

Bit

Position

Value

Description

[7:0]

FCMD

73H

8CH

95H

63H

5EH

Flash Command:
First unlock command.

Second unlock command.

Page erase command.

Mass erase command.

Flash Sector Protect register select.
All other commands, or any command out of sequence, locks the Flash
Controller.

Program Memory

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Flash Status Register

The Flash Status Register, shown in Table 117, indicates the current state of the Flash Con-
troller. This register can be read at any time. The read-only Flash Status Register shares its
Register File address with the write-only Flash Control Register.

Flash Page Select Register

The Flash Page Select (FPS) Register, shown in Table 118, selects one of the 32 available
Flash memory pages to be erased or programmed. Each Flash Page contains 512 bytes of
Flash memory. During a Page Erase operation, all Flash memory locations with the 7 most
significant bits of the address assigned by the

PAGE

field are erased to

FFh

The Flash Page Select Register shares its Register File address with the Flash Sector Pro-
tect Register. The Flash Page Select Register cannot be accessed when the Flash Sector
Protect Register is enabled.

Table 117. Flash Status Register (FSTAT)

BITS

FIELD

Reserved

FSTAT

RESET

00B

00_0000B

R/W

ADDR

FF8H

Bit

Position

Value

Description

[7:6]

Reserved

Must be 00.

[5:0]

FSTAT

00_0000

00_0001

00_0010

00_0011

00_0100

00_1xxx

01_0xxx

10_0xxx

Flash Controller Status
Flash Controller locked.

First unlock command received.

Second unlock command received.

Flash Controller unlocked.

Flash Sector Protect register selected.

Program operation in progress.

Page erase operation in progress.

Mass erase operation in progress.

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P R E L I M I N A R Y

Flash Sector Protect Register

Z8FMC16100 Series Flash MCU

Product Specification

219

Flash Sector Protect Register

The Flash Sector Protect Register, shown in Table 119, protects Flash memory sectors
from being programmed or erased from user code. The Flash Sector Protect Register
shares its Register File address with the Flash Page Select Register. The Flash Sector pro-
tect Register can be accessed only after writing the Flash Control Register with

5Eh

User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).

Table 118. Flash Page Select Register (FPS)

BITS

FIELD

INFO_EN

PAGE

RESET

000_0000B

R/W

R/W

ADDR

FF9H

Bit

Position

Value

Description

[7]

INFO_EN

Information Area Enable
Information area is not selected.

Information Area is selected.

The Information area is mapped into the Program Memory address space at
addresses FE00H through FFFFH.

[6:0]

PAGE

Page Select

This 7-bit field selects the Flash memory page for Programming and Page Erase
operations. Program Memory Address[15:9] = PAGE[6:0].

Table 119. Flash Sector Protect Register (FPROT)

BITS

FIELD

SECT7

SECT6

SECT5

SECT4

SECT3

SECT2

SECT1

SECT0

RESET

R/W

R/W1

ADDR

FF9H

R/W1 = Register is accessible for Read operations. Register can be written to 1 only (through user code).

Program Memory

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Flash Frequency High and Low Byte Registers

The Flash Frequency High and Low Byte registers, shown in Tables 120 and 121, com-
bine to form a 16-bit value, FFREQ, to control timing for Flash program and erase opera-
tions. The 16-bit Flash Frequency registers must be written with the system clock
frequency in kilohertz for Program and Erase operations. Calculate the Flash Frequency
value using the following equation:

Flash programming and erasure is not supported for system clock frequencies below
32 KHz, above 20 MHz, or outside of the valid operating frequency range for the device.
The Flash Frequency High and Low Byte registers must be loaded with the correct value
to ensure proper program and erase times.

Bit

Position

Value

Description

[7:0]]

SECTn

Sector Protect

Sector n can be programmed or erased from user code.

Sector n is protected and cannot be programmed or erased from user code.

FFREQ[15:0] = {FFREQH[7:0],FFREQL[7:0]} =

System Clock Frequency

1000

Table 120. Flash Frequency High Byte Register (FFREQH)

BITS

FIELD

FFREQH

RESET

00H

R/W

R/W

ADDR

FFAH

Caution:

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P R E L I M I N A R Y Option

Bit

Types

Z8FMC16100 Series Flash MCU

Product Specification

223

Option Bits

Option bits allow user configuration of certain aspects of the Z8FMC16100 Series Flash
MCU operation. The feature configuration data is stored in program memory and read
during Reset. The features available for control using the option bits are:

�

Watch-Dog Timer time-out selection of interrupt or Reset

�

Watch-Dog Timer enabled at Reset

�

Code protection by preventing external read access of program memory

�

The ability to prevent accidental programming and erasure of program memory

�

Voltage Brown-Out can be disabled during STOP mode to reduce power consumption

�

External oscillator mode selection

�

Selectable PWM OFF state, output polarity, fault state, and Reset state

�

Disable PWM output pairs, enabling them as inputs

�

RESET/Fault0 pin function selection

�

Low power clock divide mode selection

Option Bit Types

Two types of option bits, user option bits and trim option bits, allow configuration of cer-
tain aspects of Z8FMC16100 Series Flash MCU operation. Each is described in this sec-
tion.

User Option Bits

The user option bits are contained in the first two bytes of program memory. Because
these locations contain application-specific device configuration, it is possible for the user
to alter these bytes by programming Flash memory.

The information contained in these bytes is lost when page 0 of program memory is
erased.

Trim Option Bits

The trim option bits are contained in the information page of Flash memory. These bits are
factory-programmed values required to optimize the operation of on-board analog cir-
cuitry, and cannot be altered by the user. Program memory can be erased without endan-
gering these values.

Note:

Option Bits

P R E L I M I N A R Y

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It is possible to alter the working values of these bits by accessing the Trim Bit Address
and Data registers, but these working values are lost after a Reset.

There are 32 trim addresses. To read or write these values, the user code must first write a
value between

00h

and

1Fh

into the Trim Bit Address Register. Writing the Trim Bit Data

Register changes the working value of the target trim data. Reading the Trim Bit Data
Register returns the working value of the target trim data.

User Option Bit Configuration By Reset

Each time the user option bits are programmed or erased, the device must be Reset for the
change to take place.

Option Bit Address Space

The first two bytes of program memory at addresses

0000h

, shown in Table 122, and

0001h

, shown in Table 123, are reserved for the user option bits.

Program Memory Address 0000H

Table 122. User Option Bits at Program Memory Address 0000H

BITS

FIELD WDT_RES WDT_AO

OSC_SEL[1:0]

VBO_AO

Reserved

FWP

RESET

R/W

R/W

ADDR

Program Memory 0000H

Note: U = Unchanged by Reset. R/W = Read/Write.

Bit

Position

Value

(H)

Description

[7]

WDT_RES

Watch-Dog Timer Reset

Watch-Dog Timer time-out generates an interrupt request. Interrupts must be
globally enabled for the eZ8 CPU to acknowledge the interrupt request.

Watch-Dog Timer time-out causes a Reset.

[6]

WDT_AO

Watch-Dog Timer Always On
Watch-Dog Timer is automatically enabled.

Watch-Dog Timer is enabled upon execution of the WDT instruction.

Caution:

PS024604-1005

P R E L I M I N A R Y

Program Memory Address 0001H

Z8FMC16100 Series Flash MCU

Product Specification

225

Program Memory Address 0001H

These bits define the behavior of the Pulse-Width Modulator. The high and low default
off-state (the output polarity) is also defined here. The off-state is used by the PWM output
control and PWM Fault logic. PWM output pairs can be disabled and used as high-imped-
ance input pins. The RESET/Fault0 pin function is also selectable.

[5:4]

OSC_SEL

External Oscillator Mode Selection:
Reserved.

Minimum power for use with very low frequency crystals (32KHz to 1.0MHz).

Medium power for use with medium frequency crystals or ceramic resonators
(0.5MHz to 10.0MHz).

Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz).

[3]

VBO_AO

Voltage Brown Out Always On

Voltage Brown-Out Protection is disabled in STOP mode to reduce total power
consumption.

Voltage Brown-Out Protection is always enabled.

[2]

Read Protect

External access to User program code is disabled.

User program code is accessible.

[1]

Reserved

Must be 1.

his Option Bit is reserved for future use and must always be 1.

[0]

FWP

Flash Write Protect

Programming, Page Erase, and Mass Erase using User Code is disabled.

Programming, Page Erase, and Mass Erase are enabled for all of Flash Program
Memory.

Table 123. Options Bits at Program Memory Address 0001H

BITS

FIELD

FLTSEL

LPDEN

Reserved PWM2EN PWM1EN PWM0EN

PWMHI

PWMLO

RESET

R/W

R/W

ADDR

Program Memory 0001H

Note: U = Unchanged by Reset. R/W = Read/Write.

Bit

Position

Value

(H)

Description

Option Bits

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Bit

Position

Value

(H)

Description

[7]

FLTSEL

RESET/Fault0 Select

RESET/Fault0 pin is configured as Fault0 input.

RESET/Fault0 pin is configured as RESET input.

[6]

LPDEN

Low Power Divide Mode Enable. See

Oscillator Control

chapter on page 231.

Low Power Divide mode is enabled

Low Power Divide mode is disabled

[5]

Reserved

Must be 1.

his Option Bit is reserved for future use and must always be 1.

[4]

PWM2EN

PWM Output Pair PWM2 Enable

PWM2 outputs are enabled and controlled by PWM logic.

PWM2 outputs are always high-impedance.

[3]

PWM1EN

PWM Output Pair PWM1 Enable

PWM1 outputs are enabled and controlled by PWM logic.

PWM1 outputs are always high-impedance.

[2]

PWM0EN

PWM Output Pair PWM0 Enable

PWM0 outputs are enabled and controlled by PWM logic.

PWM0 outputs are always high-impedance.

[1]

PWMHI

PWM High Side (PWM outputs 0H,1H, 2H) Default Off-State

PWM High-side inactive state is low, active state is High.

PWM High-side inactive state is high, active state is Low.

[0]

PWMLO

PWM Low Side (PWM outputs 0L,1L, 2L) Default Off-State

PWM Low-side inactive state is low, active state is high.

PWM Low-side inactive state is high, active state is low.

Option Bits

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Trim Bit Address 0001H

This register is loaded from the Flash Information Area following reset or STOP mode
recovery. Writing to this register allows user frequency adjustment of the IPO. Writing to
this register does not effect the Flash memory contents.

Trim Bit Address 0002H

Table 126. IPO Trim Option Bits at 0001H (IPO_TRIM)

BITS

FIELD

TEMP_TRIM

IPO_TRIM[9:8]

RESET

R/W

R/W

ADDR

Information Page Memory 0021H

U = Unchanged by Reset. R/W = Read/Write.

Bit Position Value (H) Description

TEMP_TRIM

[5:0]

00 - 3FH Internal precision Oscillator trim bits for Temperature compensation.

IPO_TRIM

[9:8]

00 - 11H

Internal Precision Oscillator Trim Byte

Used with IPO Trim1 options bits as bits [9:8]. Trimming for Internal Precision

Oscillator frequency adjustment.

Table 127. IPO Trim1 Option Bits at 0002H (IPO_TRIM1)

BITS

FIELD

IPO_TRIM[7:0]

RESET

R/W

R/W

ADDR

Information Page Memory 0022H

U = Unchanged by Reset. R/W = Read/Write.

PS024604-1005

P R E L I M I N A R Y Operation

Z8FMC16100 Series Flash MCU

Product Specification

231

Oscillator Control

The Z8FMC16100 Series Flash MCU uses three possible clocking schemes, each user-
selectable:

�

Trimmable Internal Precision Oscillator

�

On-chip oscillator using off-chip crystal/resonator or external clock driver

�

On-chip low precision Watch-Dog Timer oscillator

In addition, Z8FMC16100 Series Flash MCUs contain clock failure detection and recov-
ery circuitry, allowing continued operation despite any potential failure of the primary
oscillator.

The on-chip system clock frequency can be reduced via a clock divider allowing reduced
dynamic power dissipation. Flash memory can be powered down during portions of the
clock period when running slower than 10 MHz.

Operation

This section explains the logic used to select the system clock, divide down the system
clock, and handle oscillator failures. A description of the specific operation of each oscil-
lator is outlined elsewhere in this document. Refer to

Watch-Dog Timer

chapter on page

63, the

On-Chip Oscillator

chapter on page 237, and the

Internal Precision Oscillator

chapter on page 239.

System Clock Selection

The oscillator control block selects from the available clocks. Table 129 details each clock
source and its usage.

Oscillator Control

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Unintentional accesses to the Oscillator Control Register (OSCCTL) can stop the chip by
switching to a nonfunctioning oscillator. Accidental alteration of the OSCCTL register is
prevented by a locking/unlocking scheme. To write the register, unlock it by making two
writes to the OSCCTL register with the values

E7H

followed by

18H

. A third write to the

OSCCTL register then changes the value of the register and returns the register to a locked
state. Any other sequence of oscillator control register writes has no effect. The values
written to unlock the register must be ordered correctly, but need not be consecutive. It is
possible to access other registers within the locking/unlocking operation.

Clock Selection Following System Reset

The Internal Precision Oscillator is selected following a System Reset. Startup code after
the System Reset may change the system clock source by unlocking and configuring the
OSCCTL register. If the

LPDEN

bit in Program Memory Address 0001H is zero, Flash

Low Power mode is enabled during reset. When Flash Low Power mode is enabled during
reset, the

FLPEN

bit in the Oscillator Control Register (OSCCTL) will be set and the

DIV

field of the OSCDIV register will be set to

08h

Clock Failure Detection and Recovery for Primary Oscillator

The Z8FMC16100 Series Flash MCU generates a System Exception when a failure of the
primary oscillator occurs if the

POFEN

bit is set in the OSCCTL Register. To maintain sys-

tem function in this situation, the clock failure recovery circuitry automatically forces the

Table 129. Oscillator Configuration and Selection

Clock Source

Characteristics

Required Setup

Internal Precision
Oscillator

� 5.5296 MHz
� High precision possible when trimmed
� No external components required

� This is the reset default.

External Crystal/
Resonator/
External Clock
Drive

� 0 to 20MHz
� Very high accuracy (dependent on
crystal/resonator or external source)
� Requires external components

� Configure Option Bits for correct

external oscillator mode

� Unlock and write Oscillator Control

� Wait for required stabilization time
� Unlock and write Oscillator Control

Internal Watchdog
Timer Oscillator

� 10KHz nominal
� Low accuracy
� No external components required
� Low power consumption

� Unlock and write Oscillator Control
Register (OSCCTL) to enable and select
Internal WDT oscillator

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P R E L I M I N A R Y Clock Failure Detection and Recovery for WDT

Z8FMC16100 Series Flash MCU

Product Specification

233

Watch-Dog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
Watch-Dog Timer is the primary oscillator.

The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz �+/-50%. For operating frequencies below 2KHz, do not enable the
clock failure circuitry (

POFEN

must be deasserted in the OSCCTL register).

Clock Failure Detection and Recovery for WDT Oscillator

In the event of a Watch-Dog Timer oscillator failure, a System Exception will be issued if
the

WDFEN

bit of the OSCCTL register is set. This event does not trigger an attendant clock

switch-over, but alerts the CPU of the failure. After a Watch-Dog Timer failure, it is no
longer possible to detect a primary oscillator failure.

The Watch-Dog Timer oscillator failure detection circuit counts system clocks while look-
ing for a Watch-Dog Timer clock. The logic counts 8000 system clock cycles before deter-
mining that a failure occurred. The system clock rate determines the speed at which the
Watch-Dog Timer failure can be detected. A very slow system clock results in very slow
detection times. If the Watch-Dog Timer is the primary oscillator or if the Watch-Dog
Timer oscillator is disabled, deassert the

WDFEN

bit of the OSCCTL register.

Oscillator Control Register

The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry, actively powers down the flash,
and selects the primary oscillator, which becomes the system clock.

The Oscillator Control Register must be unlocked before writing. Writing the two-step
sequence

E7H

followed by

18H

to the Oscillator Control Register address unlocks it. The

Table 130. Oscillator Control Register (OSCCTL)

BITS

FIELD

INTEN

XTLEN

WDTEN

POFEN

WDFEN

FLPEN

SCKSEL

RESET

R/W

R/W

ADDR

F86H

* The reset value is 1 if the option bit LPDEN is 0.

Oscillator Control

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Oscillator Divide Register

The Oscillator Divide Register (OSCDIV) provides the value that divides the system
clock. The Oscillator Divide Register must be unlocked before writing. Writing the two-
step sequence

E7h,

followed by

18h

, to the Oscillator Control Register address unlocks

the register. The register locks after completion of a register Write to the OSCDIV.

Bit

Position

Value

(H)

Description

[7]

INTEN

Internal Precision Oscillator Enable

Internal precision oscillator is disabled.

Internal precision oscillator is enabled.

[6]

XTLEN

Crystal Oscillator Enable

Crystal oscillator is disabled.

Crystal oscillator is enabled.

[5]

WDTEN

Watch-Dog Timer Oscillator Enable

Watch-Dog Timer oscillator is disabled

Watch-Dog Timer oscillator is enabled

[4]

POFEN

Primary Oscillator Failure Detection Enable

Failure detection and recovery of primary oscillator is disabled. This bit is cleared
automatically if a primary oscillator failure is detected.

Failure detection and recovery of primary oscillator is enabled

[3]

WDFEN

Watch-Dog Timer Oscillator Failure Detection Enable

Failure detection of Watch-Dog Timer oscillator is disabled.This bit is cleared
automatically if a Watch-Dog Timer oscillator failure is detected.

Failure detection of Watch-Dog Timer oscillator is enabled

[2]

FLPEN

Flash Low Power Mode Enable

Flash Low Power Mode is disabled.

Flash Low Power Mode is enabled. The Flash will be powered down during idle
periods of the clock and powered up during Flash reads. This bit should only be
set if the frequency of the primary oscillator source is 8MHz or lower. The reset
value of this bit is controlled by the LPDEN option bit during reset.

[1:0]

SCKSEL

System Clock Oscillator Select

Internal precision oscillator functions as system clock at 5.6 MHz

Crystal oscillator or external clock driver functions as system clock

Reserved

Watch-Dog Timer oscillator functions as system clock

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P R E L I M I N A R Y Crystal

Oscillator

Operation

Z8FMC16100 Series Flash MCU

Product Specification

237

On-Chip Oscillator

The products in the Z8FMC16100 Series Flash MCU features an on-chip oscillator for use
with external crystals with frequencies ranging from 32 KHz to 20 MHz. In addition, the
oscillator can support ceramic resonators with oscillation frequencies up to 20 MHz. This
oscillator generates the primary system clock for the internal eZ8 CPU and the majority of
the on-chip peripherals. Alternatively, the X

input pin can also accept a CMOS-level

clock input signal (32 KHz�20 MHz). If an external clock generator is used, the X

OUT

must remain unconnected.

When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the X

input pin determines the frequency of the system clock (that is, no

internal clock divider).

Crystal Oscillator Operation

Figure 40 illustrates a recommended configuration for connection with an external funda-
mental-mode, parallel-resonant crystal operating at 20 MHz. Recommended 20 MHz crys-
tal specifications are provided in Table 132. The printed circuit board layout must add no
more than 4 pF of stray capacitance to either the X

or X

OUT

pins. If oscillation does not

occur, reduce the values of capacitors C1 and C2 to decrease loading.

Figure 40. Recommended 20MHz Crystal Oscillator Configuration

C = 22 pF

OUT

C = 22 pF

20 MHz Crystal

(Fundamental Mode)

On-Chip Oscillator

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Z8FMC16100 Series Flash MCU

Product Specification

239

Internal Precision Oscillator

The Internal Precision Oscillator (IPO) is designed for use without external components.
The IPO comes factory trimmed a �4% frequency accuracy over the operating tempera-
ture and supply voltage range of the device. IPO features include:

�

On-chip RC oscillator that does not require external components

�

Trimmed to �4% accuracy

�

Target output frequency of 5.5296 MHz

�

Trimming possible through Flash option bits with user override

�

Can eliminate crystals or ceramic resonators in applications where high timing accura-
cy is not required.

Operation

The internal oscillator is an RC relaxation oscillator that has had its sensitivity to power
supply variation minimized. By using ratio tracking thresholds, the effect of power supply
voltage is cancelled out. The dominant source of oscillator error is the absolute variance of
chip-level fabricated components, such as capacitors. Two 8-bit trimming registers, incor-
porated into the design, allow compensation of absolute variation of oscillator frequency.
Once calibrated, the oscillator frequency is relatively stable and does not require subse-
quent calibration.

By default, the oscillator is configured through the Flash Option bits. However, the user
code can override these trim values as described in

Trim Option Bits

section on page 223.

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P R E L I M I N A R Y Architecture

Z8FMC16100 Series Flash MCU

Product Specification

241

On-Chip Debugger

The Z8FMC16100 Series Flash MCU device includes an integrated On-Chip Debugger
(OCD) that provides advanced debugging features, including:

�

Reading and writing of the Register File

�

Reading and writing of program and data memory

�

Setting of break points

�

Execution of eZ8 CPU instructions

Architecture

The On-Chip Debugger consists of four primary functional blocks: Transmitter, Receiver,
Autobaud Generator, and Debug Controller. Figure 41 illustrates the architecture of the
On-Chip Debugger.

OCD Interface

The On-Chip Debugger (OCD) uses the DBG pin for communication with an external
host. This one-pin interface is a bidirectional open-drain interface that transmits and

Figure 41. On-Chip Debugger Block Diagram

Autobaud

Detector/Generator

System

Clock

DBG Pin

Transmitter

Debug Controller

eZ8 CPU

Control

Receiver

On-Chip Debugger

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receives data. Data transmission is half-duplex, in that transmit and receive cannot occur
simultaneously. The serial data on the DBG pin is sent using the standard asynchronous
data format defined in RS-232. This pin interfaces the Z8FMC16100 Series Flash MCU
device to the serial port of a host PC using minimal external hardware. Two different
methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 42
and 43 .

For operation of the Z8FMC16100 Series Flash MCU, all power pins (V

and AV

)

must be supplied with power, and all ground pins (V

and AV

) must be properly

grounded. The DBG pin should always be connected to V

through an external pull-

up resistor.

Figure 42. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1)

Figure 43. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2)

Caution:

Diode

RS-232

Transceiver

DBG pin

10K

RS232 TX

RS232 RX

Open-Drain

Buffer

RS-232

Transceiver

DBG pin

10K

RS232 TX

RS232 RX

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P R E L I M I N A R Y Debug

Mode

Z8FMC16100 Series Flash MCU

Product Specification

243

Debug Mode

The operating characteristics of the Z8FMC16100 Series Flash MCU device in DEBUG
mode are:

�

The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions

�

The system clock operates unless in STOP mode

�

All enabled on-chip peripherals operate unless in STOP mode or otherwise defined by
the on-chip peripheral to disable in DEBUG mode

�

Automatically exits HALT mode

�

Constantly refreshes the Watch-Dog Timer, if enabled

Entering Debug Mode

The device enters DEBUG mode following any of the following operations:

�

Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface

�

eZ8 CPU execution of a BRK (break point) instruction (when enabled)

�

Match of PC to OCDCNTR register (when enabled)

�

OCDCNTR register decrements to

0000h

(when enabled)

�

The DBG pin is Low when the device exits Reset

Exiting Debug Mode

The device exits DEBUG mode following any of the following operations:

�

Clearing the DBGMODE bit in the OCD Control Register to 0

�

Power-on reset

�

Voltage Brown Out reset

�

Asserting the RESET pin Low to initiate a Reset

�

Driving the DBG pin Low while the device is in STOP mode initiates a System Reset

OCD Data Format

The On-Chip Debugger (OCD) interface uses the asynchronous data format defined for
RS-232. Each character is transmitted as 1 start bit, 8 data bits (least-significant bit first),
and 1 stop bit. See Figure 44.

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OCD Auto-Baud Detector/Generator

To run over a range of baud rates (bits per second) with various system clock frequencies,
the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character

80h

. The character

80h

contains eight continuous bits Low (one Start bit

plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud
Rate Generator accordingly.

The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud
rate is the system clock frequency divided by 512. The maximum recommended baud rate
is the system clock frequency divided by 8. Table 133 lists minimum and recommended
maximum baud rates for sample crystal frequencies.

If the OCD receives a Serial Break (ten or more continuous bits Low) the Auto-Baud
Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured
by sending

80h

. If the Auto-Baud Detector overflows while measuring the Auto-Baud

character, the Auto-Baud Detector will remain reset.

OCD Serial Errors

The On-Chip Debugger can detect any of the following error conditions on the DBG pin:

�

Serial Break (a minimum of ten continuous bits Low)

�

Framing Error (received STOP bit is Low)

Figure 44. OCD Data Format

Table 133. OCD Baud-Rate Limits

System Clock

Frequency

Maximum Asynchronous

Baud Rate (bits/s)

Minimum

Baud Rate (bits/s)

20.0 MHz

2.5 M

39.1 K

1.0 MHz

125 K

1960

32.768 KHz

4096

ST = Start Bit

SP = Stop Bit

D0--D7 = Data Bits

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P R E L I M I N A R Y Automatic

Reset

Z8FMC16100 Series Flash MCU

Product Specification

245

�

Transmit Collision (OCD and host simultaneous transmission detected by the OCD)

When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a Serial Break 4096 system clock cycles long back to the host, and resets the
Auto-Baud Detector/Generator. A Framing Error or Transmit Collision can be caused by
the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter-
face, returning a Serial Break break back to the host only extends the length of the Serial
Break if the host releases the Serial Break early.

The host transmits a Serial Break on the DBG pin when first connecting to the
Z8FMC16100 Series Flash MCU device or when recovering from an error. A Serial Break
from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Con-
trol Register. A Serial Break leaves the device in DEBUG mode if that is the current mode.
The OCD is held in Reset until the end of the Serial Break when the DBG pin returns
High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to
the OCD even if the OCD is transmitting a character.

Automatic Reset

The Z8FMC16100 Series Flash MCU devices have the capability to switch clock sources
during operation. If the Auto-Baud is set and the clock source is switched, the Auto-Baud
value becomes invalid. A new Auto-Baud value must be configured with the new clock
frequency.

The oscillator control logic has clock switch detection. If a clock switch is detected and
the Auto-Baud is set, the device will automatically send a Serial Break for 4096 clocks.
This will reset the Auto-Baud and indicate to the host that a new Auto-Baud character
should be sent.

Break Points

Execution break points are generated using the BRK instruction (Op Code

00h

). When the

eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If break points are
enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If break points are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as a NOP
instruction.

If break points are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU remains able to service DMA and interrupt requests.

The loop on BRK instruction can service interrupts in the background. For interrupts to be
serviced in the background, there cannot be any break points in the interrupt service rou-
tine. Otherwise, the CPU stops on the break point in the interrupt routine. For interrupts to
be serviced in the background, interrupts must also be enabled. Debugging software does
not automatically enable interrupts when using this feature. Interrupts are typically dis-

On-Chip Debugger

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abled during critical sections of code where interrupts do not occur (such as adjusting the
stack pointer or modifying shared data).

Host software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is
looping on a BRK instruction. When software wants to stop the CPU on the BRK instruc-
tion on which it is looping, software must not set the DBGMODE bit of the OCDCTL reg-
ister. The CPU may have vectored to an interrupt service routine. Instead, software clears
the BRKLP bit. This allows the CPU to finish the interrupt service routine it may be in and
return to the BRK instruction. When the CPU returns to the BRK instruction on which it
was previously looping, it automatically sets the DBGMODE bit and enters DEBUG
mode.

The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a
BRK instruction. The eZ8 CPU must be in DEBUG mode before these commands can be
issued.

Break Points in Flash Memory

The BRK instruction is Op Code

00h

, which corresponds to the fully programmed state of

a byte in Flash memory. To implement a break point, write

00h

to the appropriate address,

overwriting the current instruction. To remove a break point, erase the corresponding page
of Flash memory and reprogram with the original data.

OCDCNTR Register

The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used
for the following:

�

Count system clock cycles between break points

�

Generate a BRK when it counts down to 0

�

Generate a BRK when its value matches the Program Counter

When configured as a counter, the OCDCNTR register starts counting when the On-Chip
Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or
when it reaches the maximum count of

FFFFh

. The OCDCNTR register automatically

resets itself to

0000h

when the OCD exits DEBUG mode if it is configured to count clock

cycles between break points.

If the OCDCNTR Register is configured to generate a BRK when it counts down to zero,
it will not be reset when the CPU starts running. The counter will start counting down
toward zero once the On-Chip debugger leaves DEBUG mode. If the On-Chip Debugger
enters DEBUG mode before the OCDCNTR register counts down to zero, the OCDCNTR
will stop counting.

If the OCDCNTR register is configured to generate a BRK when the program counter
matches the OCDCNTR register, the OCDCNTR register will not be reset when the CPU

PS024604-1005

P R E L I M I N A R Y On-Chip

Debugger

Commands

Z8FMC16100 Series Flash MCU

Product Specification

247

resumes executing and it will not be decremented when the CPU is running. A BRK will
be generated when the program counter matches the value in the OCDCNTR register
before executing the instruction at the location of the program counter.

The OCDCNTR register is used by many of the OCD commands. It counts the number
of bytes for the register and memory read/write commands. It retains the residual value
when generating the CRC. If the OCDCNTR is used to generate a BRK, its value must
be written as a final step before leaving DEBUG mode.

Because this register is overwritten by various OCD commands, it must only be used to
generate temporary break points, such as stepping over CALL instructions or running to a
specific instruction and stopping.

When the OCDCNTR register is read, it returns the inverse of the data in this register. The
OCDCNTR register is only decremented when counting. The mode where it counts the
number of clock cycles in between execution is achieved by counting down from its max-
imum count. When the OCDCNTR register is read, the counter appears to have counted
up because its value is inverted. The value in this register is always inverted when it is
read. If this register is used as a hardware break point, the value read from this register will
be the inverse of the data actually in the register.

On-Chip Debugger Commands

The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In Debug mode, all OCD commands become available unless the user code is pro-
tected by programming the Read Protect option bit (

). The Read Protect option bit

prevents the code in memory from being read out of the Z8FMC16100 Series Flash MCU
device. When this option is enabled, several of the OCD commands are disabled. Table
134 contains a summary of the On-Chip Debugger commands. Each OCD command is
described in further detail in the bulleted list following Table 134. Table 134 indicates
those commands that operate when the device is not in DEBUG mode (normal operation)
and those commands that are disabled by programming the Read Protect option bit.

Table 134. On-Chip Debugger Commands

Debug Command

Command

Byte

Enabled When Not

In Debug Mode?

Disabled by Read Protect

Option Bit

Read Revision

00h

Yes

Write OCD Counter Register

01h

Read OCD Status Register

02h

Yes

Read OCD Counter Register

03h

Caution:

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In the following bulleted list of OCD Commands, data and commands sent from the host
to the On-Chip Debugger are identified by 'DBG

Command/Data'. Data sent from the

On-Chip Debugger back to the host is identified by 'DBG

Data'

Read Revision.

The Read Revision command returns the revision identifier. DBG

00h

DBG

REVID[15:8]

(Major revision number)

DBG

REVID[7:0]

(Minor revision number)

Write OCD Control Register

04h

Yes

Read OCD Control Register

05h

Yes

Write Program Counter

06h

Disabled

Read Program Counter

07h

Disabled

Write Register

08h

Writes to on-chip peripheral

registers are enabled. Writes to

the on-chip RAM are disabled.

Read Register

09h

Reads from on-chip peripheral

registers are enabled. Reads from

the on-chip RAM are disabled.

Write Program Memory

0Ah

Disabled

Read Program Memory

0Bh

Disabled

Write Data Memory

0Ch

Disabled

Read Data Memory

0Dh

Disabled

Read Program Memory CRC

0Eh

Reserved

0Fh

Step Instruction

10h

Disabled

Stuff Instruction

11H

Disabled

Execute Instruction

12H

Disabled

Read Baud Reload Register

1BH

Note: Unlisted command byte values are reserved.

Table 134. On-Chip Debugger Commands (Continued)

Debug Command

Command

Byte

Enabled When Not

In Debug Mode?

Disabled by Read Protect

Option Bit

PS024604-1005

P R E L I M I N A R Y On-Chip

Debugger

Commands

Z8FMC16100 Series Flash MCU

Product Specification

249

Write OCD Counter Register.

The Write OCD Counter Register command writes the

data that follows to the OCDCNTR register. If the device is not in DEBUG mode, the data
is discarded.

DBG

01h

DBG

OCDCNTR[15:8]

DBG

OCDCNTR[7:0]

Read OCD Status Register.

The Read OCD Status Register command reads the OCD-

STAT register.

DBG

02h

DBG

OCDSTAT[7:0]

Read OCD Counter Register.

The OCD Counter Register can be used to count system

clock cycles in between break points, generate a BRK when it counts down to 0, or gener-
ate a BRK when its value matches the Program Counter. Because this register is really a
down counter, the returned value is inverted when this register is read so the returned
result appears to be an up counter. If the device is not in DEBUG mode, this command
returns

FFFFh

DBG

03h

DBG

~OCDCNTR[15:8]

DBG

~OCDCNTR[7:0]

Write OCD Control Register.

The Write OCD Control Register command writes the data

that follows to the OCDCTL register.

DBG

04h

DBG

OCDCTL[7:0]

Read OCD Control Register.

The Read OCD Control Register command reads the value

of the OCDCTL register.

DBG

05h

DBG

OCDCTL[7:0]

Write Program Counter.

The Write Program Counter command writes the data that fol-

lows to the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if
the Read Protect option bit is enabled, the Program Counter (PC) values are discarded.

DBG

06h

DBG

ProgramCounter[15:8]

DBG

ProgramCounter[7:0]

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Read Program Counter.

The Read Program Counter command reads the value in the eZ8

CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect
option bit is enabled, this command returns

FFFFh

DBG

07h

DBG

ProgramCounter[15:8]

DBG

ProgramCounter[7:0]

Write Register.

The Write Register command writes data to the Register File. Data can be

written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If the
device is not in DEBUG mode, the address and data values are discarded. If the Read Pro-
tect option bit is enabled, then only writes to the on-chip peripheral registers are allowed
and all other register write data values are discarded.

DBG

08h

DBG

{4'h0,Register Address[11:8]}

DBG

Size[7:0]

DBG

1-256 data bytes

Read Register.

The Read Register command reads data from the Register File. Data can

be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the device
is not in DEBUG mode or if the Read Protect option bit is enabled and on-chip RAM is
being read from, this command returns

FFh

for all the data values.

DBG

09h

DBG

{4'h0,Register Address[11:8]

DBG

Size[7:0]

DBG

1-256 data bytes

Write Program Memory.

The Write Program Memory command writes data to Program

Memory. This command is equivalent to the LDC and LDCI instructions. Data can be
written 1�65536 bytes at a time (65536 bytes can be written by setting size to 0). The on-
chip Flash controller must be written to and unlocked for the programming operation to
occur. If the Flash controller is not unlocked, the data is discarded. If the device is not in
DEBUG mode or if the Read Protect option bit is enabled, the data is discarded.

DBG

0Ah

DBG

Program Memory Address[15:8]

DBG

Program Memory Address[7:0]

DBG

Size[15:8]

DBG

Size[7:0]

DBG

1-65536 data bytes

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Debugger

Commands

Z8FMC16100 Series Flash MCU

Product Specification

251

Read Program Memory.

The Read Program Memory command reads data from Program

Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read
1�65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not
in DEBUG mode or if the Read Protect option bit is enabled, this command returns

FFh

for the data.

DBG

0Bh

DBG

Program Memory Address[15:8]

DBG

Program Memory Address[7:0]

DBG

Size[15:8]

DBG

Size[7:0]

DBG

1-65536 data bytes

Write Data Memory.

The Write Data Memory command writes data to Data Memory.

This command is equivalent to the LDE and LDEI instructions. Data can be written 1�
65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is not
in DEBUG mode or if the Read Protect option bit is enabled, the data is discarded.

DBG

0Ch

DBG

Data Memory Address[15:8]

DBG

Data Memory Address[7:0]

DBG

Size[15:8]

DBG

Size[7:0]

DBG

1-65536 data bytes

Read Data Memory.

The Read Data Memory command reads from Data Memory. This

command is equivalent to the LDE and LDEI instructions. Data can be read 1�65536
bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in
DEBUG mode, this command returns

FFh

for the data.

DBG

0Dh

DBG

Data Memory Address[15:8]

DBG

Data Memory Address[7:0]

DBG

Size[15:8]

DBG

Size[7:0]

DBG

1-65536 data bytes

Read Program Memory CRC.

The Read Program Memory CRC command computes and

returns the CRC (cyclic redundancy check) of Program Memory using the 16-bit CRC-
CCITT polynomial (x

+ x

+ 1). The CRC is preset to all 1s. The least-significant

bit of the data is shifted through the polynomial first. The CRC is inverted when it is trans-
mitted. If the device is not in DEBUG mode, this command returns

FFFFh

for the CRC

value. Unlike most other OCD Read commands, there is a delay from issuing of the com-
mand until the OCD returns the data. The OCD reads the Program Memory, calculates the

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CRC value, and returns the result. The delay is a function of the Program Memory size and
is approximately equal to the system clock period multiplied by the number of bytes in the
Program Memory.

DBG

0Eh

DBG

CRC[15:8]

DBG

CRC[7:0]

Step Instruction.

The Step Instruction command steps one assembly instruction at the

current Program Counter (PC) location. If the device is not in DEBUG mode or the Read
Protect option bit is enabled, the OCD ignores this command.

DBG

10h

Stuff Instruction.

The Stuff Instruction command steps one assembly instruction and

allows specification of the first byte of the instruction. The remaining 0�4 bytes of the
instruction are read from Program Memory. This command is useful for stepping over
instructions where the first byte of the instruction has been overwritten by a break point. If
the device is not in DEBUG mode or the Read Protect option bit is enabled, the OCD
ignores this command.

DBG

11h

DBG

opcode[7:0]

Execute Instruction.

The Execute Instruction command allows sending an entire instruc-

tion to be executed to the eZ8 CPU. This command can also step over break points. The
number of bytes to send for the instruction depends on the Op Code. If the device is not in
DEBUG mode or the Read Protect option bit is enabled, the OCD ignores this command

DBG

12h

DBG

1-5 byte opcode

Read Baud Reload Register.

The Read Baud Reload Register command returns the cur-

rent value in the Baud Reload register.

DBG

1Bh

DBG

BAUD[15:8]

DBG

BAUD[7:0]

OCD Control Register

The OCD Control Register, shown in Table 135, controls the state of the On-Chip Debug-
ger. This register enters or exits DEBUG mode and enables the BRK instruction. It can
also reset the Z8FMC16100 Series Flash MCU.

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Control

Z8FMC16100 Series Flash MCU

Product Specification

253

A reset and stop function can be achieved by writing

81H

to this register. A reset and go

function is achieved by writing

41H

to this register. If the device is in DEBUG mode, a run

function is implemented by writing

40h

to this register.

A more detailed description of each bit follows the table.

DBGMODE--Debug Mode

Setting this bit to 1 causes the device to enter Debug mode. When in DEBUG mode, the
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to resume
execution. This bit is automatically set when a BRK instruction is decoded and Break-
points are enabled.

0 = The device is running (operating in NORMAL mode).

1 = The device is in DEBUG mode.

BRKEN--Breakpoint Enable

This bit controls the behavior of the BRK instruction (opcode

00H

). By default, Break-

points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a
BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.

0 = BRK instruction is disabled.

1 = BRK instruction is enabled.

DBGACK--Debug Acknowledge

This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
a Debug Acknowledge character (

FFH

) to the host when a Breakpoint occurs. This bit

automatically clears itself when an acknowledge character is sent.

0 = Debug Acknowledge is disabled.

1 = Debug Acknowledge is enabled.

BRKLOOP--Breakpoint Loop

This bit determines what action the OCD takes when a BRK instruction is decoded and
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically
set to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops
on the BRK instruction.

0 = BRK instruction sets DBGMODE to 1.

1 = eZ8 CPU loops on BRK instruction.

Table 135. OCD Control Register (OCDCTL)

BITS

FIELD

DBGMODE

BRKEN DBGACK

BRKLOOP

BRKPC

BRKZRO

Reserved

RST

RESET

R/W

R/W

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BRKPC--Break when PC == OCDCNTR

If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.

0 = OCDCNTR is setup as counter

1 = OCDCNTR generates hardware break when PC == OCDCNTR

BRKZRO--Break when OCDCNTR ==

0000H

If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCD-
CNTR register counts down to

0000H

. If this bit is set, the OCDCNTR register is not reset

when the part leaves DEBUG Mode.

0 = OCD does not generate BRK when OCDCNTR decrements to

0000H

1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to

0000H

Reserved--Must be 0.

RST--Reset

Setting this bit to 1 resets the device. The controller goes through a normal Power-On
Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is auto-
matically cleared to 0 when the reset finishes.

0 = No effect.

1 = Reset the device.

OCD Status Register

The OCD Status Register, shown in Table 136, reports status information about the current
state of the debugger and the system. A more detailed description of each bit follows the
table.

IDLE--CPU idle

This bit is set if the part is in Debug mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idle.

0 = The eZ8 CPU is running.

1 = The eZ8 CPU is either stopped or looping on a BRK instruction.

Table 136. OCD Status Register (OCDSTAT)

BITS

FIELD

IDLE

HALT

RPEN

Reserved

RESET

R/W

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Product

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Product Specification

257

Electrical Characteristics

The electrical characteristics of the Z8FMC16100 Series are described in the following
sections.

Precharacterization Product

The product represented by this document is newly introduced and ZiLOG has not com-
pleted the full characterization of the product. The document states what ZiLOG knows
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times, because of start-up yield issues.

Absolute Maximum Ratings

The ratings listed in Table 138 are stress ratings only. Operation of the device at any con-
dition outside those indicated in the operational sections of these specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. For improved reliability, unused inputs must be tied to one of the supply
voltages (V

or V

Stresses greater than those listed in Table 138 may cause permanent damage to the de-
vice.

Table 138. Absolute Maximum Ratings*

Parameter

Minimum Maximum

Units

Notes

Ambient temperature under bias

�40 +105

�C

Storage temperature

�65

+150

�C

Voltage on any pin with respect to V

�0.3

+5.5

Voltage on V

pin with respect to V

�0.3

+3.6

Maximum current on input and/or inactive output pin

�5

�A

Maximum output current from digital active output pin

�25

+25

Maximum output current from digital active output pin

�5

*Note: This voltage applies to all pins except V

and PC0.

Caution:

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DC Characteristics

Table 139 lists the DC characteristics of the Z8FMC16100 Series Flash MCU products.
All voltages are referenced to V

, the primary system ground.

32-pin LQFP Package Maximum Ratings at �40�C to 70�C

Total power dissipation

811

Maximum current into V

or out of V

225

32-pin LQFP Package Maximum Ratings at 70�C to 105�C

Total power dissipation

295

Maximum current into V

or out of V

32-pin QFN Package Maximum Ratings at �40�C to 70�C

Total power dissipation

1580

Maximum current into V

or out of V

439

32-pin QFN Package Maximum Ratings at 70�C to 105�C

Total power dissipation

575

Maximum current into V

or out of V

160

Table 139. DC Characteristics

Symbol Parameter

= �40�C to 105�C

Units Conditions

Minimum Typical

Maximum

Supply Voltage

2.7

3.6

IL1

Low Level Input Voltage

�0.3

0.3*V

For all input pins except
RESET, DBG, and X

IL2

Low Level Input Voltage

�0.3

0.2*V

For RESET, DBG, and
X

Notes:

1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.

Table 138. Absolute Maximum Ratings* (Continued)

Parameter

Minimum Maximum

Units

Notes

*Note: This voltage applies to all pins except V

and PC0.

PS024604-1005

P R E L I M I N A R Y DC

Characteristics

Z8FMC16100 Series Flash MCU

Product Specification

259

IH1

High Level Input Voltage

0.7 x V

5.5

Port pins when their
programmable pull-ups
are disabled. Except
PC0.

IH2

High Level Input Voltage

0.7 x V

+0.3

Port pins when their
programmable pull-ups
are enabled and PC0.

IH3

High Level Input Voltage

0.8 x V

+0.3

RESET, DBG, and X

pins.

OL1

Low Level Output Voltage

0.4

= 2mA; V

= 3.0V

High Output Drive
disabled.

OH1

High Level Output Voltage

2.4

= �2 mA; V

= 3.0V

High Output Drive
disabled.

OL2

Low Level Output Voltage
High Drive

0.6

= 20 mA; V

= 3.3V

High Output Drive
enabled; T

= �40�C to

+70�C

OH2

High Level Output Voltage
High Drive

2.4

= �20 mA; V

3.3V; High Output Drive
enabled; T

= �40�C to

+70�C

OL3

Low Level Output Voltage

High Drive

0.6

= 15mA; V

= 3.3V

High Output Drive
enabled; T

= +70�C to

+105�C.

OH3

High Level Output Voltage

High Drive

2.4

= 15mA; V

= 3.3V

High Output Drive
enabled; T

= +70�C to

+105�C.

RAM

RAM Data Retention

0.7

Input Leakage Current

�5

�A

= 3.3V;

= V

or V

Table 139. DC Characteristics (Continued)

Symbol Parameter

= �40�C to 105�C

Units Conditions

Minimum Typical

Maximum

Notes:

1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.

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Figure 45 illustrates the typical active mode current consumption while operating at 25�C,
3.3 V, versus the system clock frequency. All GPIO pins are configured as outputs and
driven High.

Figures 45 through 50 are not yet available. At this time, the Z8FMC16100 Series Flash
MCU is not fully characterized.

Tri-State Leakage Current

�5

�A

= 3.3V.

PU1

Weak Pull-up Current

�A

= 2.7�3.6V.

= 0�C to +70�C.

PU2

Weak Pull-up Current

�A

= 2.7�3.6V.

= �40�C to +105�C.

Idd
stop1

Chip leakage current in
STOP mode

STOP mode with VBO
disabled, WDT enabled.

Idd
stop2

Chip leakage current in
STOP mode

STOP mode with VBO
and WDT disabled.

Table 139. DC Characteristics (Continued)

Symbol Parameter

= �40�C to 105�C

Units Conditions

Minimum Typical

Maximum

Notes:

1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.

Note:

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Figure 50. Maximum Stop Mode I

with VBO Disabled vs. Supply Voltage

AC Characteristics

The section provides information on the AC characteristics and timing. All AC timing
information assumes a standard load of 50 pF on all outputs. Data in the typical column is
from characterization at 3.3 V and 25

�

C. These values are provided for design guidance

only and are not tested in production.

Table 140. AC Characteristics

Symbol

Parameter

= 2.7�3.6V

= �40�C to 105�C

Units Conditions

Minimum Maximum

SYSCLK

System clock frequency

20.0

MHz

XTAL

Crystal oscillator frequency

0.032768

20.0

MHz System clock frequencies

below the crystal oscillator
minimum require an external
clock driver.

XIN

System clock period

CLK

= 1 � F

SYSCLK

XINH

System clock high time

CLK

= 50 ns.

XINL

System clock low time

CLK

= 50 ns.

TBD

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Product Specification

265

On-Chip Peripheral AC and DC Electrical Characteristics

Table 141 provides electrical characteristics and timing information for the POR and VBO
circuits.

Table 141. POR and VBO Electrical Characteristics and Timing

Symbol

Parameter

= �40�C to 105�C

Units Conditions

Minimum

Typical

Maximum

POR

Power-on reset
voltage threshold

2.20

2.45

2.70

= V

POR

VBO

Voltage Brown-Out
reset voltage threshold

2.15

2.40

2.65

= V

VBO

POR

�V

VBO

Starting V

voltage to

ensure valid Power-On
Reset.

ANA

Power-On Reset
analog delay

> V

POR

; T

POR

Digital Reset delay
follows T

ANA

POR

Power-On Reset digital
delay

5.0

50 WDT Oscillator
cycles (10 KHz) + 16
System Clock cycles
(20 MHz).

VBO

Voltage Brown-Out
pulse rejection period

< V

VBO

to generate

a Reset.

RAMP

Time for V

transition from V

POR

to ensure valid

Reset

0.10

100

Supply current

500

�A

= 3.3 V.

Notes:

1. Data in the typical column is from characterization at 3.3V and 25

C. These values are provided for design guid-

ance only and are not tested in production.

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Table 142 provides electrical characteristics and timing information for the External RC
Oscillator.

Table 143 provides electrical characteristics and timing information for the Internal Preci-
sion Oscillator.

Table 142. External RC Oscillator Electrical Characteristics and Timing

Symbol

Parameter

= �40�C to 105�C

Units Conditions

Minimum

Typical

Maximum

Operating voltage
range

2.70

EXT

External resistance
from X

to V

200

K�

EXT

External capacitance
from X

to V

1000

OSC

External RC oscillation

frequency

MHz

Note:

1. When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below

2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscillation
as soon as the supply voltage exceeds 2.7V..

Table 143. Internal Precision Oscillator Electrical Characteristics and Timing

Symbol

Parameter

= �40�C to 105�C

Units Conditions

Minimum

Typical

Maximum

Output frequency

5.308

5.5296

5.75

MHz

Supply current

1.6

= 3.3 V.

Note:
1. The frequency is factory programmed.

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On-Chip Peripheral AC and DC Electrical

Z8FMC16100 Series Flash MCU

Product Specification

267

Table 144 provides electrical characteristics and timing information for the Watch-Dog
Timer.

Table 145 provides electrical characteristics and timing information for the Reset and
Stop-Mode Recovery functions.

Table 146 provides electrical characteristics and timing information for the Analog-to-
Digital Converter and illustrates the input frequency response of the ADC.

Table 144. Watch-Dog Timer Electrical Characteristics and Timing

Symbol Parameter

= 2.7�3.6V

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

OSC

Output frequency

KHz V

= 3.3 V.

Supply current

�A

= 3.3 V.

Table 145. Reset and Stop-Mode Recovery Pin Timing

Symbol Parameter

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

RESET

RESET pin assertion to
initiate a System Reset.

CLK

Not in STOP mode.

CLK

= System Clock

period.

SMR

Stop-Mode Recovery pin
pulse rejection period

RESET, DBG, and GPIO
pins configured as SMR
sources.

Table 146. Analog-to-Digital Converter Electrical Characteristics and Timing

Symbol Parameter

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

Resolution

bits

External V

REF

= 2.0 V.

Throughput conversion

CLKs ADC clock cycles.

ADCCLK frequency

MHz

DNL

Differential nonlinearity
for 8-bit use

�0.99

1.25

LSB 20 MHz sys clock with

ADC clock divided by 4

INL

Integral nonlinearity
for 8-bit use

�1.25

1.25

LSB 20 MHz sys clock with

ADC clock divided by 4

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Table 147 provides electrical characteristics and timing information for the on-chip Com-
parator.

DNL

Differential nonlinearity
for 10-bit

LSB 20 MHz sys clock with

ADC clock divided by 4

INL

Integral nonlinearity
for 10-bit

LSB 20 MHz sys clock with

ADC clock divided by 4

Offset error

�30

Gain error

�25

LSB

REF

On-chip voltage reference

1.9

2.1

Analog input voltage range

REF

Analog input current

500

Reference input current

2.0

Worst case code

Vref

External Vref voltage

2.5 V

Analog input capacitance

Operation supply voltage

2.7

3.6

Operating current, AV

9.0

At 20MHz ADC clock

Power-down current

< 1

�A

Table 147. Comparator Electrical Characteristics

Symbol Parameter

= 2.7�3.6V

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

COFF

Input offset

= 3.3 V;

= V

� 2.

CPROP

Propagation delay

200

Vcomm mode =1V
Vdiff=100mV

Input bias current

�A

CMVR

Common-mode voltage
range

�0.3

� 1

Supply current

�A

= 3.6V.

Table 146. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)

Symbol Parameter

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

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Table 148 provides electrical characteristics and timing information for the on-chip Oper-
ational Amplifier.

wup

Wake up time from off
state

�s

CINP = 0.9V
CINN= 1.0V

Table 148. Operational Amplifier Electrical Characteristics

Symbol Parameter

= 2.7�3.6V

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

Input offset

=3.3 V;

= V

� 2.

VOS

Input offset Average Drift

�V/C

Input bias current

TBD

Input offset current

TBD

CMVR

Common-Mode Voltage
Range

�0.3

� 1

Output low

0.1

SINK

= 100 �A.

Output high

� 1

SOURCE

= 100 �A.

CMRR

Common-Mode Rejection
Ratio

0 < V

< 1.4V;

= 25�C.

PSRR

Power Supply Rejection
Ratio

= 2.7 V � 3.6 V;

= 25�C.

VOL

Voltage Gain

SR+

Slew Rate while rising

V/us R

LOAD

= 33 K;

LOAD

= 50 pF;

VCL

= 1,

= 0.7 V to 1.7 V.

Table 147. Comparator Electrical Characteristics (Continued)

Symbol Parameter

(Continued) = 2.7�3.6V

= �40�C to 105�C

Units Conditions

Minimum

Typical Maximum

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General Purpose I/O Port Input Data Sample Timing

Figure 51 illustrates the timing of the GPIO Port input sampling. Table 149 lists the GPIO
port input timing.

Table 149 and Table 150 provide timing information for the GPIO Port inputs and outputs.

Figure 51. Port Input Sample Timing

Table 149. GPIO Port Input Timing

Parameter

Abbreviation

Delay (ns)

Min

Max

S_PORT

Port input transition to X

fall setup time

(Not pictured)

H_PORT

fall to port input transition hold time (not pictured).

SMR

GPIO port pin pulse width to ensure Stop-Mode
Recovery (for GPIO port pins enabled as SMR
sources) .

1 �s

CLK

System

Clock

GPIO Pin

Input Value

GPIO Input

Data Latch

GPIO Data

Read on Data Bus

Port Value

Changes to 0

0 Latched

into Port Input

Data Register

GPIO Data Register

Value 0 Read

by eZ8 CPU

Electrical Characteristics

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UART Timing

Figure 54 and Table 152 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.

Figure 54. UART Timing with CTS

Table 152. UART Timing with CTS

Parameter

Abbreviation

Delay (ns)

Minimum

Maximum

CTS fall to DE assertion delay

2 x X

period 2 x X

period

+ 1 bit period

DE assertion to TxD falling edge (start)
delay

1 bit period

1 bit period +

1 x X

period

End of stop bit(s) to DE deassertion delay 1 x X

period 2 x X

period

End of

Stop Bit(s)

CTS

(Input)

(Output)

TxD

(Output)

Bit 0

Bit 1

Bit 7

Stop

Parity

Start

� � �

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Figure 55 and Table 153 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data Register is writ-
ten with the next character before the current character has completed.

Figure 55. UART Timing without CTS

Table 153. UART Timing without CTS

Parameter

Abbreviation

Delay (ns)

Minimum

Maximum

DE assertion to TxD falling edge (start)
delay

1 bit period

1 bit period +

1 x X

period

End of stop bit(s) to DE deassertion delay 1 x X

period 2 x X

period

End of

Stop Bit(s)

(Output)

TxD

(Output)

Bit 0

Bit 1

Bit 7

Stop

Parity

Start

� � �

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eZ8 CPU Instruction Set

This chapter describes how to use the eZ8 CPU.

Assembly Language Programming Introduction

The eZ8 CPU assembly language provides a means for writing an application program
without concern for actual memory addresses or machine instruction formats. A program
written in assembly language is called a source program. Assembly language allows the
use of symbolic addresses to identify memory locations. It also allows mnemonic codes
(Op Codes and operands) to represent the instructions themselves. The Op Codes identify
the instruction while the operands represent memory locations, registers, or immediate
data values.

Each assembly language program consists of a series of symbolic commands called state-
ments. Each statement can contain labels, operations, operands and comments.

Labels can be assigned to a particular instruction step in a source program. The label iden-
tifies that step in the program as an entry point for use by other instructions.

The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the
assembly process.

The source program is processed (assembled) by the assembler to obtain a machine lan-
guage program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is detailed in the code below.

Assembly Language Source Program Example

JP START

; Everything after the semicolon is a comment.

START:

; A label called START. The first instruction (JP

START) in this

; example causes program execution to jump to the

point within the

; program where the START label occurs.

LD R4, R7

; A Load (LD) instruction with two operands. The

first operand,

; Working Register R4, is the destination. The

second operand,

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Assembly Language Syntax

For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as `destination, source'. After assembly, the object code usually has
the operands in the order 'source, destination', but ordering is Op Code-dependent. The
following instruction examples illustrate the format of some basic assembly instructions
and the resulting object code produced by the assembler. This binary format must be fol-
lowed by users that prefer manual program coding or intend to implement their own
assembler.

Example 1.

If the contents of registers

43h

and

08h

are added and the result is stored in

43h

, the assembly syntax and resulting object code is:

Example 2.

In general, when an instruction format requires an 8-bit register address, that

address can specify any register location in the range 0�255 or, using Escaped Mode
Addressing in working registers R0�R15. If the contents of Register

43h

and Working

43h

, the assembly syntax and resulting

object code is:

; Working Register R7, is the source. The contents

of R7 is

; written into R4.

LD 234H, #%01

; Another Load (LD) instruction with two operands.

; The first operand, Extended Mode Register Address

234H,

; identifies the destination. The second operand,

Immediate Data

; value 01h, is the source. The value 01h is

written into the

; Register at address 234h.

Assembly Language Code

ADD

43H,

08h

(ADD dst, src)

Object Code

(OPC src, dst)

Assembly Language Code

ADD

43H,

(ADD dst, src)

Object Code

(OPC src, dst)

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The size of the register file varies depending upon device type. The register file is 512
bytes for the Z8FMC16100 Series Flash MCU.

eZ8 CPU Instruction Notation

In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 154.

Table 154. Notational Shorthand

Notation Description

Operand Range

Bit

b represents a value from 0 to 7 (000b to 111b).

Condition Code

See Condition Codes overview in the eZ8 CPU
User Manual (UM0128).

Direct Address

Addrs

Addrs represents a number in the range of 0000h
to FFFFh.

Extended Addressing Register Reg

Reg. represents a number in the range of 000h to
FFFh.

Immediate Data

#Data

Data is a number between 00h to FFh.

Indirect Working Register

@Rn

n = 0 �15.

Indirect Register

@Reg

Reg. represents a number in the range of 00h to
FFh.

Irr

Indirect Working Register Pair

@RRp

p = 0, 2, 4, 6, 8, 10, 12, or 14.

IRR

Indirect Register Pair

@Reg

Reg. represents an even number in the range 00h
to FEh.

Polarity

Polarity is a single bit binary value of either 0b or
1b.

Working Register

n = 0�15.

Reg

Reg. represents a number in the range of 00h to
FFh.

Relative Address

X represents an index in the range of +127 to

�128, which is an offset relative to the address of
the next instruction.

Working Register Pair

RRp

p = 0, 2, 4, 6, 8, 10, 12, or 14.

Reg

Reg. represents an even number in the range of
00h to FEh.

Note:

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Table 155 contains additional symbols that are used throughout the Instruction Summary
and Instruction Set Description sections.

Assignment of a value is indicated by an arrow. For example,

dst

dst + src

indicates the source data is added to the destination data and the result is stored in the des-
tination location.

Vector

Vector Address

Vector

Vector represents a number in the range of 00h to
FFh.

Indexed

#Index

The register or register pair to be indexed is offset
by the signed Index value (#Index) in a +127 to �
128 range.

Table 155. Additional Symbols

Symbol

Definition

dst

Destination Operand

src

Source Operand

Indirect Address Prefix

Stack Pointer

Program Counter

FLAGS

Flags Register

Immediate Operand Prefix

Binary Number Suffix

Hexadecimal Number
Prefix

Hexadecimal Number
Suffix

Table 154. Notational Shorthand (Continued)

Notation Description

Operand Range

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Condition Codes

The C, Z, S, and V flags control the operation of the conditional jump (JP cc and JR cc)
instructions. Sixteen frequently-useful functions of the flag settings are encoded in a 4-bit
field called the condition code (cc), which forms Bits 7:4 of the conditional jump instruc-
tions. Table 156 summarizes the condition codes. Some binary condition codes can be cre-
ated using more than one assembly code mnemonic. The result of the flag test operation
decides whether the conditional jump is executed.

Table 156. Condition Codes

Binary

Hex

Assembly
Mnemonic

Definition

Flag Test Operation

0000

Always False

0001

Less Than

(S XOR V) = 1

0010

Less Than or Equal

(Z or (S XOR V)) = 1

0011

ULE

Unsigned Less Than or Equal (C OR Z) = 1

0100

Overflow

V = 1

0101

Minus

S = 1

0110

Zero

Z = 1

0110

Equal

Z = 1

0111

Carry

C = 1

0111

ULT

Unsigned Less Than

C = 1

1000

T (or blank)

Always True

1001

Greater Than or Equal

(S XOR V) = 0

1010

Greater Than

(Z OR (S XOR V)) = 0

1011

UGT

Unsigned Greater Than

(C = 0 AND Z = 0) = 1

1100

NOV

No Overflow

V = 0

1101

Plus

S = 0

1110

Non-Zero

Z = 0

1110

Not Equal

Z = 0

1111

No Carry

C = 0

1111

UGE

Unsigned Greater Than or
Equal

C = 0

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eZ8 CPU Instruction Classes

eZ8 CPU

instructions can be divided functionally into the following groups:

�

Arithmetic

�

Bit Manipulation

�

Block Transfer

�

CPU Control

�

Load

�

Logical

�

Program Control

�

Rotate and Shift

Tables 157 through 164 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one table
as these instruction can be considered as a subset of more than one category. Within these
tables, the source operand is identified as src, the destination operand is dst and a condi-
tion code is cc.

Table 157. Arithmetic Instructions

Mnemonic

Operands

Instruction

ADC

dst, src

Add with Carry

ADCX

dst, src

Add with Carry using extended addressing

ADD

dst, src

Add

ADDX

dst, src

Add using extended addressing

dst, src

Compare

CPC

dst, src

Compare with Carry

CPCX

dst, src

Compare with Carry using extended addressing

CPX

dst, src

Compare using extended addressing

dst

Decimal Adjust

DEC

dst

Decrement

DECW

dst

Decrement Word

INC

dst

Increment

INCW

dst

Increment Word

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MULT

dst

Multiply

SBC

dst, src

Subtract with Carry

SBCX

dst, src

Subtract with Carry using extended addressing

SUB

dst, src

Subtract

SUBX

dst, src

Subtract using extended addressing

Table 158. Bit Manipulation Instructions

Mnemonic

Operands

Instruction

BCLR

bit, dst

Bit Clear

BIT

p, bit, dst

Bit Set or Clear

BSET

bit, dst

Bit Set

BSWAP

dst

Bit Swap

CCF

Complement Carry Flag

RCF

Reset Carry Flag

SCF

Set Carry Flag

TCM

dst, src

Test Complement Under Mask

TCMX

dst, src

Test Complement Under Mask using extended
addressing

dst, src

Test Under Mask

TMX

dst, src

Test Under Mask using extended addressing

Table 159. Block Transfer Instructions

Mnemonic

Operands

Instruction

LDCI

dst, src

Load Constant to/from program memory and
autoincrement addresses

LDEI

dst, src

Load External Data to/from data memory and
autoincrement addresses

Table 157. Arithmetic Instructions (Continued)

Mnemonic

Operands

Instruction

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Table 160. CPU Control Instructions

Mnemonic

Operands

Instruction

CCF

Complement Carry Flag

Disable Interrupts

Enable Interrupts

HALT

HALT Mode

NOP

No Operation

RCF

Reset Carry Flag

SCF

Set Carry Flag

SRP

src

Set Register Pointer

STOP

STOP mode

WDT

Watch-Dog Timer Refresh

Table 161. Load Instructions

Mnemonic

Operands

Instruction

CLR

dst

Clear

dst, src

Load

LDC

dst, src

Load Constant to/from program memory

LDCI

dst, src

Load Constant to/from program memory and
autoincrement addresses

LDE

dst, src

Load External Data to/from data memory

LDEI

dst, src

Load External Data to/from data memory and
autoincrement addresses

LDWX

dst, src

Load Word using extended addressing

LDX

dst, src

Load using extended addressing

LEA

dst, X(src)

Load Effective Address

POP

dst

Pop

POPX

dst

Pop using extended addressing

PUSH

src

Push

PUSHX

src

Push using extended addressing

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Table 162. Logical Instructions

Mnemonic

Operands

Instruction

AND

dst, src

Logical AND

ANDX

dst, src

Logical AND using extended addressing

COM

dst

Complement

dst, src

Logical OR

ORX

dst, src

Logical OR using extended addressing

XOR

dst, src

Logical Exclusive OR

XORX

dst, src

Logical Exclusive OR using extended addressing

Table 163. Program Control Instructions

Mnemonic

Operands

Instruction

ATM

Atomic

BRK

On-Chip Debugger Break

BTJ

p, bit, src, DA

Bit Test and Jump

BTJNZ

bit, src, DA

Bit Test and Jump if Non-Zero

BTJZ

bit, src, DA

Bit Test and Jump if Zero

CALL

dst

Call Procedure

DJNZ

dst, src, RA

Decrement and Jump Non-Zero

IRET

Interrupt Return

dst

Jump

JP cc

dst

Jump Conditional

Jump Relative

JR cc

Jump Relative Conditional

RET

Return

TRAP

vector

Software Trap

Table 164. Rotate and Shift Instructions

Mnemonic

Operands

Instruction

BSWAP

dst

Bit Swap

dst

Rotate Left

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eZ8 CPU Instruction Summary

Table 165 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags Register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.

RLC

dst

Rotate Left through Carry

dst

Rotate Right

RRC

dst

Rotate Right through Carry

SRA

dst

Shift Right Arithmetic

SRL

dst

Shift Right Logical

SWAP

dst

Swap Nibbles

Table 165. eZ8 CPU Instruction Summary

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

ADC dst, src

dst

dst + src + C

ADCX dst, src

dst

dst + src + C

ER ER

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

Table 164. Rotate and Shift Instructions (Continued)

Mnemonic

Operands

Instruction

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ADD dst, src

dst

dst + src

ADDX dst, src

dst

dst + src

ER ER

AND dst, src

dst

dst + src

-- *

0 -- --

ANDX dst, src

dst

dst AND src

ER ER

-- *

0 -- --

ATM

Atomic execution

-- -- -- -- -- --

BCLR bit, dst

dst[bit]

-- *

0 -- --

BIT p, bit, dst

dst[bit]

-- *

0 -- --

BRK

Debugger Break

-- -- -- -- -- --

BSET bit, dst

dst[bit]

-- *

0 -- --

BSWAP dst

dst[7:0]

dst[0:7]

BTJ p, bit, src,
dst

if src[bit] = p

PC + X

-- -- -- -- -- --

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

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BTJNZ bit, src,
dst

if src[bit] = 1

PC + X

-- -- -- -- -- --

BTJZ bit, src,
dst

if src[bit] = 0

PC + X

-- -- -- -- -- --

CALL dst

SP � 2

@SP

dst

IRR

-- -- -- -- -- --

CCF

* -- -- -- -- --

CLR dst

dst

00h

-- -- -- -- -- --

COM dst

dst

~dst

-- *

0 -- --

CP dst, src

dst � src

* -- --

CPC dst, src

dst � src � C

1F A2

* -- --

1F A3

1F A4

1F A5

1F A6

1F A7

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

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CPCX dst, src

dst � src � C

ER ER

1F A8

* -- --

1F A9

CPX dst, src

dst � src

ER ER

* -- --

DA dst

dst

DA(dst)

X -- --

DEC dst

dst

dst � 1

-- *

v --

DECW dst

dst

dst � 1

-- *

* -- --

IRR

IRQE

-- -- -- -- -- --

DJNZ dst, RA

dst

dst � 1

if dst

PC + X

0A�FA

-- -- -- -- -- --

IRQE

-- -- -- -- -- --

HALT

HALT Mode

-- -- -- -- -- --

INC dst

dst

dst + 1

-- *

* -- --

0E�FE

INCW dst

dst

dst + 1

-- *

* -- --

IRR

IRET

FLAGS

@SP

SP + 1

@SP

SP + 2

IRQE

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

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JP dst

dst

-- -- -- -- -- --

IRR

JP cc, dst

if cc is true

dst

0D�FD

-- -- -- -- -- --

JR dst

PC + X

-- -- -- -- -- --

JR cc, dst

if cc is true

PC + X

0B�FB

-- -- -- -- -- --

LD dst, rc

dst

src

0C�FC

-- -- -- -- -- --

X(r)

LDC dst, src

dst

src

Irr

-- -- -- -- -- --

Irr

LDCI dst, src

dst

src

r + 1

rr + 1

Irr

-- -- -- -- -- --

Irr

LDE dst, src

dst

src

Irr

-- -- -- -- -- --

Irr

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

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LDEI dst, src

dst

src

r + 1

rr + 1

Irr

-- -- -- -- -- --

Irr

LDWX dst, src

dst

src

ER ER

1F E8

-- -- -- -- -- --

LDX dst, src

dst

src

-- -- -- -- -- --

IRR

IR IRR

X(rr)

IRR

IRR IR

ER ER

LEA dst, X(src) dst

src + X

X(r)

-- -- -- -- -- --

rr X(rr)

MULT dst

dst[15:0]

dst[15:8] * dst[7:0]

-- -- -- -- -- --

NOP

No operation

-- -- -- -- -- --

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

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OR dst, src

dst

dst OR src

-- *

0 -- --

ORX dst, src

dst

dst OR src

ER ER

-- *

0 -- --

POP dst

dst

@SP

SP + 1

-- -- -- -- -- --

POPX dst

dst

@SP

SP + 1

-- -- -- -- -- --

PUSH src

SP � 1

@SP

src

-- -- -- -- -- --

1F 70

PUSHX src

SP � 1

@SP

src

-- -- -- -- -- --

RCF

0 -- -- -- -- --

RET

@SP

SP + 2

-- -- -- -- -- --

RL dst

* -- --

RLC dst

* -- --

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

D7 D6 D5 D4 D3 D2 D1 D0

dst

D7 D6 D5 D4 D3 D2 D1 D0

dst

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P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8FMC16100 Series Flash MCU

Product Specification

293

RR dst

* -- --

RRC dst

* -- --

SBC dst, src

dst

dst � src � C

SBCX dst, src

dst

dst � src � C

ER ER

SCF

1 -- -- -- -- --

SRA dst

0 -- --

SRL dst

1F C0

* -- --

1F C1

SRP src

src

-- -- -- -- -- --

STOP

STOP mode

-- -- -- -- -- --

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

D7 D6 D5 D4 D3 D2 D1 D0

dst

D7 D6 D5 D4 D3 D2 D1 D0

dst

D7 D6 D5 D4 D3 D2 D1 D0

dst

D7 D6 D5 D4 D3 D2 D1 D0

dst

PS024604-1005

P R E L I M I N A R Y

eZ8 CPU Instruction Set

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Motor Control Flash MCUs

Product Specification

294

SUB dst, src

dst

dst � src

SUBX dst, src

dst

dst � src

ER ER

SWAP dst

dst[7:4]

dst[3:0]

X -- --

TCM dst, src

(NOT dst) AND src

-- *

0 -- --

TCMX dst, src

(NOT dst) AND src

ER ER

-- *

0 -- --

TM dst, src

dst AND src

-- *

0 -- --

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

PS024604-1005

P R E L I M I N A R Y

eZ8 CPU Instruction Set

Z8FMC16100 Series Flash MCU

Product Specification

295

Flags Register

The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z,
and S) can be tested for use with conditional jump instructions. Two flags (H and D) can-
not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.

The two remaining bits, User Flags (F1 and F2), are available as general-purpose status
bits. User Flags are unaffected by arithmetic operations and must be set or cleared by
instructions. The User Flags cannot be used with conditional Jumps. They are undefined at

TMX dst, src

dst AND src

ER ER

-- *

0 -- --

TRAP Vector

SP � 2

@SP

SP � 1

@SP

FLAGS

@Vector

Vect

-- -- -- -- -- --

WDT

-- -- -- -- -- --

XOR dst, src

dst

dst XOR src

-- *

0 -- --

XORX dst, src

dst

dst XOR src

ER ER

-- *

0 -- --

Table 165. eZ8 CPU Instruction Summary (Continued)

Assembly

Mnemonic

Symbolic Operation

Address

Mode

Code(s)

(Hex)

Flags

Fetch

Cycles

Instr.

Cycles

dst src

C Z S V D H

Note: Flags Notation:

* = Value is a function of the result of the operation.
� = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.

PS024604-1005

P R E L I M I N A R Y Op

Code

Maps

Z8FMC16100 Series Flash MCU

Product Specification

297

Op Code Maps

Figure 57 and Table 166 provide descriptions of the Op Code map data and the abbrevia-
tions. Figures 58 and 59 provide information about each of the eZ8 CPU instructions.

Figure 57. Op Code Map Cell Description

Table 166. Op Code Map Abbreviations

Abbreviation

Description

Abbreviation

Description

Bit position

IRR

Indirect Register Pair

Condition code

Polarity (0 or 1)

8-bit signed index or
displacement

4-bit Working Register

Destination address

8-bit register

Extended Addressing register

r1, R1, Ir1, Irr1, IR1,
rr1, RR1, IRR1, ER1

Destination address

Immediate data value

r2, R2, Ir2, Irr2, IR2,
rr2, RR2, IRR2, ER2

Source address

Indirect Working Register

Relative

Indirect register

Working Register Pair

Irr

Indirect Working Register Pair RR

Fetch Cycles

Instruction Cycles

First Operand

After Assembly

Op Code

Upper Nibble

Op Code

Lower Nibble

3.3

R2,R1

Second Operand

After Assembly

PS024604-1005

P R E L I M I N A R Y Op

Code

Maps

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Figure 58. First Op Code Map

3.3

R2,R1

3.4

IR2,R1

2.3

r1,r2

2.4

r1,Ir2

CPX

4.3

ER2,ER1

CPX

4.3

IM,ER1

3.3

R1,IM

3.4

IR1,IM

RRC

2.2

RRC

2.3

IR1

Lower Nibble (Hex)

per

bbl

e (

)

BRK

1.1

SRP

2.2

ADD

2.3

r1,r2

ADD

2.4

r1,Ir2

ADD

3.3

R2,R1

ADD

3.4

IR2,R1

ADD

3.3

R1,IM

ADD

3.4

IR1,IM

ADDX

4.3

ER2,ER1

ADDX

4.3

IM,ER1

DJNZ

2.3

r1,X

2.2

cc,X

2.2

r1,IM

3.2

cc,DA

INC

1.2

NOP

1.2

RLC

2.2

RLC

2.3

IR1

ADC

2.3

r1,r2

ADC

2.4

r1,Ir2

ADC

3.3

R2,R1

ADC

3.4

IR2,R1

ADC

3.3

R1,IM

ADC

3.4

IR1,IM

ADCX

4.3

ER2,ER1

ADCX

4.3

IM,ER1

INC

2.2

INC

2.3

IR1

SUB

2.3

r1,r2

SUB

2.4

r1,Ir2

SUB

3.3

R2,R1

SUB

3.4

IR2,R1

SUB

3.3

R1,IM

SUB

3.4

IR1,IM

SUBX

4.3

ER2,ER1

SUBX

4.3

IM,ER1

DEC

2.2

DEC

2.3

IR1

SBC

2.3

r1,r2

SBC

2.4

r1,Ir2

SBC

3.3

R2,R1

SBC

3.4

IR2,R1

SBC

3.3

R1,IM

SBC

3.4

IR1,IM

SBCX

4.3

ER2,ER1

SBCX

4.3

IM,ER1

2.2

2.3

IR1

2.3

r1,r2

2.4

r1,Ir2

3.3

R2,R1

3.4

IR2,R1

3.3

R1,IM

3.4

IR1,IM

ORX

4.3

ER2,ER1

ORX

4.3

IM,ER1

POP

2.2

POP

2.3

IR1

AND

2.3

r1,r2

AND

2.4

r1,Ir2

AND

3.3

R2,R1

AND

3.4

IR2,R1

AND

3.3

R1,IM

AND

3.4

IR1,IM

ANDX

4.3

ER2,ER1

ANDX

4.3

IM,ER1

COM

2.2

COM

2.3

IR1

TCM

2.3

r1,r2

TCM

2.4

r1,Ir2

TCM

3.3

R2,R1

TCM

3.4

IR2,R1

TCM

3.3

R1,IM

TCM

3.4

IR1,IM

TCMX

4.3

ER2,ER1

TCMX

4.3

IM,ER1

PUSH

2.2

PUSH

2.3

IR2

2.3

r1,r2

2.4

r1,Ir2

3.3

R2,R1

3.4

IR2,R1

3.3

R1,IM

3.4

IR1,IM

TMX

4.3

ER2,ER1

TMX

4.3

IM,ER1

DECW

2.5

RR1

DECW

2.6

IRR1

LDE

2.5

r1,Irr2

LDEI

2.8

Ir1,Irr2

LDX

3.2

r1,ER2

LDX

3.3

Ir1,ER2

LDX

3.4

IRR2,R1

LDX

3.5

IRR2,IR1

LDX

3.4

r1,rr2,X

LDX

3.4

rr1,r2,X

2.2

2.3

IR1

LDE

2.5

r2,Irr1

LDEI

2.8

Ir2,Irr1

LDX

3.2

r2,ER1

LDX

3.3

Ir2,ER1

LDX

3.4

R2,IRR1

LDX

3.5

IR2,IRR1

LEA

3.3

r1,r2,X

LEA

3.5

rr1,rr2,X

INCW

2.5

RR1

INCW

2.6

IRR1

CLR

2.2

CLR

2.3

IR1

XOR

2.3

r1,r2

XOR

2.4

r1,Ir2

XOR

3.3

R2,R1

XOR

3.4

IR2,R1

XOR

3.3

R1,IM

XOR

3.4

IR1,IM

XORX

4.3

ER2,ER1

XORX

4.3

IM,ER1

LDC

2.5

r1,Irr2

LDCI

2.8

Ir1,Irr2

LDC

2.5

r2,Irr1

LDCI

2.8

Ir2,Irr1

2.3

IRR1

LDC

2.8

Ir1,Irr2

3.4

r1,r2,X

PUSHX

3.3

ER2

SRA

2.2

SRA

2.3

IR1

POPX

3.3

ER1

3.4

r2,r1,X

CALL

2.6

IRR1

BSWAP

2.2

CALL

3.3

3.2

R2,R1

3.3

IR2,R1

BIT

2.2

p,b,r1

2.3

r1,Ir2

LDX

4.2

ER2,ER1

LDX

4.2

IM,ER1

3.3

R1,IM

3.4

IR1,IM

2.2

2.3

IR1

MULT

2.9

RR1

3.3

R2,IR1

TRAP

2.6

Vector

2.3

Ir1,r2

BTJ

3.3

p,b,r1,X

BTJ

3.4

p,b,Ir1,X

SWAP

2.2

SWAP

2.3

IR1

RCF

1.2

WDT

1.2

STOP

1.2

HALT

1.2

RET

1.4

IRET

1.5

SCF

1.2

CCF

1.2

Op Code

See 2nd

Map

ATM

1.1

PS024604-1005

P R E L I M I N A R Y Ordering

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302

Ordering Information

Table 167 identifies the basic features available for each device within the Z8FMC16100
Series Flash MCU product line. Table 168 provides ordering information for these prod-
ucts by part number. See the

Part Number Description

section on page 304 for a descrip-

tion of a part number's unique identifying attributes.

Each of the parts listed in Table 168 is shown in a lead-free package. The use of lead-free
packaging adheres to a socially responsible environmental standard. To order the standard
plastic (lead-soldered) package, please contact

ZiLOG Customer Service

Table 167. Z8FMC16100 Series Part Selection Guide

Product Feature

Z8FMC16100 Z8FMC08100 Z8FMC04100

Flash (KB)

SRAM (B)

512

General-Purpose I/O

Motor Control PWM Channels

ADC Inputs

Operational Amplifier

Yes

Comparator

Yes

16-bit Standard Timers w/ Capture, Compare, PWM

Yes

UART with support for LIN, and IrDA

Yes

C or SPI Controller

Yes

Watch-Dog Timer

Yes

5.5296 MHz Internal Precision Oscillator

Yes

Z8FMC16100

Yes

PS024604-1005

P R E L I M I N A R Y Ordering

Information

Z8FMC16100 Series Flash MCU

Product Specification

303

Navigate your browser to ZiLOG's website to order the Z8FMC16100 Series Flash MCU.
Or, contact your local

ZiLOG Sales Office

. ZiLOG provides additional assistance on its

Customer Service

page, and is also here to help with

Technical Support

issues. For

ZILOG's valuable

development tools and downloadable software

, visit the

ZiLOG web-

site

Table 168. Ordering Information for the Z8FMC16100 Series Products*

Part Number

Flash KB

(Bytes)

SRAM

Bytes GPIO

Max.

Speed

(MHz)

C/SPI

Trimmed

IPO

Package

Temp (�C)

Z8FMC16100 with 16 KB Flash and 512 B SRAM

Z8FMC16100QKSG

(16,384)

512

C/SPI

QFN-32

to +70

Z8FMC16100QKEG

�40

to +105

Z8FMC16100AKSG

(16,384)

512

C/SPI

LQFP-32

to +70

Z8FMC16100AKEG

�40

to +105

Z8FMC08100 with 8 KB Flash and 512 B SRAM

Z8FMC08100QKSG

8 (8,192)

512

C/SPI

QFN-32

to +70

Z8FMC08100QKEG

�40

to +105

Z8FMC08100AKSG

8 (8,192)

512

C/SPI

LQFP-32

to +70

Z8FMC08100AKEG

�40

to +105

Z8FMC04100 with 4 KB Flash and 512 B SRAM

Z8FMC04100QKSG

4 (4,096)

512

C/SPI

QFN-32

to +70

Z8FMC04100QKEG

�40

to +105

Z8FMC04100AKSG

4 (4,096)

512

C/SPI

LQFP-32

to +70

Z8FMC04100AKEG

�40

to +105

Z8FMC16100 Series Development Kit

Z8FMC160100KIT

Z8FMC16100

Series Development Kit

Z8FMC161000ZEM

Z8 Encore! Z8FMC16100 Series In-Circuit Emulator Development Tool

ZUSBOPTSC01ZAC USB Opto-isolated Smart Cable Accessory Kit

*Note: Factory-programmed versions of the devices in this table are available upon request from ZiLOG.

PS024604-1005

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Part Number Description

ZiLOG part numbers consist of a number of components, as indicated in the following
examples:

Example

Part number Z8FMC16100QKSG is a 16-bit Flash Motor Controller with 16 KB Program
Memory in a QFN package with 32 pins, operating over a 0�C to +70�C temperature range
and built using lead-free solder.

Precharacterization Product

ZiLOG 8-bit microcontroller product

FMC

Flash Motor Controller

Memory size

100

Product family

Package type

Pin count

Temperature

Environmental flow*

Note: *An environmental flow of G represents the lead-
free packaging option.

Packages

A = LQFP

Q = QFN

Pin Count

K = 32 pins

Temperature

E = �40�C to +105�C

S = 0�C to +70�C

Environmental Flow

C = Plastic Standard

G = Lead-Free

PS024604-1005

P R E L I M I N A R Y Document

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Change Log

Rev

Date

Sections

April
2005

Original issue

August
2005

Revised GPIO count and packages. Updated Figure 60 on page 301.

Added 8K (FMC08100) and 4K (FMC04100) parts to the

Z8FMC16100 Series Flash MCU

Features

section on page 1,

Block Diagram

section on page 2,

Program Memory

section on

page 14,

Program Memory

chapter on page 211, and

Ordering Information

section on page

302 for CR 6264.

Added USB Opto-isolated Smart Cable Accessory Kit to

Ordering Information

section on page

302.

Removed Sample and Hold from

Block Diagram

section on page 2 and

Ordering Information

section on page 302. Updated Figure 36 on page 200. Replaced "Current-Sense Sample and
Hold Control Register" section with

Current Sense ADC Trigger Control Register

section on

page 87.

Removed "Operational Amplifier" chapter for CR 6261.

Updated

Z8FMC16100 Series Flash MCU Features

section on page 1 for CR 6262.

Updated

General-Purpose I/O

chapter on page 35.

Updated

Watch-Dog Timer

chapter on page 63.

Updated

Pulse-Width Modulator

chapter on page 67.

Updated

General-Purpose Timer

chapter on page 91.

Updated

I2C Master/Slave Controller

chapter on page 163.

Updated

Internal Precision Oscillator

chapter on page 239.

Updated

Electrical Characteristics

chapter on page 257.

Updated all register tables throughout manual.

Added

Appendix A--Register Tables

on page 307.

Added the number of interrupts to

Z8FMC16100 Series Flash MCU Features

on page 1 and

the

Interrupt Controller

chapter on page 51 for CR 6305.

Updated Table 108 on page 206, Table 109 on page 207, and Table 130 on page 233 for CR
6382.

Septem-
ber 2005

Updated Figure 1 on page 2.

October
2005

Updated the

chapter on page 17. Updated Table 43 on page 76,

Table 54 on page 85, and Table 168 on page 303. Updated the

Electrical Characteristics

chapter on page 257.

PS024604-1005

P R E L I M I N A R Y

Appendix A--Register Tables

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[6�5]

TICONFIG

Timer Interrupt Configuration--This field configures timer interrupt definitions.
These bits affect all modes. The effect per mode is explained below:

GATED:
0x Timer interrupt occurs on reload or inactive gate edge.
10 Timer interrupt occurs on inactive gate edge.
11 Timer interrupt occurs on reload.

CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART:
0x Timer interrupt occurs on reload and capture.
10 Timer interrupt occurs on capture only.
11 Timer interrupt occurs on reload only

[4]

TINSEL

Timer Input Select

Timer input is the Timer input pin.

Timer input is the comparator output.

[3�1]
PWMD

000

001

010

011

100

101

110

111

No delay

2 cycles delay

4 cycles delay

8 cycles delay

16 cycles delay

32 cycles delay

64 cycles delay

128 cycles delay

[0]

INCAP

Input Capture Event
Previous timer interrupt is not a result of a Timer Input Capture Event

Previous timer interrupt is a result of a Timer Input Capture Event.

Bit

Position

Value

(H)

Description

PS024604-1005

P R E L I M I N A R Y

Appendix A--Register Tables

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