CP00300-TVX0698
1
P
RELIMINARY
D
ATA
S
HEET
Z90231/233/234/239
1
Z8 D
IGITAL
T
ELEVISION
C
ONTROLLERS
FEATURES
Z8-Based CMOS Microcontroller for Consum-
er Television, Cable Box, and Satellite Re-
ceiver Applications
42-Pin SDIP Package except Z90239 (124 PGA)
Z8
MCU Core at 6 MHz
Mask ROM sizes Available in 16 and 24KB
Ten 6-bit Pulse Width Modulators
One 14-bit Pulse Width Modulator
On-Chip Infrared (IR) Capture Registers
Four Channel 4-bit Analog-to-Digital Converter
Twenty Seven General Purpose I/O Pins
I
2
C Master Serial Communication Port
On Screen Display (OSD) Section
Supports Displays up to 10 rows by 24 Columns with
256 Characters
Character Cell Resolution of 14 Pixels by 18 Scan lines
Variable Inter-row Spacing from 015 Horizontal Scan
Lines
Foreground and Background Colors Fully Programma-
ble by Character
GENERAL DESCRIPTION
The Z9023X Digital Television Controller (DTC) family is
ZiLOG's latest and most powerful Z8-based DTC product
offering. These parts feature larger system RAM and ROM
options, together with a host of new features including a new
color palette system, flexible inter-row spacing, higher
character cell resolution, background mesh effect, dedicated
I.R. capture registers, on-chip Analog-to-Digital conver-
sion, and a hardware Master mode I
2
C interface. The famil-
iar Z8 core in combination with these advanced features
makes the Z9023X family an ideal choice for low to mid-
range televisions in both PAL and NTSC markets.
The Z9023X family consists of three basic device types; ICE
Chip (Z90239), ROM Mask Parts (Z90233/Z90234), and
OTP Part (Z90231). The OTP (Z90231) supports field pro-
grammable 32KB system ROM. ICE Chip (Z90239) is used
in Z90239 Emulator and ProtoPak. As described above,
Z90233 supports 16KB system ROM and Z90234 supports
24KB system ROM for mask.
The Z9021X family takes full advantage of the Z8's ex-
panded register file space to offer greater flexibility in On
Screen Display creation.
Note:
All signals with an overline, " ", are active Low. For ex-
ample, B/
: (WORD is active Low, only); %/W (BYTE
is active Low, only).
Device
ROM
(KB)
RAM
(Bytes)
I/O
Lines
1
Voltage
Range
Z90231
32(OTP)
236
27
4.5V to 5.5V
Z90233
16
236
27
4.5V to 5.5V
Z90234
24
236
27
4.5V to 5.5V
Z90239
32(ext.)
236
27
4.5V to 5.5V
Note:
+V EQWPVU CNN OWZGF +1 RQTV
Part_Number
Z8 Digital Television Controllers
ZiLOG
2
P R E L I M I N A R Y
CP00300-TVX0698
GENERAL DESCRIPTION (Continued)
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS,
AV
SS
Figure 1. Functional Block Diagram
-
2TQITCO 41/
< %27
%QTG
4'5'6
1UEKNNCVQT
9&6
%QWPVGT
6KOGT
%QWPVGT
6KOGT
DKV
#&%
+4
%QWPVGT
2QTV
$[VG
4GIKUVGT (KNG
2QTV
2QTV
1P 5ETGGP
&KURNC[
D[ DKV
%JCTCEVGT 4#/
- D[ DKV
%JCTCEVGT 41/
29/
29/
VQ
29/
DKV
DKV
:6#.
:6#.
4'5'6
#&%
#&%
#&%
#&%
+4+0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
15&:
15&:
*5[PE
85[PE
4
)
$
8$NCPM
29/
29/
29/
29/
29/
29/
29/
29/
29/
29/
29/
D[ DKV
5%.-
5#
+
%
2
2
2
2
2
2
2
1WVRWV
2QTV
+PVGTHCEG
5%.-
5#
*.(60
$[VG
Z90231/233/234/239
ZiLOG
Z8 Digital Television Controllers
CP00300-TVX0698
P R E L I M I N A R Y
3
PIN IDENTIFICATION
Figure 2. 42-Pin SIDP Pin Identification
29/2
29/2
29/2
29/2
29/2
29/2
29/2
2
2#&%
2#&%
2#&%
2#&%
#855
2
2
2
229/
229/
229/
229/
2*.(60
25#
25%.-
25#
25%.-
2
2
+4+0
2
8
&&
4'5'6
:6#.
:6#.
855
15&:
15&:
85;0%
*5;0%
8$.#0-
4
)
$
<Z
6QR 8KGY
Part_Number
Z8 Digital Television Controllers
ZiLOG
4
P R E L I M I N A R Y
CP00300-TVX0698
PIN IDENTIFICATION (Continued)
Table 1. Z90231/233/234 42-Pin SDIP Package
Pin Number
Pin Function
I/O/PWR
Reset State
Name
Note
34
+5 Volts
PWR
PWR
V
DD
30,13
0 Volts
PWR
PWR
V
SS
, AV
SS
36
Infra Red remote capture input
I
I
IRIN
1
14-bit Pulse Width Modulator output
O
I
PWM11
1
20,19,18,17,2,3,4,5,6,7
6-bit Pulse Width Modulator output
O
I
PWM[10:1]
1
7,6,5,4,3,2,1
Bit Programmable Input/Output ports
I/O
I
P5[6:0]
42,41,40,39,38,37,35,21
Bit programmable Input/Output ports
I/O
I
P2[7:0]
21
Half tone output
O
I
HLFTN
40,42
I
2
C Data
I/O
I
SDATA0,1
39,41
I
2
C Clock
I/O
I
SCLK0,1
16,12,10,9
Bit programmable Input/Output ports
I/O
I
P6[3:0]
20,19,18,17,15,14,11,8
Bit programmable Input/Output ports
I/O
I
P4[7:0]
31
Crystal oscillator input
I
I
XTAL1
32
Crystal oscillator output
O
O
XTAL2
28
Dot clock oscillator input
I
I
OSDX1
29
Dot clock oscillator output
O
O
OSDX2
26
Horizontal Sync
I
I
HSYNC
27
Vertical Sync
I
I
VSYNC
25
Video blank
O
O
VBLANK
24,23,22
Video R,G,B
O
O
R,G,B
9,10,11,12
4-bit Analog to Digital converter input
AI
I
ADC[3:0]
33
Device reset
I
I
/RESET
Note:
1. It is Input on POR. It must be configured to be output ports for PWM applications
Z90231/233/234/239
ZiLOG
Z8 Digital Television Controllers
CP00300-TVX0698
P R E L I M I N A R Y
5
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
rating is a stress rating only. Operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test con-
ditions as noted. All voltages are referenced to GND. Pos-
itive current flows into the referenced pin (Figure 3).
Symbol
Parameters
Min
Max
Units
Notes
V
DD
Power Supply Voltage
0.3
+7
V
V
I
Input Voltage
0.3
V
DD
+0.3
V
V
O
Output Voltage
0.3
V
DD
+0.3
V
I
OH
Output Current High
10
mA
per pin
I
OH
Output Current High
100
mA
per device
I
OL
Output Current Low
20
mA
per pin
I
OL
Output Current Low
200
mA
per device
T
A
Operating Temperature
0
70
o
C
T
STG
Storage Temperature
55
150
o
C
Figure 3. Test Load Diagram
+5V
From Output
Under Test
150 pF
9.1 k
2.1 k
Part_Number
Z8 Digital Television Controllers
ZiLOG
6
P R E L I M I N A R Y
CP00300-TVX0698
DC CHARACTERISTICS
6
#
Q
% VQ
Q
% 8
&&
8 VQ
8 (
15%
/*\
Symbol
Parameter
Min
Typical
Max
Units
Conditions
V
DD
Power Supply Voltage
4.5
5.00
5.5
V
V
IH
Input Voltage High
0.7V
DD
V
DD
V
V
IL
Input Voltage Low
0
0.2V
DD
V
V
IHC
Input XTAL/Osc in High
0.7V
DD
V
CC
V
V
ILC
Input XTAL/Osc In Low
0
0.07V
DD
V
V
OH_ST
Output Voltage High
V
DD
0.4
4.75
V
I
OH
=2mA for standard drive
V
OL_ST
Output Voltage Low
0.16
0.4
V
I
OL
=2.00mA for standard drive
V
OH_LE
Output Voltage High
V
DD
0.4
V
I
OH
=0.98mA for low EMI drive
V
OL_LE
Output Voltage Low
0.4
V
I
OL
=0.66mA for low EMI drive
V
HY
Schmitt Hysteresis
0.1V
DD
0.8
V
I
IR
Reset Input Current
46
80
uA
V
RL
=0V
I
IL
Input Leakage
3.0
0.01
3.0
uA
0V,V
DD
I
OL
Tri-State Leakage
3.0
0.02
3.0
uA
0V,V
DD
I
CC
Supply Current
25
40
mA
All inputs at rail;outputs floating
I
CC1
HALT Mode Current
3.2
6
mA
All inputs at rail;outputs floating
I
CC2
STOP Mode Current
0.1
10
uA
All inputs at rail;outputs floating
Note:
6[RKECN XCNWGU OGCUWTGF CV
Q
%
/KPKOWO CPF /CZKOWO XCNWGU KPFKECVGF HTQO
Q
%
VQ
Q
%
Z90231/233/234/239
ZiLOG
Z8 Digital Television Controllers
CP00300-TVX0698
P R E L I M I N A R Y
7
AC CHARACTERISTICS
No
Symbol
Parameter
Min
Max
Unit
1
T
p
C
Input clock period
166
1000
ns
2
T
r
C, T
f
C
Clock input raise and fall
25
ns
3
T
w
C
Input clock width
35
ns
4
T
w
H
SYNC
L
Timer input low width
70
ns
5
T
w
H
SYNC
H
Timer input high width
3T
p
C
6
T
p
H
SYNC
Timer input period
8T
p
C
7
T
r
H
SYNC
, T
r
H
SYNC
Timer input raise and fall
100
ns
8
T
w
IL
Int request input low
70
ns
9
T
w
IH
Int request input high
3T
p
C
10
T
d
POR
Power-On reset delay
25
100
ms
11
T
d
LVIRES
Low voltage detect to internal
RESET condition
200
ns
12
T
w
RES
Reset minimum width
5T
p
C
13
T
d
H
s
Ol
H
sync
start to V
osc
stop
2T
p
V
3T
p
V
14
T
d
H
s
Oh
H
sync
start to V
osc
start
1T
p
V
Part_Number
Z8 Digital Television Controllers
ZiLOG
8
P R E L I M I N A R Y
CP00300-TVX0698
AC TIMING DIAGRAMS
Figure 4. Timing Diagram
:6#.
*
5;0%
+430
8
%%
+PVGTPCN4'5'6
'ZVGTPCN4'5'6
*
5;0%
15%:
Z90231/233/234/239
ZiLOG
Z8 Digital Television Controllers
CP00300-TVX0698
P R E L I M I N A R Y
9
Pre-Characterization Product:
The product represented by this CPS is newly introduced and
ZiLOG has not completed the full characterization of the
product. The CPS states what ZiLOG knows about this product
at this time, but additional features or non-conformance with
some aspects of the CPS may be found, either by ZiLOG or its
customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
1998 by ZiLOG, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of ZiLOG, Inc. The
information in this document is subject to change without notice.
Devices sold by ZiLOG, Inc. are covered by warranty and patent
indemnification provisions appearing in ZiLOG, Inc. Terms and
Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES FROM INTELLECTUAL PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
ZiLOG, Inc. shall not be responsible for any errors that may
appear in this document. ZiLOG, Inc. makes no commitment to
update or keep current the information contained in this
document.
ZiLOG's products are not authorized for use as critical
components in life support devices or systems unless a specific
written agreement pertaining to such intended use is executed
between the customer and ZiLOG prior to use. Life support
devices or systems are those which are intended for surgical
implantation into the body, or which sustains life whose failure
to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to
result in significant injury to the user.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: http://www.zilog.com
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