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ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432
Telephone: 408.558.8500 Fax: 408.558.8300
www.ZiLOG.com
Advance Product Specification
PS023801-1004
Z8 GP
TM
Microcontrollers
ZGP323H
OTP MCU Family
Disclaimer
P r e l i m i n a r y
PS023801-1004
This publication is subject to replacement by a later edition. To determine whether a later edition
exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.
zilog
.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or
service names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty
and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no
warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No licenses are
conveyed, implicitly or otherwise, by this document under any intellectual property rights.
Z8 GP
TM
OTP MCU Family
Advance Product Specification
PS023801-1004
P r e l i m i n a r y
Table of Contents
iii
Table of Contents
Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Port 0 (P07P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Port 1 (P17P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Port 2 (P27P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Port 3 (P37P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 63
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 68
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Z8 GP
TM
OTP MCU Family
Advance Product Specification
PS023801-1004
P r e l i m i n a r y
List of Figures
iv
List of Figures
Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . 5
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . 6
Figure 5. 40-Pin PDIP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. 48-Pin SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 21
Figure 14. Program Memory Map (32K OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. Register Pointer--Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 41
Figure 24. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 25. 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 26. T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27. T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28. Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 30. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 32. Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 52
Figure 33. STOP Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Z8 GP
TM
OTP MCU Family
Advance Product Specification
PS023801-1004
P r e l i m i n a r y
List of Figures
v
Figure 34. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 35. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 36. Stop Mode Recovery Register 2 ((0F)DH:D2D4, D6 Write Only) . 58
Figure 37. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . 59
Figure 38. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 39. TC8 Control Register ((0D)O0H: Read/Write) . . . . . . . . . . . . . . . . . 63
Figure 40. T8 and T16 Common Control Functions ((0D)01H: Read/Write) . . . 64
Figure 41. T16 Control Register ((0D) 2H: Read/Write) . . . . . . . . . . . . . . . . . . 66
Figure 42. T8/T16 Control Register (0D)03H: Read/Write . . . . . . . . . . . . . . . . 67
Figure 43. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 44. Port Configuration Register (PCON)(0F)00H: Write Only) . . . . . . . 69
Figure 45. Stop Mode Recovery Register ((0F)0BH: D6D0=Write Only, D7=Read
Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 46. Stop Mode Recovery Register 2 ((0F)0DH:D2D4, D6 Write Only) 71
Figure 47. Watch-Dog Timer Register ((0F) 0FH: Write Only) . . . . . . . . . . . . . 72
Figure 48. Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . 72
Figure 49. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . 73
Figure 50. Port 0 and 1 Mode Register (F8H: Write Only) . . . . . . . . . . . . . . . . 74
Figure 51. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . 75
Figure 52. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . 76
Figure 53. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . 76
Figure 54. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 55. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 56. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 78
Figure 57. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 58. 20-Pin CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 59. 20-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 60. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 61. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 62. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 63. 28-Pin CDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 64. 28-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 65. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 66. 40-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 67. 48-Pin SSOP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84