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Электронный компонент: U6264ASA

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1
November 01, 2001
U6264ASA07
The U6264ASA07 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The full CMOS data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by E2 =
L, the standby current (TTL) drops
to 150
A typ.
F
8192 x 8 bit static CMOS RAM
F
70 ns Access Time
F
Common data inputs and outputs
F
Three-state outputs
F
Typ. operating supply current:
30 mA
F
TTL/CMOS-compatible
F
Automatic reduction of power
dissipation in long Read or Write
cycles
F
Power supply voltage 5 V
F
Operating temperature ranges
-40 to 125
C
F
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
F
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F
Latch-up immunity > 100 mA
F
Packages: SOP28 (300 mil)
SOP28 (330 mil)
Pin Configuration
1
n.c.
VCC
28
2
A12
W (WE)
27
4
A6
A8
25
5
A5
A9
24
3
A7
E2 (CE2)
26
6
A4
A11
23
7
A3
G (OE)
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E1 (CE1)
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
SOP
Pin Description
Signal Name
Signal Description
A0 - A12
Address Inputs
DQ0 - DQ7
Data In/Outputs
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Read/Write Enable
VCC
Power Supply Voltage
VSS
Ground
n.c.
not connected
Top View
Automotive 8K x 8 SRAM
Features
Description
2
November 01, 2001
U6264ASA07
Block Diagram
* H or L
Operating Mode
E1
E2
W
G
DQ0 - DQ7
Standby/not
selected
*
L
*
*
High-Z
H
*
*
*
High-Z
Internal Read
L
H
H
H
High-Z
Read
L
H
H
L
Data Outputs, Low-Z
Write
L
H
L
*
Data Inputs, High-Z
Truth Table
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.3
7
V
Input Voltage
V
I
-0.3
V
CC
+ 0.5
V
Output Voltage
V
O
-0.3
V
CC
+ 0.5
V
Power Dissipation
P
D
1
W
Operating Temperature
T
a
-40
125
C
Storage Temperature
T
stg
-65
150
C
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times, in which cases transition is measured
200 mV from steady-state voltage.
A0
A1
A2
A3
A10
Address
Change
Detector
Memory Cell
Array
256 Rows x
256 Columns
Ro
w De
c
o
d
e
r
Ro
w
A
d
d
r
e
s
s
In
p
u
t
s
Co
l
u
m
n
De
c
o
d
e
r
Co
m
m
o
n
Da
t
a
I
/
O
Sense Amplifier/
Write Control Logic
Clock
Generator
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E2
E1
Co
l
u
m
n
A
d
d
r
e
s
s
In
p
u
t
s
V
CC
V
SS
W
G
A4
A5
A6
A7
A8
A9
A11
A12
3
November 01, 2001
U6264ASA07
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(TTL level)
I
CC(OP)
I
CC(SB)1
V
CC
V
IL
V
IH
t
cW
V
CC
V
E1
= V
E2
or V
E2
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
= 5.5 V
= 2.2 V
= 0.8 V
55
3
mA
mA
Output High Voltage
TTL compatible
CMOS compatible
Output Low Voltage
V
OH
V
OH
V
OL
V
CC
I
OH
V
CC
I
OL
= 4.5 V
= -1.0 mA
= 4.5 V
= 3.2 mA
2.4
0.85
*
V
CC
-
-
-
0.4
V
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
CC
V
OL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-
3.2
-1
-
mA
mA
Supply Current - Standby Mode
(CMOS level)
Supply Current - Data Retention Mode
I
CC(SB)
I
CC(DR)
V
CC
V
E1
= V
E2
or V
E2
V
CC(DR)
V
E1
= V
E2
or V
E2
= 5.5 V
= V
CC
-
0.2
V
= 0.2 V
= 3
V
= V
CC(DR)
- 0.2 V
= 0.2 V
30
10
A
A
Input High Leakage Current
Input Low Leakage Current
I
IH
I
IL
V
CC
V
IH
V
CC
V
IL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
-
-2
2
-
A
A
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
I
OHZ
I
OLZ
V
CC
V
OH
V
CC
V
OL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
-
-2
2
-
A
A
* -2 V at Pulse Width 10 ns
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Data Retention Voltage
V
CC(DR)
2.0
-
V
Input Low Voltage*
V
IL
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+0.3
V
4
November 01, 2001
U6264ASA07
Switching Characteristics
Symbol
Min.
Max.
Unit
Alt.
IEC
Time to Output in Low-Z
t
LZ
t
t(QX)
5
10
ns
Cycle Time
Write Cycle Time
Read Cycle Time
t
WC
t
RC
t
cW
t
cR
70
70
-
-
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
t
ACE
t
OE
t
AA
t
a(E)
t
a(G)
t
a(A)
-
-
-
70
40
70
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
t
WP
t
CW
t
w(W)
t
w(E)
50
65
-
-
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
t
AS
t
CW
t
WP
t
DS
t
su(A)
t
su(E)
t
su(W)
t
su(D
)
0
65
50
35
-
-
-
-
ns
ns
ns
ns
Data Hold Time
Address Hold from End of Write
t
DH
t
AH
t
h(D)
t
h(A)
0
0
-
-
ns
ns
Output Hold Time from Address Change
t
OH
t
v(A)
5
-
ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
HZCE
t
HZWE
t
HZOE
t
dis(E)
t
dis(W)
t
dis(G)
0
0
0
25
30
25
ns
ns
ns
Data Retention Mode E1-Controlled
Data Retention
4.5 V
t
DR
t
rec
V
CC
E1
V
CC(DR)
2 V
V
E2(DR)
V
CC(DR)
- 0.2 V or V
E2(DR)
0.2 V
V
CC(DR)
- 0.2 V
V
E1(DR)
V
CC(DR)
+ 0.3 V
0 V
2.2 V
2.2 V
V
CC(DR)
2 V
Data Retention Mode E2-Controlled
Data Retention
t
DR
0.8 V
0.8 V
V
E2(DR)
0.2 V
4.5 V
0 V
V
CC
E2
t
rec
Chip Deselect to Data Retention Time
t
DR
:
min 0 ns
Operating Recovery Time
t
rec
:
min t
cR
5
November 01, 2001
U6264ASA07
Test Configuration for Functional Check
(for TTL output levels)
V
IH
V
IL
V
SS
V
CC
5 V
960
510
30 pF
1)
V
O
S
i
m
u
l
t
an
eo
us
m
e
a
s
ur
e
-
me
nt
of
al
l 8

o
u
t
p
ut

p
i
ns
Inp
u
t
le
v
e
l
ac
c
o
r
d
in
g t
o
t
h
e
r
e
l
e
v
a
n
t
t
e
s
t
m
e
as
ur
e
m
en
t
1)
In measurement of t
dis(E)
, t
dis(W)
, t
dis(G)
the capacitance is 5 pF.
IC Code Numbers
Example
All pins not under test must be connected with ground by capacitors.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
E1
E2
W
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
V
CC
= 5.0 V
V
I
=
V
SS
C
I
8
pF
Output Capacitance
f
= 1 MHz
T
a
=
25
C
C
O
10
pF
S
U6264A
07
A
Type
Package
S1 = SOP28 (300 mil)
S
= SOP28 (330 mil)
Access Time
07 = 70 ns
Operating Temperature Range
A = -40 to 125 C
Internal Code
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
6
November 01, 2001
U6264ASA07
t
h(D)
Read Cycle 1 (during Read cycle: E1 = G = V
IL
, E2 = W = V
IH
)
Read Cycle 2 (during Read cycle: W = V
IH
)
Write Cycle 1 (W-controlled)
t
a(A)
Previous Data Valid
Output Data Valid
t
cR
Addresses Valid
t
v(A)
A
i
DQ
i
A
i
E1
E2
G
DQ
i
Output
Output
t
dis(E)
t
cR
t
su(A)
t
a(E)
t
su(A)
t
t(QX)
t
t(QX)
t
t(QX)
t
a(G)
t
a(E)
t
dis(E)
t
dis(G)
Addresses Valid
Output Data Valid
A
i
E1
E2
W
DQ
i
Input
G
DQ
i
Output
t
cW
t
su(E)
t
h(A)
t
w(W)
t
su(A)
t
su(E)
t
su(D)
t
dis(W)
t
t(QX)
Addresses Valid
Input Data Valid
High-Z
High-Z
7
November 01, 2001
U6264ASA07
t
su(A)
Input Data Valid
t
h(D)
t
su(W)
t
w(E)
t
su(D)
t
cW
Addresses Valid
t
su(E)
t
h(A)
t
t(QX)
t
dis(W)
A
i
E1
E2
W
DQ
i
Input
G
DQ
i
Output
High-Z
t
su(A)
undefined
L- or H-level
Write Cycle 2 (E1-controlled)
Write Cycle 3 (E2-controlled)
t
h(D)
A
i
E1
E2
W
DQ
i
Input
G
DQ
i
Output
t
cW
t
w(E)
t
h(A)
t
su(W)
t
su(E)
t
su(D)
t
dis(W)
t
t(QX)
Addresses Valid
Input Data Valid
High-Z
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstrae 28
D-01109 Dresden
P. O. B. 80 01 34
D-01101 Dresden
Germany
Phone: +49 351 8822 306
Fax: +49 351 8822 337
Email: sales@zmd.de
http://www.zmd.de
November 01, 2001
U6264ASA07
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.