March 8, 1999

U62H256S

Features

32768 x 8 bit static CMOS RAM

35 and 55 ns Access Time

Common data inputs and
data outputs

Three-state outputs

Typ. operating supply current

35 ns: 45mA
55 ns: 30mA

Standby current < 2 mA

TTL/CMOS-compatible

Automatic reduction of power
dissipation in long Read or Write
cycles

Power supply voltage 5 V

Operating temperature range

-40

to 85

-40

C to 125

CECC 90000 Quality Standard

ESD protection > 2000 V
(MIL STD 883C M3015.7)

Latch-up immunity >100 mA

Package:

SOP28 (300 mil)

Description

The U62H256S is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read

- Standby

- Write

- Data Retention

The memory array is based on a
MIXMOS cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L each address change leads
to a new Read or Write cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new

information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (I

= 0 mA)

drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of W, or by the rising edge of
E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.

Automotive Fast 32K x 8 SRAM

Pin Configuration

Top View

Signal Name

Signal Description

A0 - A14

Address Inputs

DQ0 - DQ7

Data In/Out

Chip Enable

Output Enable

Write Enable

VCC

Power Supply Voltage

VSS

Ground

Pin Description

A14

VCC

A12

A13

A11

A10

DQ1

DQ5

DQ7

DQ0

DQ6

DQ2

DQ4

VSS

DQ3

SOP

March 8, 1999

U62H256S

* H or L

Operating Mode

DQ0 - DQ7

Standby/not selected

High-Z

Internal Read

High-Z

Read

Data Outputs Low-Z

Write

Data Inputs High-Z

Truth Table

Block Diagram

Maximum Ratings

Symbol

Min.

Max.

Unit

Power Supply Voltage

-0.5

Input Voltage

-0.5

+ 0.5

Output Voltage

-0.5

+ 0.5

Power Dissipation

Operating Temperature

K-Type
A-Type

-40
-40

125

Storage Temperature

stg

-65

150

Output Short-Circuit Current
at V

= 5 V and V

= 0 V

| I

200

Characteristics

Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

All voltages are referenced to V

= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of

5 ns, measured between 10 % and 90 % of V

, as well as

input levels of V

= 0 V and V

= 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the t

dis

-times and t

-times, in which cases transition is measured

200 mV from steady-state voltage.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

w A

r
e

I
npu

t
s

r
e

I
nput

Address

Change

Detector

w D

Sense Amplifier/

Write Control Logic

Clock

Generator

mmo

t
a

/
O

Memory Cell

Array

256 Rows x

128 x 8 Columns

A0
A1
A2
A3
A10
A5

A7
A8
A9
A4
A11
A12
A13
A14

March 8, 1999

U62H256S

* -2 V at Pulse Width 10 ns

Recommended
Operating Conditions

Symbol

Conditions

Min.

Max.

Unit

Power Supply Voltage

4.5

5.5

Input Low Voltage

-0.3

0.8

Input High Voltage

2.2

+ 0.3

Electrical Characteristics

Symbol

Conditions

Min.

Max.

Unit

Supply Current - Operating Mode

Supply Current - Standby Mode
(CMOS level)

Supply Current - Standby Mode
(TTL level)

CC(OP)

CC(SB)

CC(SB)1

K-Type
A-Type

= 5.5 V
= 0.8 V
= 2.2 V
= 35 ns
= 55 ns

= 5.5 V
= V

- 0.2 V

= 5.5 V
= 2.2 V

90
70

0.5

10
20

mA
mA

Output High Voltage

Output Low Voltage

= 4.5 V
= -4.0 mA
= 4.5 V
= 8.0 mA

2.4

0.4

Input High Leakage Current

Input Low Leakage Current

= 5.5 V
= 5.5 V
= 5.5 V
= 0 V

-2

Output High Current

Output Low Current

= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V

-4

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

OHZ

OLZ

= 5.5 V
= 5.5 V
= 5.5 V
=

0 V

-2

March 8, 1999

U62H256S

Switching Characteristics
Read Cycle

Symbol

Unit

Alt.

IEC

Min.

Max.

Min.

Max.

Read Cycle Time

Address Access Time to Data Valid

a(A)

Chip Enable Access Time to Data Valid

ACE

a(E)

G LO W to Data Valid

a(G)

E HIGH to Output in High-Z

HZCE

dis(E)

G HIGH to Output in High-Z

HZOE

dis(G)

E LOW to Output in Low-Z

LZCE

en(E)

G LO W to Output in Low-Z

LZOE

en(G)

Output Hold Time from Address Change

v(A)

E LOW to Power-Up Time

E HIGH to Power-Down Time

Switching Characteristics
Write Cycle

Symbol

Unit

Alt.

IEC

Min.

Max.

Min.

Max.

Write Cycle Time

Write Pulse Width

w(W)

Write Setup Time

su(W)

Address Setup Time

su(A)

Address Valid to End of Write

tsu(A-WH)

Chip Enable Setup Time

su(E)

Pulse Width Chip Enable to End of Write

w(E)

Data Setup Time

su(D)

Data Hold Time

h(D)

Address Hold from End of Write

h(A)

W LOW to Output in High-Z

HZWE

dis(W)

G HIGH to Output in High-Z

HZOE

dis(G)

W HIGH to Output in Low-Z

LZWE

en(W)

G LO W to Output in Low-Z

LZOE

en(G)

March 8, 1999

U62H256S

Data Retention Mode

Data Retention
Characteristics

Symbol

Conditions

Min.

Typ.

Max.

Unit

Alt.

IEC

Data Retention Supply Voltage

CC(DR)

5.5

Data Retention Supply Current

CC(DR)

= 3 V

CC(DR)

- 0.2 V

K-Type
A-Type

0.09

mA
mA

Data Retention Setup Time

CDR

su(DR)

See Data Retention
Waveforms (above)

Operating Recovery Time

rec

AAAA

Data Retention

4.5 V

su(DR)

rec

CC(DR)

2 V

0 V

2.2 V

DQ0
DQ1
DQ2

DQ3

DQ4
DQ5
DQ6
DQ7

Test Configuration for Functional Check

5 V

481

255

30 pF

In measurement of t

dis(E)

dis(W)

, t

en(E)

, t

en(W)

, t

en(G)

the capacitance is 5 pF.

I
npu

t

l
e

l
ac

r
d

i
n

r
e

l
e

ant

t
e

t
m

eas

ent

l
t
ane

ous

eas

ent

f

al

l

8 o

t
p

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

E
W
G

E - controlled

CC(DR)

- 0.2 V

E(DR)

CC(DR)

+ 0.3 V

March 8, 1999

U62H256S

All pins not under test must be connected with ground by capacitors

Capacitance

Conditions

Symbol

Min.

Max.

Unit

Input Capacitance

= 5.0 V
= V

= 1

MHz

= 25

Output Capacitance

IC Code Numbers

U62H256

Type

Package
S = SOP

Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C

Access Time
35 = 35 ns
55 = 55 ns

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.

March 8, 1999

U62H256S

dis(G)

dis(E)

Previous
Data Valid

Output Data
Valid

Address Valid

su(A )

High-Z

en(E)

en(G)

a(G)

a(E)

Read Cycle 1: A

-controlled (during Read Cycle : E = G = V

, W = V

)

Read Cycle 2: G-, E-controlled (during Read Cycle: W = V

)

a(A)

v(A)

AAAA

AAA

AAAA

AAA

Output

AAAA

AAA

Output

AAAAAAAAAAAAAAAAAAAAA

AAAAAAAAAAA

CC(OP)

CC(SB)

50 %

Output Data
Valid

March 8, 1999

U62H256S

AAAA

L- to H-level

undefined

H- to L-level

The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and
rights to change design reserved.

Input Data
Valid

Write Cycle1: W-controlled

Write Cycle 2: E-controlled

su(A )

h(D)

Input

Output

w(E)

h(A )

su(W)

su(D)

dis(W)

en(E)

High-Z

AAAA

AAA

AAAA

h(D)

Input

Output

su(E)

h(A )

w(W)

su(A )

su(D)

dis(W)

en(W)

Address Valid

Input Data
Valid

High-Z

AAAA

AAA

AAAA

AAA

AAAA

AAA

su(A -WH)

AAAA

Address Valid

Zentrum Mikroelektronik Dresden GmbH

Grenzstrasse 28

D-01109 Dresden

P. O. B. 80 01 34

D-01101 Dresden

Germany

Phone:

+49

351

22-3

Fax:

+49

351

22-3

Email: sales@zmd.de

http://www.zmd.de

LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.

LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be
reliable. However Zentrum Mikroelektronik Dresden GmbH (ZMD) makes no
guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or
reliance upon it. The information in this document describes the type of component
and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any information contained herein will not
infringe upon the patent, trademark, copyright, mask work right or other rights of
third parties, and no patent or licence is implied hereby. This document does not in
any way extent ZMD's warranty on any product beyond that set forth in its standard
terms and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the
products or specifications, or both, presented in this publication at any time and
without notice.

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