December 12, 1997

U62H64SA

Description

The U62H64SA is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
(E1 = L and E2 = H), each address
change leads to a new Read or
Write cycle. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at

the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the ope-
rating current (at I

= 0 mA) drops to

the value of the operating current in
the Standby mode. The Read cycle
is finished by the falling edge of E2
or W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E1 and E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.

Features

Fast 8192 x 8 bit static CMOS RAM

35 ns Access Time

Bidirectional data inputs and data

outputs

Three-state outputs

Data retention current at 3 V:

< 50

Standby current < 100

TTL/CMOS-compatible

Automatic reduction of power

dissipation in long Read or Write
cycles

Power supply voltage 5 V

Operating temperature range

-40 to 125

Quality assessment according to

CECC 90000, CECC 90100 and
CECC 90111

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity > 200 mA

Package: SOP28 (300 mil)

Pin Description

Signal Name Signal Description

A0 - A12 Address Inputs

DQ0 - DQ7 Data In/Out

Chip Enable 1

E2 Chip Enable 2

Output Enable

Write Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Configuration

n.c.

VCC

A12

W (WE)

E2 (CE2)

A11

G (OE)

A10

DQ1

DQ5

E1 (CE1)

DQ7

DQ0

DQ6

DQ2

DQ4

VSS

DQ3

SOP

Top View

Automotive Fast 8K x 8 SRAM

December 12, 1997

U62H64SA

* H or L

Operating Mode E1

E2 W

DQ0 - DQ7

Standby/not

selected

* L * * High-Z

H * * * High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs

Low-Z

Write L H L * Data Inputs High-Z

Truth Table

Block Diagram

Memory Cell

Array

128 Rows

64 x 8 Columns

r
e

t
i
ona

l

D

t
a

/
O

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

* Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 s.

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage V

-0.3 7 V

Input Voltage V

-0.3 V

+ 0.5 V

Output Voltage V

-0.3 V

+ 0.5 V

Operating Temperature T

-40 125

Storage Temperature T

stg

-65 150

Output Short-Circuit Current
at V

= 5 V and V

= 0 V

200

Characteristics

Addr

I
nput

w De

Sense Amplifier/

Write Control Logic

Clock

Generator

l
u

Addr

I
nput

l
u

oder

Address

Change

Detector

A6
A7
A8
A9
A10
A11
A12

All voltages are referenced to V

= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of

5 ns, measured between 10 % and 90 % of V

, as well as

input levels of V

= 0 V and V

= 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the t

dis

-times and t

-times, in which cases transition is measured

200 mV from steady-state voltage.

December 12, 1997

U62H64SA

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - Standby Mode
(CMOS level)

Supply Current - Standby Mode
(TTL level)

Supply Current - Data Retention
Mode

CC(OP)

CC(SB)

CC(SB)1

CC(DR)

= V

CC(DR)

= V

= 5.5 V
= 0.8 V
= 2.2 V
=

35 ns

= 5.5 V
= V

- 0.2 V

= 5.5 V
= 2.2 V

= 3.0 V
= V

CC(DR)

- 0.2 V

100

(typ. 2)

Output High Voltage

Output Low Voltage

= 4.5 V
= -4.0 mA
= 4.5 V
= 8.0 mA

2.4

0.4

Output High Current

Output Low Current

= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V

8.0

-4.0

Input High Leakage Current

Input Low Leakage Current

= 5.5 V
= 5.5 V
= 5.5 V
= 0 V

-2

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

OHZ

OLZ

= 5.5 V
= 5.5 V
= 5.5 V
=

0 V

-2

* -2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns

Recommended

Operating Conditions

Symbol Conditions Min. Max. Unit

Power Supply Voltage V

4.5 5.5 V

Data Retention Voltage V

CC(DR)

2.0

Input Low Voltage *

-0.3 0.8 V

Input High Voltage V

2.2 V

+0.3 V

December 12, 1997

U62H64SA

Switching Characteristics

Symbol Min. Max. Unit

Alt. IEC 35 35

Time to Output in Low-Z from

E1 LO W or E2 HIGH
G LOW
W HIGH

LZCE

LZOE

LZWE

en(E)

en(G)

en(W)

5
0
0

ns
ns
ns

Cycle Time

Write Cycle Time
Read Cycle Time

35
35

ns
ns

Access Time

E1 LO W or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid

ACE

a(E)

a(G)

a(A)

35
15
35

ns
ns
ns

Pulse Widths

Write Pulse Width
Chip Enable to End of Write

w(W)

w(E)

20
25

ns
ns

Setup Times

Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time

su(A)

su(E)

su(W)

su(D)

25
20
15

ns
ns
ns
ns

Data Hold Time
Address Hold from End of Write

h(D)

h(A)

0
0

ns
ns

Output Hold Time from Address Change t

v(A)

E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z

HZCE

HZWE

HZOE

dis(E)

dis(W)

dis(G)

15
15
12

ns
ns
ns

E1 LOW or E2 HIGH to Power-Up t

E1 HIGH or E2 LO W to Power-Down t

35 ns

Data Retention Mode E1-Controlled

Data Retention Mode E2-Controlled

4.5 V

CC(DR)

2 V

E2(DR)

CC(DR)

- 0.2 V or V

E2(DR)

0.2 V

CC(DR)

- 0.2 V

E1(DR)

CC(DR)

+ 0.3 V

0 V

0.8 V

4.5 V

0 V

Chip Deselect to Data Retention Time t

: min 0 ns

Operating Recovery Time at V

CC(DR)

rec

: min t

E1(DR)

CC(DR)

- 0.2 V or V

E1(DR)

0.2 V

E2(DR)

0.2 V

rec

Data Retention

2.2 V

2.2 V t

rec

CC(DR)

2 V

Data Retention

December 12, 1997

U62H64SA

Test Configuration for Functional Check

5 V

481

255

30 pF

IC Code Number

Example

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.

U62H64

Type

Package
S = SOP

Access Time
35 = 35 ns

Operating Temperature Range
A = -40 to 125 °C

All pins not under test must be connected with ground by capacitors.

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e

l
a

r
d

i
n

r
e

l
e

ant

t
e

t
m

eas

ent

l
t
aneou

eas

l
l
8

out

put

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

E1
E2
W
G

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance

= 5.0 V

= V

Output Capacitance

f = 1 MHz
T

= 25

10 pF

In measurement of t

dis(E)

, t

dis(W)

, t

dis(G)

, t

en(E)

, t

en(W)

, t

en(G)

the capacitance is 5 pF.

December 12, 1997

U62H64SA

AAAA

High-Z

Addresses Valid

Read Cycle 2 (during Read cycle: W = V

, G-, E1- or E2-controlled)

Output

dis(E)

su(A)

a(E)

su(A)

en(E)

en(G)

a(G)

a(E)

dis(E)

dis(G)

Output Data
Valid

AAAA

AAA

AAAA

AAA

CC(OP)

CC(SB)

h(D)

Read Cycle 1 (during Read cycle: E1 = G = V

, E2 = W = V

, A

-controlled)

Write Cycle 1 (W-controlled)

a(A)

Previous
Data Valid

Output Data
Valid

Addresses Valid

v(A)

AAAA

AAA

Output

su(E)

h(A)

w(W)

su(A )

su(E)

su(D)

dis(W)

en(W)

Addresses Valid

High-Z

AAAA

AAA

AAAA

AAA

Input

* The same applies to E1

50 %

AAAA

AAA

Input Data
Valid

December 12, 1997

U62H64SA

AAAA

AAA

AAAA

AAA

High-Z

nput Data

Valid

h(D)

su(W)

w(E)

su(D)

Addresses Valid

su(A )

su(E)

h(A)

en(E)

dis(W)

AAAA

Input

Output

su(A )

AAAA

undefined L- or H-level

Write Cycle 2 (E1-controlled)

Write Cycle 3 (E2-controlled)

h(D)

Input

Output

w(E)

h(A)

su(W)

su(E)

su(D)

dis(W)

en(E)

Addresses Valid

Input Data
Valid

High-Z

AAAA

AAA

AAAA

AAA

LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.

The information describes the type of component and shall not be considered as
assured characteristics.

Terms of delivery and rights to change design reserved.

Memory Products 1998

Automotive Fast 8K x 8 SRAM U62H64SA

Zentrum Mikroelektronik Dresden GmbH

Grenzstraße 28

· D-01109 Dresden

B. 80

D-01101 Dresden

Germany

Phone: +49 351 88 22-3 06 · Fax: +49 351 88 22-3 37 · Email: sales@zmd.de

Internet Web Site: http://www.zmd.de

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