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Электронный компонент: U62H64SK35LG1

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April 20, 2004
1
U62H64
The U62H64 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E1 and E2,
all inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
!
Fast 8192 x 8 bit static CMOS
RAM
!
35 ns Access Time
!
Bidirectional data inputs and data
outputs
!
Three-state outputs
!
Data retention mode at Vcc > 2V
!
Data retention current at 2 V:
< 3 A (K-Type)
< 50
A (A-Type)
!
Standby current
< 5
A
(K-Type)
< 100 A (A-Type)
!
TTL/CMOS-compatible
!
Automatic reduction of power
dissipation in long Read or Write
cycles
!
Power supply voltage 5 V
!
Operating temperature ranges
-40 to 85 C
-40 to 125
C
!
QS 9000 Quality Standard
!
ESD protection > 2000 V
(MIL STD 883C M3015.7)
!
Latch-up immunity > 200 mA
!
Package:
SOP28 (300 mil)
Pin Description
Signal Name
Signal Description
A0 - A12
Address Inputs
DQ0 - DQ7
Data In/Out
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
n.c.
not connected
Pin Configuration
1
n.c.
VCC
28
2
A12
W (WE)
27
4
A6
A8
25
5
A5
A9
24
3
A7
E2 (CE2)
26
6
A4
A11
23
7
A3
G (OE)
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E1 (CE1)
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
SOP
Top View
Automotive Fast 8K x 8 SRAM
Features
Description
April 20, 2004
2
U62H64
Block Diagram
* H or L
Operating Mode
E1
E2
W
G
DQ0 - DQ7
Standby/not selected
*
L
*
*
High-Z
H
*
*
*
High-Z
Internal Read
L
H
H
H
High-Z
Read
L
H
H
L
Data Outputs Low-Z
Write
L
H
L
*
Data Inputs High-Z
Truth Table
A0
A1
A2
A3
A4
A5
Memory Cell
Array
128 Rows
64 x 8 Columns
B
i
d
i
r
e
c
t
i
o
n
a
l
D
a
t
a
I/
O
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E2
E1
V
CC
V
SS
W
G
Ro
w A
d
d
r
e
s
s
In
p
u
t
s
Ro
w De
c
o
d
e
r
Sense Amplifier/
Write Control Logic
Clock
Generator
Co
l
u
m
n
A
d
d
r
e
s
s
I
npu
t
s
Co
l
u
m
n
De
c
o
d
e
r
Address
Change
Detector
A6
A7
A8
A9
A10
A11
A12
April 20, 2004
3
U62H64
a
Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
Maximum voltage is 7 V
c
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Absolute Maximum Ratings
a
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.3
7
V
Input Voltage
V
I
-0.3
V
CC
+ 0.5
b
V
Output Voltage
V
O
-0.3
V
CC
+ 0.5
b
V
Operating Temperature
K-Type
A-Type
T
a
-40
-40
85
125
C
C
Storage Temperature
T
stg
-65
150
C
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
c
|I
OS
|
200
mA
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
200 mV from steady-state voltage.
d
-2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Data Retention Voltage
V
CC(DR)
2.0
-
V
Input Low Voltage
d
V
IL
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
April 20, 2004
4
U62H64
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
Supply Current - Data Retention Mode
I
CC(OP)
I
CC(SB)
I
CC(SB)1
I
CC(DR)
V
CC
V
IL
V
IH
t
cW
V
CC
V
E1
= V
E2
K-Type
A-Type
V
CC
V
E1
= V
E2
V
CC(DR)
V
E1
= V
E2
K-Type
A-Type
= 5.5
V
= 0.8
V
= 2.2
V
=
35 ns
= 5.5
V
= V
CC
- 0.2 V
= 5.5
V
= 2.2
V
= 2.0
V
= V
CC(DR)
- 0.2 V
50
5
100
5
(typ. 2)
3
50
mA
A
A
mA
A
A
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
V
CC
I
OL
= 4.5
V
= -4.0 mA
= 4.5
V
= 8.0 mA
2.4
-
-
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
CC
V
OL
= 4.5
V
= 2.4 V
= 4.5 V
= 0.4
V
-
8.0
-4.0
-
mA
mA
Input High Leakage Current
Input Low Leakage Current
I
IH
I
IL
V
CC
V
IH
V
CC
V
IL
= 5.5 V
= 5.5 V
= 5.5
V
= 0 V
-
-2
2
-
A
A
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
I
OHZ
I
OLZ
V
CC
V
OH
V
CC
V
OL
= 5.5
V
= 5.5 V
= 5.5
V
=
0 V
-
-2
2
-
A
A
April 20, 2004
5
U62H64
Switching Characteristics
Symbol
Min.
Max.
Unit
Alt.
IEC
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
W HIGH
t
LZCE
t
LZOE
t
LZWE
t
en(E)
t
en(G)
t
en(W)
5
0
0
ns
ns
ns
Cycle Time
Write Cycle Time
Read Cycle Time
t
WC
t
RC
t
cW
t
cR
35
35
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
t
ACE
t
OE
t
AA
t
a(E)
t
a(G)
t
a(A)
35
15
35
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
t
WP
t
CW
t
w(W)
t
w(E)
20
25
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
t
AS
t
CW
t
WP
t
DS
t
su(A)
t
su(E)
t
su(W)
t
su(D)
0
25
20
15
ns
ns
ns
ns
Data Hold Time
Address Hold from End of Write
t
DH
t
AH
t
h(D)
t
h(A)
0
0
ns
ns
Output Hold Time from Address Change
t
OH
t
v(A)
5
ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
HZCE
t
HZWE
t
HZOE
t
dis(E)
t
dis(W)
t
dis(G)
15
15
12
ns
ns
ns
E1 LOW or E2 HIGH to Power-Up
t
PU
0
ns
E1 HIGH or E2 LOW to Power-Down
t
PD
35
ns
Data Retention Mode E1-Controlled
4.5 V
V
CC
E1
V
CC(DR)
2 V
V
E2(DR)
V
CC(DR)
- 0.2 V or V
E2(DR)
0.2 V
V
CC(DR)
- 0.2 V
V
E1(DR)
V
CC(DR)
+ 0.3 V
0 V
t
rec
t
DR
Data Retention
2.2 V
2.2 V
Data Retention Mode E2-Controlled
0.8 V
0.8 V
4.5 V
0 V
V
CC
V
E1(DR)
V
CC(DR)
- 0.2 V or V
E1(DR)
0.2 V
V
E2(DR)
0.2 V
t
rec
t
DR
V
CC(DR)
2 V
Data Retention
E2
Chip Deselect to Data Retention Time
t
DR
:
min 0 ns
Operating Recovery Time at V
CC(DR)
t
rec
: min
t
cR