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August 13, 2003
U631H16
SoftStore 2K x 8 nvSRAM
!
Packages: PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (300 mil)
SOP24 (300 mil)
Description
The U631H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion), or from the EEPROM to the
SRAM (the RECALL ) operation)
are initiated through software
sequences.
The U631H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
!
High-performance CMOS nonvola-
tile static RAM 2048 x 8 bits
!
25, 35 and 45 ns Access Times
!
12, 20 and 25 ns Output Enable
Access Times
!
Software STORE Initiation
(STORE Cycle Time < 10 ms)
!
Automatic STORE Timing
!
10
5
STORE cycles to EEPROM
!
10 years data retention in
EEPROM
!
Automatic RECALL on Power Up
!
Software RECALL Initiation
(RECALL Cycle Time < 20
s)
!
Unlimited RECALL cycles from
EEPROM
!
Unlimited Read and Write to
SRAM
!
Single 5 V
10 % Operation
!
Operating temperature ranges:
0 to 70 C
-40 to 85 C
!
QS 9000 Quality Standard
!
ESD characterization according
!
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Pin Configuration
Pin Description
Top View
1
n.c.
VCC
28
2
n.c.
W
27
4
A6
A8
25
5
A5
A9
24
3
A7
n.c.
26
6
A4
n.c.
23
7
A3
G
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
PDIP
Signal Name
Signal Description
A0 - A10
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
SOP
28
Top View
2
A6
A8
23
3
A5
A9
22
1
A7
VCC
24
4
A4
W
21
5
A3
G
20
6
A2
A10
19
10
DQ1
DQ5
15
7
A1
E
18
8
A0
DQ7
17
9
DQ0
DQ6
16
11
DQ2
DQ4
14
12
VSS
DQ3
13
SOP
24
Features
2
August 13, 2003
U631H16
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read L
H
L
Data
Outputs
Low-Z
Write
L
L
*
Data Inputs High-Z
Block Diagram
Truth Table for SRAM Operations
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
200 mV from steady-state voltage.
a: Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
a
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7
V
Input Voltage
V
I
-0.3
V
CC
+0.5
V
Output Voltage
V
O
-0.3
V
CC
+0.5
V
Power Dissipation
P
D
1
W
Operating Temperature
C-Type
K-Type
T
a
0
-40
70
85
C
C
Storage Temperature
T
stg
-65
150
C
EEPROM Array
32 x (64 x 8)
STORE
RECALL
SRAM
Array
32 Rows x
64 x 8 Columns
A5
A6
A7
A8
A9
Store/
Recall
Control
Ro
w De
c
o
d
e
r
V
CC
V
SS
V
CC
G
E
W
Software
Detect
A0 - A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
A0 A1
A2
A3
A4 A10
In
p
u
t B
u
ffe
r
s
3
August 13, 2003
U631H16
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Operating Supply Current
b
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
t
c
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 35 ns
= 45 ns
90
80
75
95
85
80
mA
mA
mA
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
6
7
mA
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC(SB)1
V
CC
E
t
c
t
c
t
c
= 5.5 V
V
IH
= 25 ns
= 35 ns
= 45 ns
30
23
20
34
27
23
mA
mA
mA
Average Supply Current
at t
cR
= 200 ns
b
(Cycling CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
15
15
mA
Standby Supply Current
d
(Stable CMOS Input Levels)
I
CC(SB)
V
CC
E
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
1
1
mA
Recommended Operation
Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Input Low Voltage
V
IL
-2 V at Pulse Width
10 ns permitted
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+0.3
V
b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
c: I
CC2
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
4
August 13, 2003
U631H16
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
2.4
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
OL
= 4.5 V
= 2.4 V
= 0.4 V
8
-4
8
-4
mA
mA
Input Leakage Current
High
Low
I
IH
I
IL
V
CC
V
IH
V
IL
= 5.5 V
= 5.5 V
= 0 V
-1
1
-1
1
A
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
V
CC
V
OH
V
OL
= 5.5 V
= 5.5 V
= 0 V
-1
1
-1
1
A
A
SRAM Memory Operations
No.
Switching Characteristics
Read Cycle
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
Read Cycle Time
f
t
AVAV
t
cR
25
35
45
ns
2
Address Access Time to Data Valid
g
t
AVQV
t
a(A)
25
35
45
ns
3
Chip Enable Access Time to Data Valid
t
ELQV
t
a(E)
25
35
45
ns
4
Output Enable Access Time to Data Valid
t
GLQV
t
a(G)
12
20
25
ns
5
E HIGH to Output in High-Z
h
t
EHQZ
t
dis(E)
13
17
20
ns
6
G HIGH to Output in High-Z
h
t
GHQZ
t
dis(G)
13
17
20
ns
7
E LOW to Output in Low-Z
t
ELQX
t
en(E)
5
5
5
ns
8
G LOW to Output in Low-Z
t
GLQX
t
en(G)
0
0
0
ns
9
Output Hold Time after Addr. Change
g
t
AXQX
t
v(A)
3
3
3
ns
19 Chip Enable to Power Active
e
t
ELICCH
0
0
0
ns
11 Chip Disable to Power Standby
d, e
t
EHICCL
25
35
45
ns
e: Parameter guaranteed but not tested.
f:
Device is continuously selected with E and G both LOW.
g: Address valid prior to or at the same time with E transition LOW.
h: Measured
200 mV from steady state output voltage.
5
August 13, 2003
U631H16
t
PU
(10)
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
No. Switching Characteristics
Write Cycle
Symbol
25
35
45
Unit
Alt. #1
Alt. #2
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
t
AVAV
t
AVAV
t
cW
25
35
45
ns
13 Write Pulse Width
t
WLWH
t
w(W)
20
30
35
ns
14 Write Pulse Width Setup Time
t
WLEH
t
su(W)
20
30
35
ns
15 Address Setup Time
t
AVWL
t
AVEL
t
su(A)
0
0
0
ns
16 Address Valid to End of Write
t
AVWH
t
AVEH
t
su(A-WH)
20
30
35
ns
17 Chip Enable Setup Time
t
ELWH
t
su(E)
20
30
35
ns
18 Chip Enable to End of Write
t
ELEH
t
w(E)
20
30
35
ns
19 Data Setup Time to End of Write
t
DVWH
t
DVEH
t
su(D)
12
18
20
ns
20 Data Hold Time after End of Write
t
WHDX
t
EHDX
t
h(D)
0
0
0
ns
21 Address Hold after End of Write
t
WHAX
t
EHAX
t
h(A)
0
0
0
ns
22 W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
10
13
15
ns
23 W HIGH to Output in Low-Z
t
WHQX
t
en(W)
5
5
5
ns
Ai
E
G
DQi
Output
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Address Valid
Output Data Valid
High Impedance
I
CC
ACTIVE
STANDBY
t
PD
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(11)
t
a(A)
(2)
t
a(A)
Previous Data Valid
Output Data Valid
t
cR
Address Valid
t
v(A)
Ai
DQi
Output
(1)
(2)
(9)