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Электронный компонент: U631H64SC25

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1
September 25, 2002
U631H64
!
High-performance CMOS non-
volatile static RAM 8192 x 8 bits
!
25, 35 and 45 ns Access Times
!
12, 20 and 25 ns Output Enable
Access Times
!
Software STORE Initiation
(STORE Cycle Time < 10 ms)
!
Automatic STORE Timing
!
10
5
STORE cycles to EEPROM
!
10 years data retention in
EEPROM
!
Automatic RECALL on Power Up
!
Software RECALL Initiation
(RECALL Cycle Time < 20
s)
!
Unlimited RECALL cycles from
EEPROM
!
Unlimited Read and Write to
SRAM
!
Single 5 V
10 % Operation
!
Operating temperature ranges:
0 to 70
C
-40 to 85
C
!
QS 9000 Quality Standard
!
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
!
Packages: PDIP28 (300 mil)
SOP28 (330 mil)
The U631H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The U631H64 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
SoftStore 8K x 8 nvSRAM
Pin Configuration
Pin Description
Top View
1
n.c.
VCC
28
2
A12
W
27
4
A6
A8
25
5
A5
A9
24
3
A7
n.c.
26
6
A4
A11
23
7
A3
G
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
PDIP
SOP
Signal Name
Signal Description
A0 - A12
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
Features
Description
2
September 25, 2002
U631H64
Block Diagram
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read L
H
L
Data
Outputs
Low-Z
Write
L
L
*
Data Inputs High-Z
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
200 mV from steady-state voltage.
a: Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Rating
a
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7
V
Input Voltage
V
I
-0.3
V
CC
+0.5
V
Output Voltage
V
O
-0.3
V
CC
+0.5
V
Power Dissipation
P
D
1
W
Operating Temperature
C-Type
K-Type
T
a
0
-40
70
85
C
C
Storage Temperature
T
stg
-65
150
C
EEPROM Array
128 x (64 x 8)
STORE
RECALL
SRAM
Array
128 Rows x
64 x 8 Columns
A5
A6
A7
A8
A9
A11
A12
Store/
Recall
Control
Ro
w
De
c
o
d
e
r
V
CC
V
SS
V
CC
G
E
W
Software
Detect
A0 - A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
A0 A1
A2
A3
A4 A10
I
n
p
u
t Bu
ffe
r
s
3
September 25, 2002
U631H64
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Operating Supply Current
b
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
t
c
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 35 ns
= 45 ns
90
80
75
95
85
80
mA
mA
mA
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
6
7
mA
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC(SB)1
V
CC
E
t
c
t
c
t
c
= 5.5 V
V
IH
= 25 ns
= 35 ns
= 45 ns
30
23
20
34
27
23
mA
mA
mA
Average Supply Current
at t
cR
= 200 ns
b
(Cycling CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
15
15
mA
Standby Supply Current
d
(Stable CMOS Input Levels)
I
CC(SB)
V
CC
E
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
1
1
mA
Recommended Operation
Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Input Low Voltage
V
IL
-2 V at Pulse Width
10 ns permitted
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+0.3
V
b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
c: I
CC2
is the average current requird for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
4
September 25, 2002
U631H64
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
2.4
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
OL
= 4.5 V
= 2.4 V
= 0.4 V
8
-4
8
-4
mA
mA
Input Leakage Current
High
Low
I
IH
I
IL
V
CC
V
IH
V
IL
= 5.5 V
= 5.5 V
= 0 V
-1
1
-1
1
A
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
V
CC
V
OH
V
OL
= 5.5 V
= 5.5 V
= 0 V
-1
1
-1
1
A
A
SRAM Memory Operations
No.
Switching Characteristics
Read Cycle
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
Read Cycle Time
f
t
AVAV
t
cR
25
35
45
ns
2
Address Access Time to Data Valid
g
t
AVQV
t
a(A)
25
35
45
ns
3
Chip Enable Access Time to Data Valid
t
ELQV
t
a(E)
25
35
45
ns
4
Output Enable Access Time to Data Valid
t
GLQV
t
a(G)
12
20
25
ns
5
E HIGH to Output in High-Z
h
t
EHQZ
t
dis(E)
13
17
20
ns
6
G HIGH to Output in High-Z
h
t
GHQZ
t
dis(G)
13
17
20
ns
7
E LOW to Output in Low-Z
t
ELQX
t
en(E)
5
5
5
ns
8
G LOW to Output in Low-Z
t
GLQX
t
en(G)
0
0
0
ns
9
Output Hold Time after Addr. Change
g
t
AXQX
t
v(A)
3
3
3
ns
10 Chip Enable to Power Activee
t
ELICCH
t
PU
0
0
0
ns
11 Chip Disable to Power Standby
d, e
t
EHICCL
t
PD
25
35
45
ns
e: Parameter guaranteed but not tested.
f:
Device is continuously selected with E and G both LOW.
g: Address valid prior to or at the same time with E transition LOW.
h: Measured
200 mV from steady state output voltage.
5
September 25, 2002
U631H64
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
No. Switching Characteristics
Write Cycle
Symbol
25
35
45
Unit
Alt. #1 Alt. #2
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
t
AVAV
t
AVAV
t
cW
25
35
45
ns
13 Write Pulse Width
t
WLWH
t
w(W)
20
30
35
ns
14 Write Pulse Width Setup Time
t
WLEH
t
su(W)
20
30
35
ns
15 Address Setup Time
t
AVWL
t
AVEL
t
su(A)
0
0
0
ns
16 Address Valid to End of Write
t
AVWH
t
AVEH
t
su(A-WH)
20
30
35
ns
17 Chip Enable Setup Time
t
ELWH
t
su(E)
20
30
35
ns
18 Chip Enable to End of Write
t
ELEH
t
w(E)
20
30
35
ns
19 Data Setup Time to End of Write
t
DVWH
t
DVEH
t
su(D)
12
18
20
ns
20 Data Hold Time after End of Write
t
WHDX
t
EHDX
t
h(D)
0
0
0
ns
21 Address Hold after End of Write
t
WHAX
t
EHAX
t
h(A)
0
0
0
ns
22 W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
10
13
15
ns
23 W HIGH to Output in Low-Z
t
WHQX
t
en(W)
5
5
5
ns
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Address Valid
Output Data Valid
High Impedance
ACTIVE
STANDBY
t
PD
t
PU
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(10)
(11)
t
a(A)
(2)
t
a(A)
Previous Data Valid
Output Data Valid
t
cR
Address Valid
t
v(A)
(1)
(2)
(9)
Ai
E
G
DQi
Output
I
CC
Ai
DQi
Output
6
September 25, 2002
U631H64
(15)
t
su(A)
Write Cycle #1: W-controlled
j
Write Cycle #2: E-controlled
j
L- to H-level
undefined
H- to L-level
i:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j:
E or W must be > V
IH
during address transitions.
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
su(E)
t
h(A)
t
w(W)
t
su(D)
t
dis(W)
t
en(W)
Address Valid
Input Data Valid
High Impedance
t
su(A-WH)
(12)
(16)
(13)
19
(20)
(23)
(21)
t
su(A)
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
w(E)
t
h(A)
t
su(D)
Address Valid
Input Data Valid
t
su(W)
(12)
(18)
(21)
(20)
(19)
(17)
(22)
Previous Data Valid
(14)
High Impedance
(15)
7
September 25, 2002
U631H64
No.
STORE Cycle Inhibit and
Automatic Power Up RECALL
Symbol
Min.
Max.
Unit
Alt.
IEC
24 Power Up RECALL Duration
k, e
t
RESTORE
650
s
Low Voltage Trigger Level
V
SWITCH
4.0
4.5
V
Nonvolatile Memory Operations
STORE Cycle Inhibit and Automatic Up RECALL
k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
V
CC
5.0 V
STORE inhibit
Power Up
V
SWITCH
t
RESTORE
RECALL
(24)
t
Software Mode Selection
E
W
A12 - A0
(hex)
Mode
I/O
Power
Notes
L
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
I
CC2
l, m
l, m
l, m
l, m
l, m
l
L
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l
l:
The six consecutive addresses must be in order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a Store cycle or (0000, 1555, 0AAA,
1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C.
m: I/O state assumes that G
V
IL
. Activation of nonvolatile cycles does not depend on the state of G.
8
September 25, 2002
U631H64
n: The software sequence is clocked with E controlled READs.
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by V
CC
< V
SWITCH
(STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when V
CC
exceeds V
SWITCH
and takes t
RESTORE
. V
CC
must not drop below
V
SWITCH
once it has been exceeded for the RECALL to function properly.
r:
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than t
a(E)
(see Read Cycle) but greater than or equal t
w(E)SR
, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
No. Software Controlled STORE/RECALL
Cycle
l, n
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
t
AVAV
t
cR
25
35
45
ns
26 Chip Enable to Output Inactive
o
t
ELQZ
t
dis(E)SR
600
600
600
ns
27 STORE Cycle Time
p
t
ELQXS
t
d(E)S
10
10
10
ms
28 RECALL Cycle Time
q
t
ELQXR
t
d(E)R
20
20
20
s
29 Address Setup to Chip Enable
r
t
AVELN
t
su(A)SR
0
0
0
ns
30 Chip Enable Pulse Width
r, s
t
ELEHN
t
w(E)SR
20
25
35
ns
31 Chip Disable to Address Change
r
t
EHAXN
t
h(A)SR
0
0
0
ns
Ai
E
DQi
Output
t
cR
t
w(E)SR
High Impedance
ADDRESS 1
VALID
VALID
Software Controlled STORE/RECALL Cycle
r, s, t, u
(E = HIGH after STORE initiation)
ADDRESS 6
t
cR
(25)
(25)
t
h(A)SR
(31)
(30)
t
su(A)SR
Ai
E
DQi
Output
t
cR
t
w(E)SR
High Impedance
ADDRESS 1
VALID
VALID
ADDRESS 6
t
d(E)S
(27)
(28)
(25)
t
h(A)SR
(31)
(30)
t
su(A)SR
(29)
t
dis(E)SR
(26)
t
h(A)SR
(31)
t
su(A)SR
(29)
t
w(E)SR
t
h(A)SR
(31)
(30)
t
su(A)SR
(29)
(5)
t
dis(E)
Software Controlled STORE/RECALL Cycle
r, s, t, u
(E = LOW after STORE initiation)
t
dis(E)SR
(26)
(29)
t
d(E)S
(27)
(28)
t
d(E)R
t
d(E)R
t:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H64 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
9
September 25, 2002
U631H64
Test Configuration for Functional Check
v: In measurement of t
dis
-times and t
en
-times the capacitance is 5 pF.
w: Between V
CC
and V
SS
must be connected a high frequency bypass capacitor 0.1
F to avoid disturbances.
Capacitance
e
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
V
CC
V
I
f
T
a
= 5.0 V
= V
SS
= 1MHz
= 25
C
C
I
8
pF
Output Capacitance
C
O
7
pF
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
Type
Package
Access Time
D = PDIP (300 mil)
25 = 25 ns
S = SOP28 (330 mil) Type 1
35 = 35 ns (on special request)
45 = 45 ns (on special request)
Operating Temperature Range
C = 0 to 70
C
K = -40 to 85
C
B
ESD Class
blank > 2000 V
x
B > 1000 V
D
U631H64
35
C
x:
ESD protection > 2000 V under development
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
V
IH
V
IL
V
SS
V
CC
w
480
255
30 pF
v
V
O
S
i
m
u
l
t
an
eo
us
m
e
a
s
ur
e
-
me
nt
of
al
l 8
ou
t
p
ut
pi
ns
In
pu
t le
v
e
l ac
c
o
r
d
in
g to

t
h
e
r
e
l
e
v
a
n
t
t
e
s
t
me
as
ur
em
en
t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
E
W
G
5 V
Internal Code
10
September 25, 2002
U631H64
Device Operation
The U631H64 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
SRAM READ
The U631H64 performs a READ cycle whenever E and
G are LOW while W is HIGH. The address specified on
pins A0 - A12 determines which of the 8192 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of t
cR
. If the READ is initiated by E or G, the outputs will
be valid at t
a(E)
or at t
a(G)
, whichever is later. The data
outputs will repeatedly respond to address changes
within the t
cR
access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid t
su(D)
before the end of a W controlled WRITE or
t
su(D)
before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
dis(W)
after W goes LOW.
Noise Consideration
The U631H64 is a high speed memory and therefore it
must have a high frequency bypass capacitor of appro-
ximately 0.1
F connected between V
CC
and V
SS
using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise
problems.
Software Nonvolatile STORE
The U631H64 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U631H64 implements nonvolatile operation
while remaining compatible with standard 8K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is first performed, followed by
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted and no STORE or RECALL will take
place.
To initiate the STORE cycle the following READ
sequence must be performed:
1.
Read address
0000
(hex) Valid READ
2.
Read address
1555
(hex) Valid READ
3.
Read address
0AAA (hex) Valid READ
4.
Read address
1FFF (hex) Valid READ
5.
Read address
10F0 (hex) Valid READ
6. Read
address
0F0F (hex) Initiate
STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence. It is not
necessary that G is LOW for the sequence to be valid.
After the t
STORE
cycle time has been fulfilled, the SRAM
will again be activated for READ and WRITE operation.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1.
Read address
0000
(hex) Valid READ
2.
Read address
1555
(hex) Valid READ
3.
Read address
0AAA (hex) Valid READ
4.
Read address
1FFF (hex) Valid READ
5.
Read address
10F0 (hex) Valid READ
6. Read
address
0F0E (hex) Initiate
RECALL
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Automatic Power Up RECALL
On power up, once V
CC
exceeds the sense voltage of
V
SWITCH
, a RECALL cycle is automatically initiated. The
voltage on the V
CC
pin must not drop below V
SWITCH
once it has risen above it in order for the RECALL to
operate properly.
11
September 25, 2002
U631H64
Due to this automatic RECALL, SRAM operation
cannot commence until t
RESTORE
after V
CC
exceeds
V
SWITCH
.
If the U631H64 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 K
resistor should be
connected between W and V
CC
.
Hardware Protection
The U631H64 offers hardware protection against inad-
vertent STORE operation through V
CC
sense.
For V
CC
< V
SWITCH
the software initiated STORE opera-
tion will be inhibited.
Low Average Active Power
The U631H64 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the V
CC
level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstrae 28
D-01109 Dresden P. O. B. 80 01 34 D-01101 Dresden Germany
Phone: +49 351 8822 306
Fax: +49 351 8822 337 Email: memory@zmd.de http://www.zmd.de
U631H64
September 25, 2002
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
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and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon
it. The information in this document describes the type of component and shall not be considered as assured cha-
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