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Электронный компонент: U634H256CSC25

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1
December 05, 2003
U634H256
Top View
SOP
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VCAP
A14
A12
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PowerStore 32K x 8 nvSRAM
Pin Configuration
Pin Description
Signal Name
Signal Description
A0 - A14
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCCX
Power Supply Voltage
VSS
Ground
VCAP
Capacitor
HSB
Hardware Controlled Store/Busy
!
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
!
25, 35 and 45 ns Access Times
!
10, 15 and 20 ns Output Enable
Access Times
!
I
CC
= 15 mA typ. at 200 ns Cycle
Time
!
Automatic STORE to EEPROM
on Power Down using external
capacitor
!
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
!
Automatic STORE Timing
!
10
5
STORE cycles to EEPROM
!
10 years data retention in
EEPROM
!
Automatic RECALL on Power Up
!
Software RECALL Initiation
(RECALL Cycle Time < 20
s)
!
Unlimited RECALL cycles from
EEPROM
!
Single 5 V
10 % Operation
!
Operating temperature ranges:
0 to 70
C
-40 to 85
C
-40/-55 to 125 C (only 35 ns)
!
QS 9000 Quality Standard
!
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
!
Packages: SOP32 (300 mil),
PDIP32 (600 mil, only C/K-Type)
The U634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U634H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 F capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The U634H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
PDIP
Features
Description
2
December 05, 2003
U634H256
Operating Mode
E
HSB
W
G
DQ0 - DQ7
Standby/not selected
H
H
*
*
High-Z
Internal Read
L
H
H
H
High-Z
Read L
H
H
L
Data
Outputs
Low-Z
Write
L
H
L
*
Data Inputs High-Z
Truth Table for SRAM Operations
Block Diagram
Absolute Maximum Ratings
a
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7
V
Input Voltage
V
I
-0.3
V
CC
+0.5
V
Output Voltage
V
O
-0.3
V
CC
+0.5
V
Power Dissipation
P
D
1
W
Operating Temperature
C-Type
K-Type
A-Type
M-Type
T
a
0
-40
-40
-55
70
85
125
125
C
C
C
C
Storage Temperature
T
stg
-65
150
C
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
200 mV from steady-state voltage.
*
H or L
a: Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
EEPROM Array
512 x (64 x 8)
STORE
RECALL
SRAM
Array
512 Rows x
64 x 8 Columns
A0 - A13
Store/
Recall
Control
HSB
Ro
w De
c
o
d
e
r
V
CCX
V
SS
V
CAP
G
E
W
Software
Detect
Power
Control
V
CCX
V
CAP
A5
A6
A7
A8
A9
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
A0 A1
A2
A3
A4A10
In
p
u
t Bu
ffe
r
s
A14
3
December 05, 2003
U634H256
DC Characteristics
Symbol
Conditions
C-Type
K-Type
A/M-Type
Unit
Min. Max. Min. Max. Min. Max.
Operating Supply Current
c
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
t
c
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 35 ns
= 45 ns
95
75
65
100
80
70
-
80
-
mA
mA
mA
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
= 5.5 V
0.2 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
6
7
7
mA
Average Supply Current during
PowerStore Cycle
I
CC4
V
CC
V
IL
V
IH
= 4.5 V
= 0.2 V
V
CC
-0.2 V
4
4
4
mA
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC(SB)1
V
CC
E
t
c
t
c
t
c
= 5.5 V
= V
IH
= 25 ns
= 35 ns
= 45 ns
40
36
33
42
38
35
-
38
-
mA
mA
mA
Operating Supply Current
at t
cR
= 200 ns
c
(Cycling CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
20
20
20
mA
Standby Supply Curent
d
(Stable CMOS Input Levels)
I
CC(SB)
V
CC
E
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
3
3
4
mA
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
b
V
CC
4.5
5.5
V
Input Low Voltage
V
IL
-2 V at Pulse Width
10 ns permitted
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+0.3
V
b: V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
c: I
CC1
and I
CC3
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
I
CC2
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION able.
The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
4
December 05, 2003
U634H256
DC Characteristics
Symbol
Conditions
Min.
Max.
Unit
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
OL
= 4.5 V
= 2.4 V
= 0.4 V
8
-4
mA
mA
Input Leakage Current
High
Low
I
IH
I
IL
V
CC
V
IH
V
IL
= 5.5 V
= 5.5 V
= 0 V
-1
1
A
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
V
CC
V
OH
V
OL
= 5.5 V
= 5.5 V
= 0 V
-1
1
A
A
No.
Switching Characteristics
Read Cycle
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1 Read Cycle Time
f
t
AVAV
t
cR
25
35
45
ns
2 Address Access Time to Data Valid
g
t
AVQV
t
a(A)
25
35
45
ns
3 Chip Enable Access Time to Data Valid
t
ELQV
t
a(E)
25
35
45
ns
4 Output Enable Access Time to Data Valid
t
GLQV
t
a(G)
10
15
20
ns
5 E HIGH to Output in High-Z
h
t
EHQZ
t
dis(E)
10
13
15
ns
6 G HIGH to Output in High-Z
h
t
GHQZ
t
dis(G)
10
13
15
ns
7 E LOW to Output in Low-Z
t
ELQX
t
en(E)
5
5
5
ns
8 G LOW to Output in Low-Z
t
GLQX
t
en(G)
0
0
0
ns
9 Output Hold Time after Address Change
t
AXQX
t
v(A)
3
3
3
ns
10 Chip Enable to Power Active
e
t
ELICCH
t
PU
0
0
0
ns
11 Chip Disable to Power Standby
d, e
t
EHICCL
t
PD
25
35
45
ns
SRAM Memory Operations
e: Parameter guaranteed but not tested.
f:
Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured
200 mV from steady state output voltage.
5
December 05, 2003
U634H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
No.
Switching Characteristics
Write Cycle
Symbol
25
35
45
Unit
Alt. #1
Alt. #2
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
t
AVAV
t
AVAV
t
cW
25
35
45
ns
13 Write Pulse Width
t
WLWH
t
w(W)
20
25
30
ns
14 Write Pulse Width Setup Time
t
WLEH
t
su(W)
20
25
30
ns
15 Address Setup Time
t
AVWL
t
AVEL
t
su(A)
0
0
0
ns
16 Address Valid to End of Write
t
AVWH
t
AVEH
t
su(A-WH)
20
25
30
ns
17 Chip Enable Setup Time
t
ELWH
t
su(E)
20
25
30
ns
18 Chip Enable to End of Write
t
ELEH
t
w(E)
20
25
30
ns
19 Data Setup Time to End of Write
t
DVWH
t
DVEH
t
su(D)
10
12
15
ns
20 Data Hold Time after End of Write
t
WHDX
t
EHDX
t
h(D)
0
0
0
ns
21 Address Hold after End of Write
t
WHAX
t
EHAX
t
h(A)
0
0
0
ns
22 W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
10
13
15
ns
23 W HIGH to Output in Low-Z
t
WHQX
t
en(W)
5
5
5
ns
t
a(A)
Previous Data Valid
Output Data Valid
t
cR
Address Valid
t
v(A)
Ai
(1)
(2)
(9)
Ai
E
G
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Output Data Valid
High Impedance
I
CC
ACTIVE
STANDBY
t
PD
t
PU
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(10)
(11)
t
a(A)
(2)
Address Valid
DQi
Output
DQi
Output
6
December 05, 2003
U634H256
L- to H-level
undefined
H- to L-level
i:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j:
E or W must be V
IH
during address transition.
Write Cycle #1: W-controlled
j
Write Cycle #2: E-controlled
j
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
su(E)
t
h(A)
t
w(W)
t
su(D)
t
dis(W)
t
en(W)
Address Valid
Input Data Valid
High Impedance
t
su(A-WH)
(12)
(16)
(13)
(19)
(20)
(23)
(21)
t
su(A)
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
w(E)
t
h(A)
t
su(D)
Input Data Valid
t
su(W)
(12)
(18)
(21)
(20)
(19)
(17)
(22)
Previous Data
(15)
(14)
High Impedance
(15)
t
su(A)
Address Valid
7
December 05, 2003
U634H256
Nonvolatile Memory Operations
Mode Selection
E
W
HSB
A13 - A0
(hex)
Mode
I/O
Power
Notes
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
l
L
L
H
X
Write SRAM
Input Data
Active
L
H
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
L
H
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
X
X
L
X
STORE/Inhibit
Output High Z
I
CC2
/Standby
m
k: The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0, 3C1F,
303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and dia
grams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l:
I/O state assumes that G
V
IL
. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
No.
PowerStore Power Up RECALL/
Hardware Controlled STORE
Symbol
Conditions
Min.
Max.
Unit
Alt.
IEC
24 Power Up RECALL Duration
n, e
t
RESTORE
650
s
25 STORE Cycle Duration
t
HLQX
t
d(H)S
V
CC
> 4.5 V
10
ms
26 HSB Low to Inhibit On
e
t
HLQZ
t
dis(H)S
1
s
27 HSB High to Inhibit Off
e
t
HHQX
t
en(H)S
700
ns
28 External STORE Pulse Width
e
t
HLHX
t
w(H)S
20
ns
HSB Output Low Current
e,o
I
HSBOL
HSB = V
OL
3
mA
HSB Output High Current
e, o
I
HSBOH
HSB = V
IL
5
60
A
Low Voltage Trigger Level
V
SWITCH
4.0
4.5
V
n: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
o: HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U634H256 to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U634H256 HSB pins.
8
December 05, 2003
U634H256
PowerStore and Automatic Power Up RECALL
Hardware Controlled STORE
DQi
Output
Previous Data Valid
HSB
t
en(H)S
t
d(H)S
Data Valid
t
dis(H)S
No.
Software Controlled STORE/RECALL
Cycle
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
29 STORE/RECALL Initiation Time
t
AVAV
t
cR
25
35
45
ns
30 Chip Enable to Output Inactive
s
t
ELQZ
t
dis(E)SR
600
600
600
ns
31 STORE Cycle Time
t
ELQXS
t
d(E)S
10
10
10
ms
32 RECALL Cycle Time
r
t
ELQXR
t
d(E)R
20
20
20
s
33 Address Setup to Chip Enable
t
t
AVELN
t
su(A)SR
0
0
0
ns
34 Chip Enable Pulse Width
s, t
t
ELEHN
t
w(E)SR
20
25
30
ns
35 Chip Disable to Address Change
t
t
EHAXN
t
h(A)SR
0
0
0
ns
t
w(H)S
q
(28)
(26)
(27)
(25)
High Impedance
V
CAP
5.0 V
t
PowerStore
Power Up
V
SWITCH
W
DQi
POWER UP
RECALL
BROWN OUT
t
RESTOR
E
t
RESTORE
BROWN OUT
PowerStore
(NO SRAM WRITES)
RECALL
(24)
(24)
NO STORE
t
PDSTORE
p
t
DELAY
p
p: t
PDSTORE
approximate t
d(E)S
or t
d(H)S
; t
DELAY
approximate t
dis(H)S
.
q: After t
w(H)S
HSB is hold down internal by STORE operation.
r: An automatic RECALL also takes place at power up, starting when V
CC
exceeds V
SWITCH
and takes t
RESTORE
. V
CC
must not drop below
V
SWITCH
once it has been exceeded for the RECALL to function properly.
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t:
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
9
December 05, 2003
U634H256
u: If the chip enable pulse width is less then t
a(E)
(see READ cycle) but greater than or equal to t
w(E)SR
, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
Ai
E
DQi
Output
t
cR
t
w(E)SR
ADDRESS 1
Software Controlled STORE/RECALL Cycle
t, u, v, w
(E = HIGH after STORE initiation)
ADDRESS 6
t
cR
(29)
(29)
t
h(A)SR
(35)
(34)
t
su(A)SR
(33)
Ai
E
DQi
Output
t
cR
t
w(E)SR
ADDRESS 1
VALID
VALID
ADDRESS 6
t
d(E)S
(31)
(32)
(29)
t
h(A)SR
(35)
(34)
t
su(A)SR
(33)
t
dis(E)SR
(30)
t
h(A)SR
(35)
t
su(A)SR
(33)
t
w(E)SR
t
h(A)SR
(35)
(34)
t
su(A)SR
(33)
(5)
t
dis(E)
Software Controlled STORE/RECALL Cycle
t, u, v, w
(E = LOW after STORE initiation)
t
dis(E)SR
(30)
High Impedance
High Impedance
t
d(E)S
(31)
(32)
VALID
VALID
t
d(E)R
t
d(E)R
10
December 05, 2003
U634H256
Test Configuration for Functional Check
V
CCX
Y
V
CAP
V
IH
V
IL
V
SS
480
255
30 pF
x
V
O
S
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m
e
as
ur
e
m
en
t
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
HSB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
5 V
A13
A14
x: In measurement of t
dis
-times and t
en
-times the capacitance is 5 pF.
y: Between V
CC
and V
SS
must be connected a high frequency bypass capacitor 0.1
F to avoid disturbances.
Capacitance
e
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
V
CC
V
I
f
T
a
= 5.0 V
= V
SS
= 1 MHz
= 25
C
C
I
8
pF
Output Capacitance
C
O
7
pF
All Pins not under test must be connected with ground by capacitors.
Example
IC Code Numbers
S
U634H256
25
C
Type
Operating Temperature Range
C =
0 to 70 C
K = -40 to 85 C
A = -40 to 125 C (only 35 ns and SOP32 package)
M = -55 to 125 C (only 35 ns and SOP32 package)
Access Time
25 = 25 ns
35 = 35 ns (C/K-Type on special request)
45 = 45 ns (on special request)
Package
D1 = PDIP32 (600 mil)
S = SOP32 (300 mil)
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
HSB
E
W
G
Internal Code
11
December 05, 2003
U634H256
Device Operation
The U634H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates In SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below V
SWITCH
. RECALL operations are
automatically initiated upon power up and may also
occur when the V
CCX
rises above V
SWITCH
, after a low
power condition. RECALL cycles may also be initiated
by a software sequence.
SRAM READ
The U634H256 performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The
address specified on pins A0 - A14 determines which of
the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of t
cR
. If the READ is initiated
by E or G, the outputs will be valid at t
a(E)
or at t
a(G)
,
whichever is later. The data outputs will repeatedly
respond to address changes within the t
cR
access time
without the need for transition on any control input pins,
and will remain valid until another address change or
until E or G is brought HIGH or W or HSB is brought
LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid t
su(D)
before the end of a W
controlled WRITE or t
su(D)
before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
dis(W)
after W goes LOW.
Automatic STORE
During normal operation, the U634H256 will draw cur-
rent from V
CCX
to charge up a capacitor connected to
the V
CAP
pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the V
CCX
pin drops below V
SWITCH
, the part
will automatically disconnect the V
CAP
pin from V
CCX
and initiate a STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of 100 F (
20 %) at 6 V.
Each U634H256 must have its own 100 F capacitor.
Each U634H256 must have a high quality, high fre-
quency bypass capacitor of 0.1 F connected between
V
CAP
and V
SS
, using leads and traces that are short as
possible. This capacitor do not replace the normal
expected high frequency bypass capacitor between the
power supply voltage and V
SS
.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
Automatic RECALL
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < V
SWITCH
)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
V
SWITCH
, a requested RECALL cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the U634H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 k
resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U634H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U634H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
12
December 05, 2003
U634H256
1.
Read address
0E38 (hex) Valid READ
2.
Read address
31C7 (hex) Valid READ
3.
Read address
03E0 (hex) Valid READ
4.
Read address
3C1F (hex) Valid READ
5.
Read address
303F (hex) Valid READ
6. Read
address
0FC0 (hex) Initiate
STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the t
STORE
cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1.
Read address
0E38 (hex) Valid READ
2.
Read address
31C7 (hex) Valid READ
3.
Read address
03E0 (hex) Valid READ
4.
Read address
3C1F (hex) Valid READ
5.
Read address
303F (hex) Valid READ
6. Read
address
0C63 (hex) Initiate
RECALL
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
HSB Nonvolatile STORE
The hardware controlled STORE Busy pin (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When
driven LOW by the internal chip circuitry it indicates that
a STORE operation (initiated via any means) is in pro-
gress within the chip. When driven LOW by external cir-
cuitry for longer than t
w(H)S
, the chip will conditionally
initiate a STORE operation after t
dis(H)S
.
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for t
dis(H)S
. During t
dis(H)S
, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
has been forced LOW, the WRITE will not occur and
the STORE operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bidirectional control line.
In order to allow a bank of U634H256s to perform syn-
chronized STORE functions, the HSB pin from a num-
ber of chips may be connected together. Each chip
contains a small internal current source to pull HSB
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it may optionally be pulled to power supply via
an external resistor with a value such that the combi-
ned load of the resistor and all parallel chip connections
does not exceed I
HSBOL
at V
OL
(see Figure 1 and 2).
Only if HSB is to be connected to external circuits, an
external pull-up resistor should be used.
During any STORE operation, regardless of how it was
initiated, the U634H256 will continue to drive the HSB
pin LOW, releasing it only when the STORE is com-
plete.
Upon completion of a STORE operation, the part will be
disabled until HSB actually goes HIGH.
Hardware Protection
The U634H256 offers hardware protection against
inadvertent STORE operation during low voltage condi-
tions. When V
CAP
< V
SWITCH
, all software or HSB initia-
ted STORE operations will be inhibited.
Preventing Automatic STORES
The PowerStore function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15 mA at V
OH
of at least 2.2 V as it will have to overpo-
wer the internal pull-down device that drives HSB LOW
for 50 ns at the onset of a PowerStore.
When the U634H256 is connected for PowerStore ope-
ration (see Figure 1) and V
CCX
crosses V
SWITCH
on the
way down, the U634H256 will attempt to pull HSB
LOW; if HSB doesn
t actually get below V
IL
, the part will
stop trying to pull HSB LOW and abort the PowerStore
attempt
.
Disabling Automatic STORES
If the PowerStore function is not required, then V
CAP
should be tied directly to the power supply and V
CCX
should by tied to ground. In this mode, STORE opera-
tion may be triggered through software control or the
HSB pin. In either event, V
CAP
(Pin 1) must always
have a proper bypass capacitor connected to it (Figure
2).
13
December 05, 2003
U634H256
Low Average Active Power
The U634H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the power supply voltage level
+
0.1
F
Bypass
100
F
20 %
V
CAP
V
SS
Power
Supply
V
CCX
HSB
10 k
(optional,
Figure 1: Automatic STORE Operation
Schematic Diagram
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
32
2
31
4
29
5
28
3
30
6
27
7
26
8
25
12
21
9
24
10
23
11
22
13
20
14
19
15
18
16
17
V
CAP
5.0 V
STORE inhibit
Power Up
V
SWITCH
t
RESTORE
RECALL
(24)
t
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
1
see description HSB
0.1
F
Bypass
V
CAP
V
SS
Power
Supply
V
CCX
HSB
10 k
(optional,
Figure 2: Disabling Automatic STORES
Schematic Diagram
32
2
31
4
29
5
28
3
30
6
27
7
26
8
25
12
21
9
24
10
23
11
22
13
20
14
19
15
18
16
17
1
see description HSB
nonvolatile store)
nonvolatile store)
Zentrum Mikroelektronik Dresden AG
Grenzstrae 28
D-01109 Dresden P. O. B. 80 01 34 D-01101 Dresden Germany
Phone: +49 351 8822 306
Fax: +49 351 8822 337 Email: memory@zmd.de http://www.zmd.de
December 05, 2003
U634H256
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance
upon it. The information in this document describes the type of component and shall not be considered as assu-
red characteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms
and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.