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Электронный компонент: U636H04BDC25

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December 12, 1997
U636H04
Preliminary
PowerStore 512 x 8 nvSRAM
Features
F
High-performance CMOS non-
volatile static RAM 512 x 8 bits
F
25 and 45 ns Access Times
F
12 and 25 ns Output Enable
Access Times
F
I
CC
= 15 mA at 200 ns Cycle Time
F
Unlimited Read and Write to
SRAM
F
Automatic STORE to EEPROM
on Power Down using system
capacitance
F
Automatic STORE Timing
F
10
5
STORE cycles to EEPROM
F
10 years data retention in
EEPROM
F
Automatic RECALL on Power Up
F
Unlimited RECALL cycles from
EEPROM
F
Single 5 V
10 % Operation
F
Operating temperature ranges:
0 to 70
C
-40 to 85
C
F
CECC 90000 Quality Standard
F
ESD characterization according
MIL STD 883C M3015.7-HBM
F
Packages: PDIP24 (600 mil)
SOP24 (300 mil)
Description
The U636H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM.
In this mode SRAM functions are
disabled.
The U636H04 is a fast static RAM
(25 and 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. Data
transfers from the SRAM to the
EEPROM (the STORE operation)
take place automatically upon
power down using charge stored in
system capacitance. Transfers
from the EEPROM to the SRAM
(the RECALL operation) take place
automatically on power up.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile date resi-
des in EEPROM.
The U636H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Pin Configuration Pin Description
Signal Name Signal Description
A0 - A8 Address Inputs
DQ0 - DQ7 Data In/Out
E
Chip Enable
G
Output Enable
W
Write Enable
VCC Power Supply Voltage
VSS Ground
2
A6 A8
23
3
A5 n.c.
22
1
A7 VCC
24
4
A4 W
21
5
A3
G
20
6
A2 n.c.
19
10
DQ1 DQ5
15
7
A1 E
18
8
A0 DQ7
17
9
DQ0 DQ6
16
11
DQ2 DQ4
14
12
VSS DQ3
13
Top View
PDIP
SOP
2
December 12, 1997
U636H04
Preliminary
Operating Mode E
W
G
DQ0 - DQ7
Standby/not selected H
*
*
High-Z
Internal Read L H H High-Z
Read L H L Data Outputs Low-Z
Write L L
*
Data Inputs High-Z
Truth Table for SRAM Operations
Block Diagram
a:
Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
a
Symbol Min. Max. Unit
Power Supply Voltage V
CC
-0.5 7 V
Input Voltage V
I
-0.3 V
CC
+0.5 V
Output Voltage V
O
-0.3 V
CC
+0.5 V
Power Dissipation P
D
1
W
Operating Temperature C-Type
K-Type
T
a
0
-40
70
85
C
C
Storage Temperature T
stg
-65 150
C
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
200 mV from steady-state voltage.
*
H or L
I
n
p
u
t
B
u
ffe
r
s
EEPROM Array
16 x (32 x 8)
RECALL
SRAM
Array
16 Rows x
(32 x 8) Columns
G
E
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
Store/
Recall
V
CC
R
o
w
D
e
c
oder
A5
A6
A7
A8
A0 A1 A2 A3 A4
V
CC
V
SS
Power
Control
STORE
3
December 12, 1997
U636H04
Preliminary
b: I
CC1
and I
CC3
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
c: I
CC2
and I
CC4
are the average currents required for the duration of the respective STORE cycles (STORE Cycle Time).
d:
Bringing E
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
DC Characteristics Symbol Conditions
C-Type K-Type
Unit
Min. Max. Min. Max.
Operating Supply Current
b
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 45 ns
90
75
95
80
mA
mA
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
= 5.5 V
0.2 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
6
7
mA
Average Supply Current during
PowerStore
Cycle
c
I
CC4
V
CC
V
IL
V
IH
= 4.5 V
= 0.2 V
V
CC
-0.2 V
4
4
mA
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC(SB)1
V
CC
E
t
c
t
c
= 5.5 V
= V
IH
= 25 ns
= 45 ns
30
20
34
23
mA
mA
Operating Supply Current
at t
cR
= 200 ns
b
(Cycling CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
15 15 mA
Standby Supply Curent
d
(Stable CMOS Input Levels)
I
CC(SB)
V
CC
E
V
IL
V
IH
= 5.5 V
V
CC
-0.2 V
0.2 V
V
CC
-0.2 V
3
3
mA
Recommended
Operating Conditions
Symbol Conditions Min. Max. Unit
Power Supply Voltage V
CC
4.5 5.5 V
Input Low Voltage V
IL
-2 V at Pulse Width
10 ns permitted
-0.3 0.8 V
Input High Voltage V
IH
2.2 V
CC
+ 0.3 V
4
December 12, 1997
U636H04
Preliminary
SRAM MEMORY OPERATIONS
e:
Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g:
Address valid prior to or coincident with E transition LOW.
h:
Measured
200 mV from steady state output voltage.
DC Characteristics Symbol Conditions
C-Type K-Type
Unit
Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
2.4
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
OL
= 4.5 V
= 2.4 V
= 0.4 V 8
-4
8
-4 mA
mA
Input Leakage Current
High
Low
I
IH
I
IL
V
CC
V
IH
V
IL
= 5.5 V
= 5.5 V
= 0 V -1
1
-1
1
A
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
V
CC
V
OH
V
OL
= 5.5 V
= 5.5 V
= 0 V -1
1
-1
1
A
A
No.
Switching Characteristics
Read Cycle
Symbol 25 45
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
1
Read Cycle Time
f
t
AVAV
t
cR
25 45 ns
2 Address Access Time to Data Valid
g
t
AVQV
t
a(A)
25 45 ns
3 Chip Enable Access Time to Data Valid t
ELQV
t
a(E)
25 45 ns
4 Output Enable Access Time to Data Valid t
GLQV
t
a(G)
12 25 ns
5
E HIGH to Output in High-Z
h
t
EHQZ
t
dis(E)
13 20 ns
6
G HIGH to Output in High-Z
h
t
GHQZ
t
dis(G)
13 20 ns
7
E LOW to Output in Low-Z t
ELQX
t
en(E)
5
5
ns
8
G LO W to Output in Low-Z t
GLQX
t
en(G)
0
0
ns
9 Output Hold Time after Address Change t
AXQX
t
v(A)
3
3
ns
10 Chip Enable to Power Active
e
t
ELICCH
t
PU
0
0
ns
11 Chip Disable to Power Standby
d, e
t
EHICCL
t
PD
25 45 ns
5
December 12, 1997
U636H04
Preliminary
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
No.
Switching Characteristics
Write Cycle
Symbol 25 45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max.
12
Write Cycle Time t
AVAV
t
AVAV
t
cW
25 45 ns
13
Write Pulse Width t
WLWH
t
w(W)
20 35 ns
14
Write Pulse Width Setup Time t
WLEH
t
su(W)
20 35 ns
15
Address Setup Time t
AVWL
t
AVEL
t
su(A)
0
0
ns
16
Address Valid to End of Write t
AVWH
t
AVEH
t
su(A-WH)
20 35 ns
17
Chip Enable Setup Time t
ELWH
t
su(E)
20 35 ns
18
Chip Enable to End of Write t
ELEH
t
w(E)
20 35 ns
19
Data Setup Time to End of Write t
DVWH
t
DVEH
t
su(D)
12 20 ns
20
Data Hold Time after End of Write t
WHDX
t
EHDX
t
h(D)
0
0
ns
21
Address Hold after End of Write t
WHAX
t
EHAX
t
h(A)
0
0
ns
22
W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
10 15 ns
23
W HIGH to Output in Low-Z t
WHQX
t
en(w)
5
5
ns
t
a(A )
Previous
Data Valid
Output Data
Valid
t
cR
Address Valid
t
v(A)
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
Ai
DQi
Output
1
2
9
Ai
E
G
DQi
Output
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Address Valid
Output Data
Valid
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
High Impedance
I
CC
t
PD
t
PU
1
3
4
5
7
6
8
10
11
t
a(A)
2
ACTIVE
STANDBY
6
December 12, 1997
U636H04
Preliminary
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
A
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
A
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A
A
A
A
L- to H-level
undefined H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be V
IH
during address transition.
Write Cycle #1: W-controlled
j
Write Cycle #2: E-controlled
j
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
su(E)
t
h(A )
t
w(W)
t
su(D)
t
dis(W)
t
en(W)
Address Valid
Input Data
Valid
High Impedance
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
t
su(A-WH)
12
16
13
19 20
23
21
t
su(A )
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
w(E)
t
h(A)
t
su(D)
Address Valid
Input Data
Valid
t
su(W)
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
12
18 21
20
19
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AA
17
22
Previous Data
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
15
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
AA
14
High Impedance
15
t
su(A)
7
December 12, 1997
U636H04
Preliminary
NONVOLATILE MEMORY OPERATIONS
MODE SELECTION
k: reserved for future development
l: reserved for future development
m: I/O state assumes that G
V
IL
.
n: An automatic RECALL also takes place at power up, starting when V
CC
exceeds V
SWI TCH
and takes t
RESTORE
. V
CC
must not drop below
V
SWITCH
once it has been exceeded for the RECALL to function properly.
E
W
A8 - A0
(hex)
Mode I/O Power Notes
H X X Not Selected Output High Z Standby
L H X Read SRAM Output Data Active m
L L X Write SRAM Input Data Active
No.
PowerStore
Power Up RECALL
Symbol
Conditions Min. Max. Unit
Alt. IEC
24
Power Up RECALL Duration
n, e
t
RESTORE
650
s
25
STORE Cycle Duration
f
t
PDSTORE
the power supply vol-
tage must stay above
3.6 V for at least
10 ms after the start
of the STORE
operation
10 ms
26
Time allowed to Complete SRAM
Cycle
f, e
t
DELAY
1
s
Low Voltage Trigger Level V
SWITCH
4.0 4.5 V
8
December 12, 1997
U636H04
Preliminary
A
A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
CC
5.0 V
t
PowerStore
Power Up
V
SWITCH
W
DQi
PO WER UP
RECALL
BROWN OUT
t
RESTORE
t
RESTORE
BROWN OUT
PowerStore
(NO SRAM WRITES)
RECALL
24 24
t
PDSTORE
25
t
DELAY
26
NO STORE
PowerStore
and automatic Power Up RECALL
o ... t reserved for future development
u, v reserved for future development
9
December 12, 1997
U636H04
Preliminary
IC Code Numbers
Type
Package Access Time
25 = 25 ns
45 = 45 ns (on special request)
Operating Temperature Range
C =
0 to 70
C
K = -40 to 85
C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
y: ESD protection > 2000 V under development
B
ESD Class
blank > 2000 V
y
B > 1000 V
D
U636H04
25
C
Example
D = PDIP (600 mil)
S = SOP (300 mil)
All Pins not under test must be connected with ground by capacitors.
Capacitance
e
Conditions Symbol Min. Max. Unit
Input Capacitance
V
CC
= 5.0 V
V
I
= V
SS
C
I
8
pF
Output Capacitance
f = 1 MHz
T
a
= 25 C
C
O
7
pF
Test Configuration for Functional Check
V
IH
V
IL
V
SS
V
CC
x
480
255
30 pF
w
V
O
Si
m
u
l
t
aneou
s
m
eas
ur
e-
m
e
nt
of

a
l
l

8 out
put
pi
ns
I
npu
t
l
e
v
e
l
ac
c
o
r
d
i
ng t
o
t
he
r
e
l
e
v
ant

t
e
s
t
m
eas
ur
em
ent
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
w: In measurement of t
dis
-times and t
en
-times the capacitance is 5 pF.
x:
Between V
CC
and V
SS
must be connected a high frequency bypass capacitor 0.1
F to avoid disturbances.
5 V
A0
A1
A2
A3
A4
A5
A6
A7
A8
E
W
G
10
December 12, 1997
U636H04
Preliminary
Device Operation
The U636H04 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below V
SWITCH
. RECALL operations are automatically
initiated upon power up and may occur also when V
CC
rises above V
SWITCH
after a low power condition.
SRAM READ
The U636H04 performs a READ cycle whenever E and
G are LOW and W are HIGH. The address specified on
pins A0 - A8 determines which of the 512 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of t
cR
. If the READ is initiated by E or G, the outputs will
be valid at t
a(E)
or at t
a(G)
, whichever is later. The data
outputs will repeatedly respond to address changes
within the t
cR
access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LO W.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid t
su(D)
before the end of a W controlled WRITE or
t
su(D)
before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
dis(W)
after W goes LOW.
AUTOMATIC STORE
The U636H04 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long
as the system power supply take at least t
PDSTORE
to
decay from V
SWITCH
down to 3.6 V the U636H04 will
safely and automatically STORE the SRAM data in
EEPROM on power down.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle.
AUTOMATIC RECALL
During power up an automatic RECALL takes place.
After any low power condition (V
CC
< V
SWITCH
) an inter-
nal RECALL request may be latched. When V
CC
once
again exceeds the sense voltage of V
SWITCH
, a reque-
sted RECALL cycle will automatically be initiated and
will take t
RESTORE
to complete.
If the U636H04 is in a WRITE state at the end of a
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 K
resistor should be
connected between W and system V
CC
.
HARDWARE PROTECTION
The U636H04 offers hardware protection against inad-
vertent STORE operation through V
CC
Sense. When
V
CC
< V
SWITCH
all software controlled STORE operati-
ons will be inhibited.
LOW AVERAGE ACTIVE POWER
The U636H04 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LO W)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the V
CC
level
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Memory Products 1998
PowerStore 512 x 8 nvSRAM U636H04
Zentrum Mikroelektronik Dresden GmbH
Grenzstrae 28
D-01109 Dresden
P.
O.
B. 80
01
34
D-01101 Dresden
Germany
Phone: +49 351 88 22-3 06 Fax: +49 351 88 22-3 37 Email: sales@zmd.de
Internet Web Site: http://www.zmd.de