December 12, 1997

Maintenance only

UD61464

64K x 4 DRAM

Features

Dynamic random access memory

65536 x 4 bits manufactured
using a CMOS technology

RAS access times 70 ns/80 ns

TTL-compatible

Three-state outputs bidirectional

256 refresh cycles

4 ms refresh cycle time

FAST PAGE MODE

Operating modes: Read, Write,

Read - Write,
RAS only Refresh,
Hidden Refresh with address
transfer

Low power dissipation

Power supply voltage 5 V

Package PDIP18 (300 mil)

Operating temperature range

0 to 70 癈

Quality assessment according to

CECC 90000, CECC 90100 and
CECC 90112

Description

Addressing
The UD61464 is a dynamic random
access memory organized 65536
words by 4 bits.

FPM facilitates faster data operation
with predefined row address. Via 8
address inputs the 16 address bits
are transmitted into the internal
address memories in a time-multi-
plex operation. The falling RAS-
edge takes over the row address.
After the row address hold time the
column address can be applied. The
bit pattern that is available at the
address outputs during the set-up
time and after the falling edge of
CAS is interpreted as row address.
During Write the column address is
taken over with the falling edge of
the control signal CAS, or W, whi-
chever becomes active as the last.
The selection of one or more
memory circuits can be made via the
RAS input.

Read-Write-Control
The choice between Read or Write
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
meanwhile LOW leads to a Write
cycle.
Both CAS-controlled and W-control-
led Write cycles are possible with
activated RAS signal.

Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic ,,0" or ,,1".
If the memory cycle is a Read,
Read-Write or a Write cycle (W-con-
trolled), Q changes from High-Z
state to the active state (,,0" or ,,1").
After access time, the contents of
the selected cell will be available,
with the exception of the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
Through storaging the data on out-
put, they remain valid from the end
of access time until the start of
another cycle.

Pin Configuration

VSS

DQ0

DQ3

DQ2

RAS

DQ1

CAS

VCC

(OE)

(WE)

Pin Description

Signal Name Signal Description

A0 - A7 Address Inputs

DQ0 - DQ3 Data In/Out

Read, Write Control

RAS

Row Address Strobe

Output Enable

VCC Power Supply Voltage

VSS Ground

CAS

Column Address Strobe

Top View

PDIP

December 12, 1997

UD61464

Row

Decoder

Row

Decoder

Operation

Function

RAS

CAS

Address

Data

Stand-by

High-Z

Read

Row

Column

Output

Data

Write

Row

Column

Input Data

Read-Write

Row

Column

Output

Data/Input

Data

FPM

Read

1st

cycle

Row

Column

Output

Data

2nd

cycle

Column

Output

Data

FPM
Write

1st

cycle

Row

Column

Input Data

2nd

cycle

Column

Input Data

FPM
Read-Write

1st

cycle

Row

Column

Output

Data/Input

Data

2nd

cycle

Column

Output

Data/Input

Data

RAS only Refresh

Row

High-Z

HIDDEN Refresh

Read L

Row

Column

Output

Data

Write

Row

Column

Input Data

*) Transfer of Refresh Address required

Block Diagram

Clock Generator

M
U
X

128

Kbi

t
A

r
r
a

i
t
h

Sens

i
f
i
e

128 Kbi

t
Ar

r
a

i
t
h

Sens

i
f
i
e

nput

4 Write-Read-Amplifiers

Write-Read-Control

Output Control

Data Input and

Output Amplifier

DQ0

DQ1

DQ2

DQ3

CAS

RAS

A0X to A7X

A0Y to A7Y

December 12, 1997

UD61464

Characteristics

All voltages are referenced to V

= 0 V (ground).

All characteristics are valid in the power supply voltage range and operating temperature range indicated below.

All pins not under test must be connected with ground by capacitors.

Absolute Maximum Ratings

Symbol

Min.

Max.

Unit

Power Supply Voltage

-0.5

7.0

Input Voltage

-1.0

7.0

Output Voltage

-1.0

7.0

Output Current

1a)

-50

Power Dissipation

Operating Temperature

�

Storage Temperature

stg

-55

125

�

Remarks: see page 7

Recommended Operating Conditions

Symbol

Min.

Max.

Unit

Power Supply Voltage

4.5

5.5

Input Low Voltage

-1.0

0.8

Input High Voltage

2.4

5.5

Remark: see page 7

Capacitances

Conditions

Symbol

Min.

Max.

Unit

Input Capacitance
A0 to A7

= 5.0 V

= 1 MHz

= 25

�

Input Capacitance
RAS, CAS, W and G

Output Capacitance DQ0 to DQ3

December 12, 1997

UD61464

Static Characteristics

Conditions

Symbol

Min.

Max.

Unit

DC07

DC08

DC07

DC08

Power Supply Current
(average value of RAS-CAS cycles)

= t

cWmin

= t

cRmin

CC1

Refresh Current
(average value of RAS cycles)

CAS = V

= t

cWmin

= t

cRmin

CC2

FPM Current
(average value of FPM cycles)

RAS = VIL

cPG

= t

cPGmin

CC3

Stand-by Current (TTL Level)

RAS = CAS = V

CC4

Stand-by Current (CMOS Level)

RAS = V

- 0.2 V

CAS = V

-0.2 V

CC5

Output High Voltage

= -5 mA

2.4

Output Low Voltage

= 4.2 mA

0.4

Input Leakage Current
at any input,
all other pins = 0 V

= 0 V to 5.5 V

-10

�

Output Leakage Current
Q = High-Z

= 0 V to 5.5 V

RAS = CAS = V

-10

�

Remarks: see page 7

December 12, 1997

UD61464

Dynamic Characteristics

Symbol

Min.

Max.

Unit

Alt.

IEC

DC07

DC08

DC07

DC08

ALL CYCLES

Transition Time (Rise and Fall)

RAS Precharge Time
CAS Precharge Time

w(RASH)

w(CASH)

50
10

60
10

ns
ns

Row Address Set-up Time
Column Address Set-up Time

ASR

ASC

su(RA-RAS)

su(CA-CAS)

0
0

ns
ns

Row Address Hold Time
Column Address Hold Time ref. to RAS
Column Address Hold Time

RAH

CAH

h(RAS-RA)

h(RAS-CA)

h(CAS-CA)

10
55
15

10
60
15

ns
ns
ns

Output Buffer Turn-off Delay Time
Output Buffer Turn-off Delay Time from G

OFF

OEZ

v(CAS)

v(G)

0
0

20
20

ns
ns

CAS to RAS Precharge Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period

CRP

RAD

RAL

CLZ

REF

CASH-RASL

RAS-CA

CA-RASH

CASL-QX

15
35

15
40

ns
ns
ns
ns

READ

Random Read Cycle Time

130

150

Access Time from RAS
Access Time from Column Address
Access Time from CAS
G Access Time

RAC

CAC

OEA

a(RAS)

a(CA)

a(CAS

)

a(G)

70
35
20
20

80
40
20
20

ns
ns
ns
ns

RAS Pulse Width
CAS Pulse Width

RAS

CAS

w(RASL)

w(CASL)

70
20

80
20

10000
10000

ns
ns

Read Command Set-up Time

RCS

su(R-CAS)

Read Command Hold Time ref. to RAS
Read Command Hold Time

RRH

RCH

h(RAS-R)

h(CAS-R)

0
0

ns
ns

RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
RAS Hold Time referenced to G

RCD

CSH

RSH

ROH

RASL-CASL

RASL-CASH

CASL-RASH

GL-RASH

20
70
20
10

20
80
20
10

ns
ns
ns
ns

Remarks: see page 7

December 12, 1997

UD61464

WRITE

Random Write Cycle Time

130

150

RAS Pulse Width
CAS Pulse Width
Write Command Pulse Width

RAS

CAS

w(RASL)

w(CASL)

w(W)

70
20
15

80
20
15

10000
10000

ns
ns
ns

Write Command Set-up Time
Data Set-up Time ref. to CAS
Data Set-up Time ref. to W

14)

12)

WCS

su(W-CAS)

su(D-CAS)

su(D-W)

0
0
0

ns
ns
ns

Write Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data Hold Time ref. to CAS
Data Hold Time ref. to W
G Command Hold Time

12)

WCH

RWL

CWL

OEH

h(CAS-W)

h(W-RAS)

h(W-CAS)

h(CAS-D)

h(W-D)

h(W-GL)

15
20
20
15
15
20

ns
ns
ns
ns
ns
ns

RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time

RCD

CSH

RSH

RASL-CASL

RASL-CASH

CASL-RASH

20
70
20

20
80
20

ns
ns
ns

READ-WRITE

Read-Write Cycle Time

RWC

cRW

185

205

RAS Pulse Width
CAS Pulse Width

RAS

CAS

w(RASL)RW

w(CASL)RW

125

135

10000
10000

ns
ns

CAS Hold Time

RAS to WRITE Delay Time
CAS to WRITE Delay Time
Column to WRITE Delay Time

14)

CSH

RWD

CWD

AWD

(RASL-

CASH)RW

RAS-W

CAS-W

(CA-W)RW

125

100

50
65

135

110

50
70

ns
ns
ns

FPM Read

Fast Page Mode Cycle Time
RAS Pulse Width

RASP

cPG

w(RASL)

50
70

50
80

100000

ns
ns

Access Time from CAS Precharge

CPA

a(CASH)

FPM Write

Fast Page Mode Cycle Time

cPG

Remarks: see page 7

Dynamic Characteristics

Symbol

Min.

Max.

Unit

Alt.

IEC

DC07

DC08

DC07

DC08

December 12, 1997

UD61464

FPM Read-Write

FPM Cycle Time

c(PG)RW

100

Access Time from CAS Precharge

CPA

a(CASH)

HIDDEN REFRESH

CAS Hold Time (CAS before RAS Cycle)

CHR

RASL-CASH

Remark: see below

Dynamic Characteristics

Symbol

Min.

Max.

Unit

Alt.

IEC

DC07

DC08

DC07

DC08

Remarks:

The Input Low Voltage must not
drop below -0.3 V for more than
40 ns.

1a)

The total sum of the absolute
values of output currents must
not exceed 100 mA in case of
static application.

The current is inversely propor-
tional to the cycle time; the max.
current is measured in the shor-
test cycle time.

For test conditions see test confi-
guration for functional test and
clock timing.

IHmin

and V

ILmax

are reference

levels for time measurement of
the input signals; transition times
are measured between V

and

v(CAS)

and t

v(G)

define the time at

which the data output goes to
High-Z; this time is not related to
any level.

RASL-CASLmax

and t

v(G)

are given

as reference points only; they do
not represent restrictive conditi-
ons.

The values of t

cWmin

, t

cRmin

and

cRWmin

are used for indication of

the particular cycle time in which
full function is guaranteed in the
temperature range from 0 to
70

�

C. Values below the one

shown above may cause perma-
nent damage to the component.

Measured with a load equivalent
to 2 TTL loads, 100 pF.

In Read cycle either t

h(RAS-R)

h(CAS-R)

must be kept.

10)

h(RASH-CA)

is only required if the

valid data are to be held beyond
the rising edge of RAS.

11)

su(W-CAS)

, t

RAS-W

, t

CAS-W

and

(CA-W)RW

do not represent

restrictive parameters:

- if t

su(W-CAS)

su(W-CAS)min

and

h(CASH-W)

h(CASH-W)min

, the

cycle is a Write cycle (CAS-con-
trolled), and the data output
remains in High-Z throughout the
whole CAS cycle,

- if t

CAS-W

> t

CAS-Wmin

, t

RAS-W

> t

RAS-Wmin

and t

(CA-W)RW

> t

(CA-

W)RWmin

, the cycle is a Read-

Write cycle, and the content of
the cell is available at the data
output,

- if none of these conditions is
satisfied, the condition of the
data output (at access time) is

indeterminate, since a Write
cycle (W-controlled) is carried
out.

12)

These parameters refer to CAS
during Write (CAS-controlled),
and to W (W-controlled) or to W
during Read-Write.

14)

su(W-CAS)

, t

RAS-W

, t

CAS-W

and t

(CA-

W)RW

do not represent restrictive

parameters:

- if t

su(W-CAS)

su(W-CAS)min

the

cycle is a Write cycle (CAS-con-
trolled) and the data output
remains in High-Z throughout the
whole CAS cycle,

- if t

CAS-W

> t

CAS-Wmin

, t

RAS-W

> t

RAS-Wmin

and t

(CA-W)RW

> t

(CA-

W)RWmin

, the cycle is a Read-

Write cycle, and the content of
the cell is available at the data
output,

- if none of these conditions is

satisfied, the condition of the
data output (at access time) is
indeterminate, since a Write
cycle (W-controlled) is carried
out.

December 12, 1997

UD61464

IC Code Numbers

Test Configuration for Functional Check

t
put

l
t
age

hec

r
d

i
n

i
m

i
ng

r
a

I
nput

l
t
ag

e ac

r
d

i
ng t

i
m

i
ng di

r
a

(
a

l
e

t
8 oper

i
n

g c

l
es

f
o

r
e

eas

ent

)
.

l
addr

r
e

t
o

be c

ed.

5 V

1,2 K

100 pF

680

DQ0
DQ1
DQ2
DQ3

A0
A1
A2
A3
A4
A5
A6
A7

RAS
CAS
W
G

UD61464

C = 0 to 70 癈

Type

Access Time

Package

07 = 70 ns
08 = 80 ns

D = PDIP

Example

Operating Temperature Range

The date of manufacture is given by the 4 last digits of the mark, the 2 first digits indicating the year, and the last 2
digits the calendar week.

December 12, 1997

UD61464

AAAA

AAA

AAAA

AAA

AAAA

Read

AAA

AAAA

w(RASL)

w(RASH)

CASL-RASH

CASH-RASL

CASH-RA SL

RASL-CASH

RASL-CASL

w(CA SL)

su(R-CAS)

CA -RASH

h(CAS-R)

h(RAS-R)

su(CA-CAS)

a(CAS)

h(RA S-CA)

su(RA-RAS)

h(RAS-RA )

h(CAS-CA )

CA SL-QX

a(CA )

RAS-CA

a(RA S)

a(G)

v(G)

v(CAS)

Output Data

RAS

CAS

A0 - A7

DQ0-
DQ3

AAA

w(RA SL)

w(RASH)

RA SL-CA SH

RA SL-CASL

w(CASL)

CA SL-RA SH

CASH-RASL

h(W-CAS)

CA SH-RA SL

h(W-RAS)

w(W)

su(W-CA S)

h(RAS-CA )

h(CAS-W)

su(RA-RAS)

CA-RA SH

h(RA S-RA)

RAS-CA

su(CA-CAS)

h(CAS-CA)

h(CAS-D)

su(D-CA S)

Input Data

RAS

CAS

A0 - A7

DQ0-
DQ3

Write (CAS-controlled)

December 12, 1997

UD61464

AAAA

w(RA SL)

w(RA SH)

RA SL-CA SH

w(CA SH)

CASL-RASH

RASL-CASL

CA SH-RA SL

w(CA SL)

h(W-CA S)

h(W-RAS)

h(CA S-W)

w(W)

h(RA S-CA)

AAA

su(RA-RAS)

h(RA S-RA)

CA -RA SH

h(CA S-CA)

RAS-CA

su(CA -CAS)

su(D-W)

h(W-D)

h(W-GL)

v(G)

Input Data

RAS

CAS

A0 - A7

DQ0-
DQ3

AAAA

Read-Write

CASH-RASL

su(RA -RA S)

RAS

CAS

A0 - A7

DQ0 -
DQ3

AAAA

AAA

cRW

w(RASL)

w(RASH)

CASL-RASH

RA SL-CA SH

RASL-CASL

w(CASL)RW

CA SH-RASL

su(R-CAS)

CAS-W

h(W-RA S)

RA S-W

h(W-CA S)

w(W)

h(RAS-CA )

h(RAS-RA )

h(CAS-CA )

su(CA -CA S)

(CA -W)RW

a(CAS)

h(W-D)

su(D-W)

O. D.

a(CA)

RAS-CA

a(RA S)

a(G)

v(G)

AAAA

Input Data

Write (W-controlled)

December 12, 1997

UD61464

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

FPM Read

w(RASH)

w(RA SL)

RA SL-CASH

cPG

CASH-RA SL

RASL-CASL

w(CASL)

w(CA SH)

w(CASL)

w(CASH)

CA SL-RA SH

h(RAS-R)

CASH-RASL

w(CA SL)

h(CAS-R)

su(R-CAS)

h(CAS-R)

su(R-CAS)

h(CA S-R)

su(R-CAS)

su(RA -RA S)

h(RA S-RA)

su(CA -CAS)

h(CAS-CA)

su(CA-CAS)

h(CAS-CA)

su(CA -CAS)

CA-RA SH

h(CA S-CA)

a(CA )

RAS-CA

a(RA S)

a(CA )

a(CASH)

a(CA SH)

v(CAS)

CA SL-QX

a(G)

v(G)

CASL-QX

a(G)

v(G)

a(G)

v(G)

v(CAS)

AAA

CASL-QX

RAS

CAS

A0 - A7

DQ0 -
DQ3

Outp. D.

AAAA

w(RA SL)

w(RASH)

cPG

RA SL-CASH

RA SL-CASL

CA SH-RA SL

w(CASL)

w(CA SH)

w(CA SL)

w(CA SH)

w(CASL)

CASL-RA SH

CASH-RASL

h(W-CA S)

h(W-CAS)

su(W-CAS)

h(CAS-W)

su(W-CAS)

w(W)

h(CAS-W)

su(W-CAS)

w(W)

CA-RASH

h(CAS-

CA )

su(CA -CA S)

h(CAS-CA )

su(CA-CAS)

h(CAS-CA )

h(RAS-CA )

h(RAS-RA )

su(CA -CAS)

AAA

RA S-CA

su(RA-RAS)

su(D-CAS)

h(CA S-D)

su(D-CA S)

h(CAS-D)

su(D-CA S)

h(CAS-D)

h(W-RAS)

RAS

CAS

A0 - A7

DQ0 -
DQ3

Input Data

FPM Write (CAS-controlled)

AAAA

AAA

AAAA

AAA

December 12, 1997

UD61464

AAAA

AAA

AAAA

AAA

AAAA

w(RA SL)

w(RA SH)

CA SH-RA SL

su(RA -RA S)

h(RAS-RA )

RAS

CAS

A0 - A7

DQ0 -
DQ3

AAAA

AAA

AAAA

FPM Read-Write

cRW

w(RA SL)

w(RA SH)

cPG

CA SL-RA SH

h(RAS-R)

RA SL-CA SL

RASL-CA SH

CASH-RASL

w(CA SL)

h(CASH)

w(CASL)

CA SH-RA SL

h(W-CA S)

RAS-W

CA S-W

su(R-CAS)

CAS-W

h(W-CA S)

h(W-RAS)

(CA-W)RW

h(CAS-CA )

su(CA-CAS)

h(CAS-CA )

su(CA -CA S)

h(RAS-RA)

su(RA -RA S)

RAS-CA

a(CAS)

a(CA)

a(RA S)

AAA

A.-D.

E.-D.

A.-D.

E.-D.

a(CA)

a(CA S)

a(CASH)

su(D-W)

h(W-D)

CA SL-QX

a(G)

v(G)

CASL-QX

a(G)

v(G)

RAS

CAS

A0 - A7

DQ0 -
DQ3

h(W-D)

su(D-W)

High-Z

RAS only Refresh

December 12, 1997

UD61464

AAAA

AAA

AAAA

HIDDEN-Refresh with address transfer

AAAA

RAS

CAS

A0-A7

DQ0 -
DQ3

w(RASL)

w(RA SL)

w(RA SH)

CASH-RA SL

RASL-CASL

CA SL-RASH

su(CA-CAS)

su(RA-RAS)

h(RA S-RA)

h(CA S-CA)

su(RA-RAS)

h(RAS-RA)

RAS-CA

a(CA )

a(CA S)

CASL-QX

a(RA S)

RA SL-CA SH

CA SH-RASL

h(RAS-R)

su(R-CA S)

a(G)

GL-RA SH

v(G)

v(CAS)

CA-RASH

LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.

The information describes the type of component and shall not be considered as
assured characteristics.

Terms of delivery and rights to change design reserved.

Memory Products 1998

64K x 4 DRAM UD61464

Zentrum Mikroelektronik Dresden GmbH

Grenzstra遝 28

� D-01109 Dresden

�

B. 80

�

D-01101 Dresden

�

Germany

Phone: +49 351 88 22-3 06 � Fax: +49 351 88 22-3 37 � Email: sales@zmd.de

Internet Web Site: http://www.zmd.de

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: UD61464DC08

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: UD61464DC08