December 12, 1997
1
Maintenance only
UD61466
64K x 4 DRAM
Features
F
Dynamic random access memory
65536 x 4 bits manufactured
using a CMOS technology
F
RAS access times 70 ns/80 ns
F
TTL-compatible
F
Three-state outputs bidirectional
F
256 refresh cycles
4 ms refresh cycle time
F
STATIC COLUMN MODE
F
Operating modes: Read, Write,
Read - Write,
RAS only Refresh,
Hidden Refresh with address
transfer
F
Low power dissipation
F
Power supply voltage 5 V
F
Package PDIP18 (300 mil)
F
Operating temperature range
0 to 70 C
F
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90112
Description
Addressing
The UD61466 is a dynamic random
access memory organized 65536
words by 4 bits.
SCM facilitates faster data operation
with predefined row address. Via 8
address inputs the 16 address bits
are transmitted into the internal
address memories in a time-multi-
plex operation. The falling RAS-
edge takes over the row address.
After the row address hold time the
column address can be applied.
During the Read cycle the address
transfer is not latched by the falling
edge at the CAS input, so that the
column address must be applied
until the data are valid at the output.
During Write the column address is
taken over with the falling edge of
the control signal CAS, or W, that
becomes active as the last. The sel-
ection of one or more memory cir-
cuits can be made via the RAS
input.
Read-Write-Control
The choice between Read or Write
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
meanwhile LOW leads to a Write
cycle.
Both CAS-controlled and W-control-
led Write cycles are possible with
activated RAS signal.
Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic ,,0" or ,,1".
The memory cycle being a Read,
Read-Write or a Write cycle (W-con-
trolled), Q changes from High-Z
state to the active state (,,0" or ,,1").
After access time, the contents of
the selected cell will be available,
with the exception of the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
Pin Description
Signal Name Signal Description
A0 - A7 Address Inputs
DQ0 - DQ3 Data In/Out
W
Read, Write Control
RAS
Row Address Strobe
G
Output Enable
VCC Power Supply Voltage
VSS Ground
CAS
Column Address Strobe
Pin Configuration
Top View
1
G
VSS
18
2
DQ0
DQ3
17
4
W
DQ2
15
5
RAS
A6
14
3
DQ1
CAS
16
6
A0
A3
13
7
A2
A4
12
8
A1
A5
11
9
VCC
A7
10
(OE)
(WE)
PDIP
SOJ
December 12, 1997
3
UD61466
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and operating temperature range indicated below.
All pins not under test (alternating voltage) must be connected with ground.
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.5
7.0
V
Input Voltage
1)
V
I
-1.0
7.0
V
Output Voltage
1)
V
O
-1.0
7.0
V
Output Current
1a)
I
O
-50
50
mA
Power Dissipation
P
D
1
W
Operating Temperature
T
a
0
70
C
Storage Temperature
T
stg
-55
125
C
Remarks: see page 7
Recommended Operating Conditions
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Input Low Voltage
1)
V
IL
-1.0
0.8
V
Input High Voltage
V
IH
2.4
5.5
V
Remark: see page 7
Capacitances
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
A0 to A7
V
CC
= 5.0 V
V
I
=
V
SS
f
= 1 MHz
T
a
= 25
C
C
I1
6
pF
Input Capacitance
RAS, CAS, W and G
C
I2
7
pF
Output Capacitance DQ0 to DQ3
C
O
7
pF
December 12, 1997
4
UD61466
Static Characteristics
Conditions
Symbol
Min.
Max.
Unit
DC07
DC08
DC07
DC08
Power Supply Current
(average value of RAS-CAS cycles)
2)
t
cW
= t
cWmin
t
cR
= t
cRmin
I
CC1
70
60
mA
Refresh Current
(average value of RAS cycles)
2)
CAS = V
IH
t
cW
= t
cWmin
t
cR
= t
cRmin
I
CC2
70
60
mA
SCM Current
(average value of SCM cycles)
2)
RAS = V
IL
t
c(A)
= t
c(A)min
I
CC3
50
40
mA
Stand-by Current TTL Level
RAS = CAS
= V
IH
I
CC4
2
2
mA
Stand-by Current CMOS Level
RAS = V
CC
-
0.2 V
CAS = V
CC
-
0.2 V
I
CC5
1
1
mA
Output High Voltage
I
OH
= -5 mA
V
OH
2.4
2.4
V
Output Low Voltage
I
OL
= 4.2 mA
V
OL
0.4
0.4
V
Input Leakage Current
at any input,
all other pins = 0 V
V
I
= 0 V to
5.5 V
I
I
-10
-10
10
10
A
Output Leakage Current
Q = High-Z
V
O
= 0 V to
5.5 V
RAS = CAS
= V
IH
I
O
-10
-10
10
10
A
Remarks: see page 7
December 12, 1997
5
UD61466
Dynamic Characteristics
3)
Symbol
Min.
Max.
Unit
Alt.
IEC
DC07
DC08
DC07
DC08
F
ALL CYCLES
Transition Time (Rise and Fall)
4)
t
T
t
t
3
3
50
50
ns
RAS Precharge Time
CAS Precharge Time
t
RP
t
CP
t
w(RASH)
t
w(CASH)
50
10
60
10
ns
ns
Row Address Set-up Time
t
ASR
t
su(RA-RAS)
0
0
ns
Row Address Hold Time
t
RAH
t
h(RAS-RA)
10
10
ns
Output Buffer Turn-off Delay Time
Output Buffer Turn-off Delay Time from OE
5)
5)
t
OFF
t
OEZ
t
v(CAS)
t
v(G)
0
0
0
0
20
20
20
20
ns
ns
CAS to RAS Precharge Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period
6)
t
CRP
t
RAD
t
RAL
t
CLZ
t
REF
t
CASH-RASL
t
RAS-CA
t
CA-RASH
t
CASL-QX
t
rf
5
15
35
0
5
15
40
0
35
4
40
4
ns
ns
ns
ns
ms
F
READ
Random Read Cycle Time
7)
t
RC
t
cR
130
150
ns
Access Time from RAS
Access Time from Column Address
Access Time from CAS
OE Access Time
8)
8)
8)
8)
t
RAC
t
AA
t
CAC
t
OEA
t
a(RAS)
t
a(CA)
t
a(CAS)
t
a(G)
70
35
20
20
80
40
20
20
ns
ns
ns
ns
RAS Pulse Width
CAS Pulse Width
t
RAS
t
CAS
t
w(RASL)
t
w(CASL)
70
20
80
20
10000
10000
10000
10000
ns
ns
Read Command Set-up Time
t
RCS
t
su(R-CAS)
0
0
ns
Read Command Hold Time ref. to RAS
Read Command Hold Time
Column Address Hold Time ref. to RAS
Column Address Hold Time ref. to RAS Rise
9)
9)
10)
t
RRH
t
RCH
t
AR
t
AH
t
h(RAS-R)
t
h(CAS-R)
t
h(RAS-CA)
t
h(RASH-CA)
0
0
70
5
0
0
80
5
ns
ns
ns
ns
RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
RAS Hold Time referenced to OE
6)
t
RCD
t
CSH
t
RSH
t
ROH
t
RASL-CASL
t
RASL-CASH
t
CASL-RASH
t
GL-RASH
20
70
20
10
20
80
20
10
50
60
ns
ns
ns
ns
Remarks: see page 7
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