December 12, 1997

UL6264A

Packages: PDIP28(600 mil)

SOP28 (330 mil)

Description

The UL6264A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L) or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G the data
inputs, or outputs, are active. In the
active state E1 = L and E2 = H,
each address change leads to a
new Read or Write cycle. In a Read
cycle, the data outputs are activa-
ted by the falling edge of G, after-
wards the data word read will be
available at the outputs
DQ0 - DQ7. After the address

change, the data outputs go High-Z
until the new read information is
available. The data outputs have no
preferred state. If the memory is
driven by CMOS levels in the active
state, and if there is no change of
the address, data input and control
signals W or G, the operating cur-
rent (at I

= 0 mA) drops to the

value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E2, all inputs
consist of NOR gates, so that no
pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
If the circuit is inactivated by E2 = L,
the standby current (TTL) drops to
100

A typ.

Features

8192 x 8 bit static CMOS RAM

250 and 500 ns Access Times

Common data inputs and data
outputs

Three-state outputs

Typ. operating supply current:

250 ns: 12 mA

500 ns: 7 mA

Standby current < 5

Standby current at 25

and 3.3 V: typ. 50 nA

TTL/CMOS-compatible

Automatic reduction of power
dissipation in long Read or Write
cycles

Power supply voltage 3.3 V

Operating temperature ranges

0 to 70

-25 to 85

-40 to 85

Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111

ESD protection > 2000 V
(MIL STD 883C M3015.7)

Latch-up immunity > 100 mA

Low Voltage 8K x 8 SRAM

Pin Description

Signal Name Signal Description

A0 - A12 Address Inputs

DQ0 - DQ7 Data In/Out

Chip Enable 1

E2 Chip Enable 2

Output Enable

Write Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Configuration

n.c.

VCC

A12

W (WE)

E2 (CE2)

A11

G (OE)

A10

DQ1

DQ5

E (CE1)

DQ7

DQ0

DQ6

DQ2

DQ4

VSS

DQ3

PDIP

Top View

SOP

December 12, 1997

UL6264A

Address

Change

Detector

* H or L

Operating Mode E1

E2 W

DQ0 - DQ7

Standby/not

selected

High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z

Write L H L * Data Inputs High-Z

Truth Table

A10

Memory Cell

Array

256 Rows x

256 Columns

oder

ddr

I
nput

l
u

oder

on D

t
a

-
I
/
O

Sense Amplifier/

Write Control Logic

Clock

Generator

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage V

-0.3 7 V

Input Voltage V

-0.3 V

+ 0.5 V

Output Voltage V

-0.3 V

+ 0.5 V

Power Dissipation P

Operating
Temperature

C-Type
G-Type
K-Type

-25
-40

70
85
85

Storage Temperature T

stg

-55 125

Characteristics

l
u

Addr

I
nput

Block Diagram

A4
A5
A6
A7
A8
A9
A11
A12

All voltages are referenced to V

= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of

5 ns, measured between 10 % and 90 % of V

, as well as

input levels of V

= 0 V and V

= 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the t

dis

-times, in which cases transition is measured

200 mV from steady-state voltage.

December 12, 1997

UL6264A

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - Standby Mode
(CMOS level)

Supply Current - Standby Mode
(TTL level)

CC(OP)

CC(SB)

CC(SB)1

= V

= 3.6 V
= 0.8 V
= 2.0 V
= 500 ns
= 250 ns

= 3.6 V
= V

0.2

= 3.6 V
= 2.0 V

20
30

(typ. 0.7)

mA
mA

Output High Voltage

Output Low Voltage

= 3.0 V
= -1.0 mA
= 3.0 V
= 2.0 mA

2.4

0.4

Input High Leakage Current

Input Low Leakage Current

= 3.6 V
= 3.6 V
= 3.6 V
=

0 V

-1

Output High Current

Output Low Current

= 3.0 V
= 2.4 V
= 3.0 V
= 0.4 V

2.0

-1 mA

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

OHZ

OLZ

= 3.6 V
= 3.6 V
= 3.6 V
=

0 V

-1

Recommended Operating
Conditions

Symbol Conditions Min. Max. Unit

Power Supply Voltage V

3.0 3.6 V

Data Retention Voltage V

CC(DR)

2.0 V

Input Low Voltage* V

-0.3 0.8 V

Input High Voltage V

2.0 V

+ 0.3 V

* -2 V at Pulse Width 10 ns

December 12, 1997

UL6264A

Switching Characteristics

Symbol Min. Max. Unit

Alt.

IEC

Time to Output in Low-Z t

t(QX)

20 20 ns

G LOW to Output in Low-Z t

OLZ

tG(QX)

10 10 ns

Cycle Time

Write Cycle Time
Read Cycle Time

250
250

500
500

ns
ns

Access Time

E1 LO W or E2 HIGH to Data Valid
G LO W to Data Valid
Address to Data Valid

ACE

a(E)

a(G)

a(A)

-
-
-

250
100
250

500
100
500

ns
ns
ns

Pulse Widths

Write Pulse Width
Chip Enable to End of Write

w(W)

w(E)

120
180

150
210

ns
ns

Setup Times

Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time

su(A)

su(E)

su(W)

su(D)

180
120

210
150
100

ns
ns
ns
ns

Data Hold Time
Address Hold Time from End of Write

h(D)

h(A)

0
0

ns
ns

Output Hold Time from Address
Change

v(A)

20 20 ns

E1 HIGH or E2 LOW to Output in

High-Z

W LOW to Output in High-Z

G HIGH to Output in High-Z

HZCE

HZWE

HZOE

dis(E)

dis(W)

dis(G)

0
0

60
40

ns
ns

CC(DR)

2 V

Data Retention Mode E1-Controlled

Data Retention Mode E2-Controlled

Data Retention

3.0 V

rec

CC(DR)

2 V

E2(DR)

CC(DR)

- 0.2 V or V

E2(DR)

0.2 V

CC(DR)

- 0.2 V

E1(DR)

CC(DR)

+ 0.3 V

0 V

Data Retention

rec

0.8 V

0.8 V V

E2(DR)

0.2 V

2.0 V

3.0 V

0 V

Chip Deselect to Data Retention Time t

min 0 ns

Operating Recovery Time t

rec

min t

December 12, 1997

UL6264A

Test Configuration for Functional Check

3.3 V

960

510

5 pF

l
t
aneou

eas

t
of

l
8 out

put

i
ns

I
n

t
l
e

l
ac

r
d

i
ng

t
o

r
e

l
e

t

t
e

t
m

ent

L1: For dynamic measurement except t

dis

-times L2: For t

dis

-times

IC Code Numbers

Example

The date of manufacture is given by the 4 last digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.

UL6264A

Type

Package
D = PDIP
S = SOP

Access Time
25 = 250 ns
50 = 500 ns

Operating Temperature Range
C = 0 to 70 °C
G = -25 to 85 °C
K = -40 to 85 °C

All pins not under test must be connected with ground by capacitors.

100 pF

Q Q Q

L1 L2

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance

= 3.3 V

= V

Output Capacitance

f = 1 MHz
T

= 25

10 pF

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

E1
E2
W
G

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

December 12, 1997

UL6264A

h(D)

Read Cycle 1 (during Read Cycle: E1 = G = V

, E2 = W = V

)

Read Cycle 2 (during Read Cycle: W = V

)

Write Cycle 1 (W-controlled)

a(A)

Previous
Data Valid

Output Data
Valid

Addresses Valid

v(A )

AAAA

AAA

Output

dis(E)

su(A )

a(E)

su(A)

t(QX)

tG(QX)

a(G)

a(E)

dis(E)

dis(G)

Addresses Valid

Output Data
Valid

AAAA

AAA

Input

Output

su(E)

h(A )

w(W)

su(A )

su(E)

su(D)

dis(W)

t(QX)

Addresses Valid

Input Data
Valid

High-Z

AAAA

AAA

AAAA

AAA

December 12, 1997

UL6264A

High-Z

Input Data
Valid

h(D)

su(W)

w(E)

su(D)

Addresses Valid

su(A )

su(E)

h(A )

t(QX)

dis(W)

AAAA

AAA

AAAA

Input

Output

su(A)

AAAA

undefined L- or H-Level

Write Cycle 2 (E1-controlled)

Write Cycle 3 (E2-controlled)

h(D)

Input

Output

w(E)

h(A )

su(W)

su(E)

su(D)

dis(W)

t(QX )

Addresses Valid

Input Data
Valid

High-Z

AAAA

AAA

AAAA

LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.

The information describes the type of component and shall not be considered as
assured characteristics.

Terms of delivery and rights to change design reserved.

Memory Products 1998

Low Voltage 8K x 8 SRAM UL6264A

Zentrum Mikroelektronik Dresden GmbH

Grenzstraße 28

· D-01109 Dresden

B. 80

D-01101 Dresden

Germany

Phone: +49 351 88 22-3 06 · Fax: +49 351 88 22-3 37 · Email: sales@zmd.de

Internet Web Site: http://www.zmd.de

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