1
Features
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n
A/D conversion with 6-bit
resolution
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Time base programmable
from 50ns to 3.27 ms (at
a clock frequency of 20
MHz)
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Trigger Modes: Auto, In-
ternal +/-, External +/-
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n
5 discrete trigger levels
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Internal SRAM for 128
values
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SRAM bypass mode
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Shift of base line by ad-
justable offset
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Supply voltage 5 Volts
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Bidirectional C interface
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Power-down for analog
part
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PLCC44 package
Application
The Graphic Signal Monitor IC
was developed for visualization
of the time behavior of electri-
cal signals. Interaction with an
external C makes it possible
to achieve the functionality of a
one-channel digital storage
oscilloscope with additional
digital voltmeter function.
The small dimensions as well
as a minimum of external wi-
ring facilitate both the applica-
tion in miniaturized measuring
devices for service and test
area, and placement near the
front panels in control panels
and switch cabinets.
Description
After the parameters of time
basis, trigger level and trigger
mode have been loaded into
the control register, the recor-
ding starts as soon as the trig-
ger condition occurs. This
procedure ends when 128
times 6 bit data have been
written from the flash A/D con-
verter into the internal SRAM.
Afterwards, an externally con-
nected microcontroller can
read the data and formate it for
an LC display or for transmis-
sion via an interface.
Block Diagram
A_IN
uC Interface
Z_IN
REFT
REFB
PARITY
DIO_0..7
OUT_10
OUT_100
SEL_AC
SEL_DC
EN_REC
LD-DISPL
EXT_PWR
BP_RAM
WR_TEST
CPUCLK
DISP_CLK
DISP_DATA
T_IN
TRIG_IN
TRIG_OUT
SHIFT REG
TRIGGER
REF
TIME BASE
MUX
STATUS
SRAM
A
D
ADC
CONTROL
+
-
2
Functional Description
The input amplifier serves for
impedance matching and
amplifies the input signal.
In order to allow also bipolar
input signals to be processed
even if there is only one supply
voltage, a level shift takes
place in the input amplifier.
Using an external potentiome-
ter, such shift can be varied
into a base line shift.
The measuring range can be
extended by connection of an
external voltage divider. An AC
input can be implemented by
means of an additional external
capacitor. Two special inputs
of the integrated circuit can be
connected with the external
voltage divider; they supply a
low current during the measu-
rement pauses. The resulting
voltage at the pins indicates
the selected measurement
range. Two more pins have
been provided for detection of
the selected signal coupling
type. The external AC/DC
switch is to tie the pins to gro-
und. The status information
about measurement range and
coupling type, multiplexed with
the measured data, is provided
for interpretation at the bidi-
rectional interface.
The measured signal is digiti-
zed in an analog-to-digital
converter operating according
to the flash principle. When the
measurement is activated, it
converts the input signal into a
6-bit digital word at a fixed
conversion rate of 20 MHz.
The 63 comparators of the
flash ADC consist of a differen-
tial stage with subsequent
latch.
For storaging the measured
data, the integrated circuit
contains an SRAM which is 6
bits wide and 128 values deep.
The SRAM Write signal is ge-
nerated by the Time Base unit
by means of a programmable
shift register.
The time base is freely se-
lectable within the range from
2
0
to 2
16
times the clock peri-
od.
Connection with a 20-MHz
quartz will result in a range
from 50ns to 3,27ms.
The RAM bypass mode creates
more possibilities of applicati-
on; the values are output di-
rectly to the bidirectional inter-
face, not into the RAM.
The measurement can be initia-
ted by an external signal or,
controlled by the trigger logic,
depending on the level of the
input signal, in an automatic or
edge- and level triggered mo-
de.
For this purpose, there is a
comparator, the reference level
of which can be selected in five
discrete stages. The compara-
tor has been provided with a
hysteresis for noise suppressi-
on.
The Control unit coordinates
the circuit functions, such as
the data exchange via the inter-
face. Measured data and status
information are output in paral-
lel. The loading of the time
base, trigger level, trigger mo-
de parameters into registers,
which is uncritical with regard
to time, is done serially via 2
pins of the bidirectional inter-
face.
The analog part of the circuit is
activated only during the short
data recording time, which
significantly reduces the total
power consumption.
For special applications, e. g.
for control of an LCD module, a
shift register has been imple-
mented. Loading of information
into the shift register is parallel,
while the output is serial via
two pins.
Pin Configuration
8
9
10
7
11 12 13 14 15 16 17
6
5
4
3
2
1
44
43
42
41
40
38 37 36
39
35 34 33 32 31 30 29
19
20
21
22
23
24
25
26
27
28
18
3
Pin Description
Pin
Name
IN/OU
T
Description
Pin
Name
IN/OUT Description
Power Supply Connections
Digital Outputs
29
VDD
Pos. supply voltage, digital
8
PD
O (ub)
Analog power-down
38
VDDA
Pos. supply voltage, analog
31
CPUCLK
O
5 MHz clock (for proces-
sor)
17
VSS
Neg. supply voltage, digital
30
WR_TEST
O
RAM Write mode active
3
VSSA
Neg. supply voltage, analog
36
TRIG_OUT
O
Trigger output
44
AGND
Signal ground
32
DISP_CLK
O
1.25 MHz clock
(Display data clock)
Analog Inputs
33
DISP_DATA O
Display data serial
43
A_IN
I
Analog signal input
Data I/Os
42
T_IN
I
Trigger signal input
20
PARITY
bid
Bid. data pin (parity)
41
Z_IN
I
Zero-level input
28...21
DIO_0...7
bid
Bidirectional data inter-
face
Digital Inputs
Analog Outputs
1
OUT_10
I (puc)
Status 1 (10V area switch)
6
REFT
O
Reference voltage (top)
2
OUT_100
I (puc)
Status 2 (100V area switch)
5
REFB
O
Reference voltage
(bottom)
10
SEL_AC
I (pu)
Status 3 (AC operation)
4
VED
O
Internal base potential
9
SEL_DC
I (pu)
Status 4 (DC operation)
External Components
34
N_MODE
I (pu)
Control 1 (operating mode)
12
XOUT
Crystal output
35
TRIG_IN
I
Trigger input
13
XIN
Qrystal input
19
EN_REC
I
Enable Record
40
CF
Follower stage,
Connection to trim-C
18
LD_DISPL
I
Load Display
39
CZ
Amplifier ,
Connection to trim-C
16
EXT_PWR
I
Control 2 (external power)
7
CW
A/D converter
power bypass capacitor
15
BP_RAM
I
Bypass Ram Mode
Test Pins
11
TRESULT
O
Test mode output
14
TEST
I (pd)
Test mode input
pu = Internal Pull-Up
puc = Internal Pull-Up Controlled
pd= Internal Pull-Down
ub = Unbuffered output
Characteristics (Selection)
Maximum Ratings
Symbol
Min
Typ
Max
Unit
General
Supply voltage (VDDA=VDD)
V
DD
4.75
5.0
5.25
V
Oscillator frequency
f
q
20
MHz
Operating temperature
T
0
70
o
C
Current drain
I
S
60
100
mA
Digital
Input H-level
V
IH
V
DD
-0.8
V
Input L-level
V
IL
0.8
V
Output H-level (2mA, pin32: 8mA))
V
OH
2.4
V
Output L-level (-2mA, pin32 -8mA)
V
OL
0.4
V
Analog Part
Input voltage
V
is
,V
it
-0.5
+0.5
V
Input resistance
R
is
,R
id
100
M
Input capacitance
C
is
,C
it
5
pF
A/D Converter
Resolution
radc
6
Bit
Differential non-linearity
DNL
0.8
LSB
Integral non-linearity
INL
1
LSB
4
Notes for Application
Before starting the measure-
ment, the parameters of time
base, trigger level and trigger
mode are to be serially loaded
to DIO(0) (clock) and DIO(1)
(data) by the microcontroller.
The recording of measured
values is prepared by activati-
on of EN_REC.
Then, the IC outputs the status
of the 4 pins for measurement
range and AC/DC coupling to
DIO(2 to 5) (parallel), until a
High pulse is applied to the
LD_DISPL pin.
The integrated circuit is now
ready to record measured va-
lues, which happens as soon
as the trigger condition occurs.
Subsequently, the microcon-
troller, by clocking of
LD_DISPL, reads out the con-
tents of the SRAM in bit-parallel
and byte-serial form at DIO(0 to
5).
The measured data and status
information taken over are
prepared in the external micro-
controller in a way that allows
to indicate them on an external
LC display or to transfer them
to a computer, for instance,
formatted according to the
RS232-Protocol.
For digital voltmeter functions,
the microprocessor can calcu-
late the average value of all
128 recorded measured valu-
es, and, by multiplying them by
0.7, it can determine the
approximate effective value.
This value can be shown on
the display as well.
A shift register is available in
the integrated circuit for special
applications. In the application
shown below, it controls an
LCD module of 16 x 32 pixels.
The microcontroller loads the
data available in parallel at DIO
(0 to 7) as well as the parity
information into the register.
The process of loading is con-
trolled by means of the signals
EN_REC and LD_DISPL. A
start and stop bit are added,
then the output takes place at
DISP_CLK (data) and
DISP_DATA (data).
When using the ZM407, it is
absolutely necessary to ensure
synchronous operation of the
system. Therefore, a 5-MHz
system clock for an external
microcontroller is provided at
the CPUCLK pin.
Multi-channel recording is
possible by cascading of se-
veral SCOPE ICs. In this case,
one TRIG_OUT output will
control several TRIG_IN inputs.
Application Circuit
SCOPE IC
DIO1..7
PARITY
EN_REC
LD_DISPL
CPUCLK
REFT
Z_IN
REFB
A_IN
OUT_10
OUT_100
SEL_AC
SEL_DC
T_IN
DISP_DATA
DISP_CLK
TRIG_OUT
TRIG_IN
AC/DC
10V/100V
TRG
IN
Y-POSITION
uController
LC Display
RS232 TX
RX
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