ZR36015

June 1993

ZORAN Corporation

1705 Wyatt Drive

Santa Clara, CA 95054

(408) 986-1314

FAX (408) 986-1240

RASTER TO BLOCK CONVERTER

PRELIMINARY

Real Time Raster to/from Block Conversion

1/2 Decimation Processing in the Horizontal Direction

30 MHz Maximum Clock Rate

Only Image in Preset Window is Converted

Compatable with Zorans ZR36050 JPEG Coder and
ZR36011 Color Space Converter

FEATURES

Supports 1:0:0,4:2:2,and 4:1:1 data formats

100-pin plastic quad flat package (PQFP)

TTL level Input/Output

Synchronous data and controls

Low power consumption: 0.45W (Typ.)

CMOS circuit operating with a single 5V power supply

Image processing

Multi-media

APPLICATIONS

DESCRIPTION

The ZR36015 performes raster to/from block conversion for
image compression and expansion applications, and it can be
connected directly to the ZR36050 JPEG coder and the
ZR36011 Color Space Converter.

An image compression system can be easily constructed using
the ZR36015 with the ZR35060 and ZR36011.

The ZR36015 uses a double buffered external SRAM Strip
Buffer to support raster to/from block conversion and block inter-
leave.

The maximum number of pixels that can be processed per line
is 8K. The maximum number of lines that can be prcessed per

image is 16K. These numbers vary according to the mode of
operation.

The ZR36015 supports 4:0:0, 4:1:1, and 4:2:2 data formats, and
one half decimation in horizontal direction during compression.

The maximum data transfer rate to the ZR36050 coder is 30
MHz.

[The ZR36015 is fabricated with an advanced low-power CMOS
technology, making it suitable for use in low-power, cost sensi-
tive applications. The device is availiable in a 100 pin , Plastic
Quad Flat Package (PQFP).]

Scanners

Image Storage

Image Capture

Figure 1. ZR36015 Block Diagram

Figure 2. ZR36015 Logical Pinout

MOE

PXDATA(15:0)

CBUSY

ADD(1:0)

Memory
Interface

Pixel

Interface

SPH

MWE

BDATA(7:0)

MADD(15:0)

MDATA(15:0)

HEN

VEN

WINDOW

CLKCSC

BSY

Host

Interface

SYSCLK

RESET

System

Clock

System

Reset

COE

EOS

STOP

DSYNC

Coder
Interface

Internal Register Control

ADD(1:0)

Raster/Block

Address

Generator

MWE

MOE

MADD(15:0)

CBSY

I/F

PXDATA(15:0)

1/2

Decimation

Selector

Sub

Buffer

MDATA(15:0)

I/F

BDATA(7:0)

Interface Logic

COE

EOS

STOP

DSYNC

RESET

SPH

Window
Control

HEN

VEN

WINDOW

BSY

CLKCSC

Host Interface

Memory
Interface

Coder Interface

Pixel

Interface

I/F

SYSCLK

This document was created with FrameMaker 4.0.4

ZR36015

PRELIMINARY

SIGNAL DESCRIPTION

1. I = Input, O = Output, B = Bidirectional, Z = High Impedance.

Name

Type

Function

PXDATA(15:0)

Pixel side data bus. Input for compression and output for expansion. High impedance during RESET or IDLE modes.
When SPH is active (High), PXDATA(7:0) is controlled by the Host Interface. It will be high impedance except during
a Host read access, in which case it will be driven. The state of PXDATA(15:8) follows that of PXDATA(7:0) in this
case but is unused.

HEN

Active High Horizontal enable signal (HDelay starts counting from the rise of HEN)

VEN

Active High Verticle enable signal (VDelay starts counting from the rise of VEN)

SYSCLK

System clock (active on rising edge).

MADD(15:0)

Address output for the strip memory. Up to 64K x 16 bits of SRAM is addressable.

MDATA(15:0)

Data bus for the strip memory. Memory A is assigned to MDATA(7:0), and Memory B is assigned to MDATA(15:8).

MWE

Active Low: Write enable for the Strip Memory.

MOE

Active Low: Output enable for the Strip Memory.

DSYNC

Active Low: Sync. signal for 64 byte block of data. Output during compression and input during expansion. In
compression, DSYNC marks the start of an 8x8 image data block and should appear as an output one SYSCLK cycle
before the first image data of a block. During expansion DSYNC is input on SYSCLK before the first image data of
a sample block. The width of DSYNC is one SYSCLK. (Connect directly to ZR36050 DSYNC signal).

STOP

Active Low: Stop sending/receiving. During compression, this signal is an input which indicates that the CODEC is
busy, and the ZR36015 should stop sending data. During expansion, this signal is an output indicating the ZR36015
is not ready to receive data, and for the CODEC to stop sending data. (Connect directly to ZR36050 STOP signal).

EOS

Active Low: Signal indicates the end of each scan. Output during compression and input during expasion. In
compression, EOS is output together with the last image data sample of the last block of each scan. In expansion,
EOS is input together with the last image data sample of the last block of each scan. (Connect directly to ZR36050
EOS signal).

BDATA(7:0)

B/Z

Data bus interface with the Coder. Output for compression and input for expansion. High impedance during reset.
Otherwise, the direction of the bus is determined by the COE input. (Connect directly to ZR36050 PIXEL(11:4) bus.)

ADD(1:0)

Address select for Host access to internal registers. Enabled when SPH is high.

Active Low: Write strobe for Host loading of internal registers and tables. Data is writtern on the rising edge of WR.
WR is enabled when SPH is high.

Active Low: Read strobe for Host reading of internal registers and tables. RD is enabled when SPH is high.

CBSY

Active Low: CBSY indicates that the ZR36015 is not ready for the next strip of data.

COE

Coder bus output enable signal. HIGH for Compression Mode (enabling the output drivers for the CDATA bus, EOS
signal and DSYNC signal. . LOW for Expansion mode (enabling the output drivers for the STOP signal). (Connect
directly to ZR36050 COMP signal).

BSY

Active Low: BSY is active when the ZR36015 is processing an image. Before setting hte GO bit in the Mode Register,
BSY should be inactive.

CLKCSC

Clock output for ZR36011 Color Space Converter. Used to synchronize data transfers.

SPH

Active High: Select host access to the ZR36015 via the PXDATA(7:0) data bus. Enables the WR, RD inputs.

WINDOW

Active HIGH; Indicates active (windowed) image area.

RESET

Asynchronous Active LOW reset. All bi-directional signals are tri-stated when this signal is active. After RESET , the
ZR36015 will be in idle mode (GO bit cleared) and the PXDATA bus will continue to behigh impedance until the GO
bit is set .

Power terminal.

Ground terminal.

ZR36015

PRELIMINARY

FUNCTIONAL DESCRIPTION

The ZR36015 performs conversion between raster and block
formatted data, with applications in image compression and
expansion. It is designed to work with the ZR36050 JPEG
Codec.

Figure 1 is a block diagram of the ZR36015.

The ZR36015 is a programmable device with an asynchronous
Host Interface (WR,RD,ADD(1:0) which is enabled by the SPH
input . Data is transferred between the Host and the ZR36015
internal Control Registers and configuration tables via the
PXDATA(7:0) bus. Because PXDATA(7:0) is used to transfer
data to/from the Host, and also for pixel data, an external buffer
is required to prevent bus contention.

The internal control registers of the ZR36015 consist of four reg-
isters which set the operating mode of the device and control the
interface between the host and the configuration tables. The
configuration tables are used to specify an active window within
the region defined by the VEN and HEN inputs, and to count the
actual number of lins that were processed.

The ZR36015 interfaces to a pixel data bus PXDATA(15:0),
which transfers 4:0:0, 4:1:1, or 4:2:2 formatted data. Transfer of
data on the Pixel Bus is controlled by the Verticle Enable (VEN)
and Horizontal Enable (HEN) inputs.

During Compression, Pixel data can be optionally decimated by
2 in the horizontal direction.

When the ZR36015 is interfaced to the ZR36011 "Color Space
Converter", then it is recommended that the Clock for Color
Space Converter (CLKCSC) output be connected to the input
clock for the ZR36011.

The ZR36015 supports a double buffered Strip Buffer SRAM
architecture, with up to 64K 16 bit words. The Strip Buffer stores
the image data in interleaved block format. Interleaved block for-
matted data is transferred between the ZR36015 and the
ZR36050 over the BDATA bus.

The ZR36015 can be directly interfaced with the ZR36050 JPEG
Codec. Block transfers of data are controlled by the DSYNC,
STOP, EOS, COE signals, with data being transferred on the
BDATA(7:0) bus. These signals are connected directly to the
ZR36050 DSYNC, STOP, EOS, COMP, and PIXEL(11:4)
signals respectively.

Overflows or underflows of the double buffered Strip Memroy
are indicated by the CBSY output.

System Configuration Example

An example of the ZR36015 system configuration is given in
Figure 3. This figure shows an image compression/expansion
system which uses the ZR36011 (Color Space Converter) and
the ZR36050 (JPEG Codec), in addition to the ZR36015.

The figure shows A/D and D/A conversion devices in between
an image source/display and the ZR36011 (Color Space Con-
verter).

The bus between the ZR36011 and the D/A and A/D converter-
ters is in 24 bit RGB format.

In Compression mode the ZR36011 converts the RGB data into
YUV (luminance/chrominance) data for more efficient compres-
sion.

In Compression mode, the ZR36015 (Raster to Block Convert-
er), converts the raster data into 8x8 blocks for processing by the
ZR36050 JPEG Codec. The SRAM strip buffer stores 8 lines of
data for conversion into block format.

In Compression mode, the ZR36050 JPEG Codec performes
JPEG compression on the block data, and transfers the com-
pressed image over the system bus.

In expansion mode, the process described above is reversed.

The ZR36015 and ZR36050 devices are programmed via the
system bus, and require minimal host intervention during the
compression/expansion processes.

Control Registers

The ZR36015 has four Control Registers which allow the Host to
set the mode of operation, and to initiate, terminate, and monitor

Image Source/Display

A/D Converter

D/A Converter

Digital RGB

ZR36011

Color Space Converter

Digital YUV

ZR36015

Raster to Block Converter

SRAM Strip Buffer for

Raster

Block Conversion

YCbCr

ZR36050

JPEG Image Processor

System Bus

Figure 3. ZR36015 System Configuration Example

ZR36015

PRELIMINARY

the status of compression or expansion prcesses. The four
control registers are listed and described below.

Soft Reset Register (Write Only):

A Write to the Soft Reset Register will abort the current process,
and put the ZR36015 in to the IDLE mode. The Soft Reset does
not modify the internal registers of the ZR36015, except for the
GO bit in the Mode Register (which is cleared).

After a soft reset, the ZR36015 will be in the IDLE state.

To start a new process, the GO bit in the Mode Register must be
set by the Host.

Mode Register (Read/Write):

The table below shows the contents of the Mode Register.

The definition of these bits is given below:

BSY: Busy Flag (Read Only)

Active High: Indicates that the ZR36015 is busy performing
an encoding or decoding process. The next process should
not be started until the current process completes (indicated
by the ZR36015 clearing this bit).

The BSY flag is set to `1' immediately after the GO bit is set.
The BSY flag is cleared when the processing for an image is
complete and the ZR36015 is ready for the next "GO".

Before setting the "GO" bit (defined later in this section), the
host should check that the Busy Flag is `0`, indicating that the
previous process has completed.

CSC: Select ZR36011 Color Space Converter (Write Only)

Table 1: Control Register Map

ADD(1:0)

Contents

Host Access

Soft Reset

Mode Register

R/W

Address Pointer Register

R/W

Configuration Register Tables

R/W

Bit

Name

Description

Go:
0: ZR36015 IDLE
1: Set to indicate Encode or Decode process.

EDC

0: Decode mode selected
1: Encode mode selected

3:2

MOD(1:0)

Pixel data Mode Select
(seeTable 2)

DCM

Decimate data (Compression mode only).
Active High.

CSC

Select ZR36011 Color Space Converter Mode
(Active High)

Not Used

BSY

Busy Flag (Active High)

Set this bit to a `1' when interfacing the PIXDATA bus to the
ZR36011 Color Space Converter, and to a `0' otherwise.

Setting the CSC bit to a `1`, will modifies the pixel data
internal delays during compression or expansion to match
the delays in the ZR36011 Color Space Converter. A
description of the modified pixel data delays is TBD.

DCM: Select 1/2 Decimation Write Only)

Set this bit to a `1' when selecting 1/2 decimation mode (for
compression only).

MOD(1:0): Pixel Data Mode Select

These bits are set to determine the PXDATA bus to/from
BDATA bus mode of operation. Table 3 shows the availiable
combinations.

EDC: Enclde/Decode select

Selects either encode (EDC = `1'), or decode (EDC = `0')
mode.

GO: Process Go Trigger Bit (Write Only)

Set to `1' to start ZR36015 processing. Prior to setting GO,
the host must...

1) Make sure that the BSY bit is not set.

2) Set all processing parameters in the tables.

When GO is set, the ZR36015 starts counting pixel elements
from the rise of VEN and HEN. When [when is go reset?]

Address Pointer Register(R/W):

This register is a pointer to the configuration tables and line
count register. A write to the configuration table (ADD(1:0) =
"0b11") will write to the table element indicated by the address
pointer regstier. A read from the number of lines registers will
access the register indicated by the address pointer register.
The Address pointer Register is automatically incremented by
one after a read or write with ADD(1:0) set to "0b11".

Configuration Register Tables(R/W):

The contents of the Configuration Table are shown in the below.
The fields of the Configuration Table are defined below and in
Figure 5.

HDelay(12:0): Horizontal delay in number of pixel elements
before active window. The setting range for WDelay(12:0) is
0 to 8191.

HWidth(14:0): Horizontal width of the active image area. The
setting range for Width(14:0) is up to 8191 for.

VDelay(12:0):Verticle delay in number of pixel elements
before active window. The setting range for HDelay(12:0) is
0 to 8191.

MOD(1:0)

PXDATA Format

BDATA Format

1:0:0

4:2:2

4:1:1

ZR36015

PRELIMINARY

VHeight(12:0):Verticle height of the active image area. The
maximum setting for Height(12:0) is 8191. Setting
Height(12:0) to `0' in encode mode, lets the Height of the
active image area be determined by the non-active point of
VEN.

Number of Lines Table:

The Number of Lines Table holds the number of lines processed
in encoding by the ZR36015.

1. Assigned to LSB's of PIXDATA(7:0)

Address Pointer Value

Window Setting Value

HDelay(7:0)

HDelay(12:8)

HWidth(7:0)

HWidth(14:0)

VDelay(7:0)

VDelay(12:8)

VWidth(7:0)

VWidth(13:8)

Number of Lines(7:0)

Number of Lines(13:8)

VDelay

HDelay

Acitve Image

Area

VWidth

HWidth

Enable Area

HEN

VEN

Figure 4. Active Image Area

Operating States

The ZR36015 has four Operating States; Reset, Idle, Compres-
sion and Expansion.

Reset State

While the RESET input is asserted, the ZR36015 is in the Reset
State. In this state the PXDATA and BDATA busses are high
impedance, and the DSYNC, STOP, EOS signals are high
impedance.

After a RESET, the ZR36015 will be in the IDLE state.

Idle State

After a Soft RESET, or after the RESET input signal has been
applied, or at the end of a compression or expansion process,
the ZR36015 will be in the IDLE state. In the IDLE state, no
active processing is taking place, and the PXDATA bus is high
impedance (the bus drivers for the Coder Interface are con-
trolled by the COE signal).

While in the IDLE state, the ZR36015 Configuration Register
Tables can be loaded with the values to select the desired active
image area. Also, the Mode Register is loaded with the desired
Mode of operation, and the number of lines table can be read

To leave the IDLE state and enter one of the processing states
(compression or expansion), the GO bit in the Mode registe is
set.

Compression

When the GO bit is set to "1", and the EDC bit equals "1", then
the ZR36015 enters the Compression State.

Setting the GO bit results in the BSY bit in the mode register
being set.

Once the GO bit is set, then on the falling edge of the Verticle
Sync Signal (VEN), the BSY output signal will be set. The BSY
bit (and output signal) will stay set until the end of the Compres-
sion process. The hardware can monitor the BSY signal, to
determine when the Compression process has completed. Note
that the GO bit must be set at least three SYSCLK cycles before
the VEN goes from High to Low (see figure ???).

Following the above, the ZR36015 monitors the VEN input to
detect the transiton of VEN from low to high. This indicates the
beginning of the image to be processed The next VDelay lines
of data are ignored in order to reach the "active image area".
Then the next VWidth lines of data are processed.

The HEN input synchronizes the line by line transfers of data into
the ZR36015. On the rise of HEN, the next HDelay pixels are
ignored in order to reach the "active image area". Then the next
HWidth pixels are procesed.

Электронный компонент: ZR36015PQC-30