EBE21AD4AGFB-5C-E (Elpida) - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive, DDR2 SDRAM

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EBE21AD4AGFB-5C-E (Elpida)

Electronic component documentation (datasheet) «EBE21AD4AGFB-5C-E» (DDR2 SDRAM), manufacturer Elpida. Download datasheet file:

Datasheet EBE21AD4AGFB-5C-E manufacturer Elpida

Partname	EBE21AD4AGFB-5C-E
Description	* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
Functional	DDR2 SDRAM
Manufacturer	Elpida Memory
Site	www.elpida.com

Size	Pages: 23, 209.82Kb
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EBE21AD4AGFB, EBE21AD4AGFB-4A-E, EBE21AD4AGFB-5C-E, EBE21AD4AGFB-6E-E

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