1
S3023
SONET/SDH/ATM CLOCK RECOVERY UNIT
April 10, 2001 / Revision A
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM CLOCK RECOVERY UNIT
S3023
FEATURES
Complies with Bellcore and ITU-T
specifications for jitter tolerance, jitter transfer
and jitter generation
On-chip high frequency PLL with internal loop
filter for clock recovery
Supports clock recovery for OC-12/STM-4
(622.08 Mbit/s) or OC-3/STM-1 (155.52 Mbit/s)
NRZ data
19.44 MHz reference frequency
Lock detect--monitors frequency
260mW typical power dissipation
Low-jitter LVPECL interface
Maintains downstream clock in absence of data
inputs
3.3V supply
Available in a 20 TSSOP package
Active Low LVPECL Signal Detect
GENERAL DESCRIPTION
The function of the S3023 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3023 is implemented using
AMCC's proven Phase Locked Loop (PLL) technology.
The S3023 receives either an OC-12/STM-4 or OC-3/
STM-1 scrambled NRZ signal and recovers the clock
from the data. The chip outputs a differential LVPECL
bit clock and retimed data. Figure 1 shows a typical
network application.
The S3023 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the reference frequency. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
Figure 1. System Block Diagram
Transceiver
S3033
Controller
Controller
Transceiver
S3033
8
8
8
8
Fiber
Optic
Module
Fiber
Optic
Module
S3023
S3023
2
S3023
SONET/SDH/ATM CLOCK RECOVERY UNIT
April 10, 2001 / Revision A
Figure 2. Functional Block Diagram
SERCLKOP/N
LOCKDET
SERDATOP/N
TTLREF
BYPASS
MODE
LCKREFN
SERDATIP/N
LOOP
FILTER
VCO
CLOCK
DIVIDER
PHASE DETECTOR
LOCK
DETECTOR
SDN
CAP 1,2
3
S3023
SONET/SDH/ATM CLOCK RECOVERY UNIT
April 10, 2001 / Revision A
OVERVIEW
The S3023 supports clock recovery for the OC-12/
STM-4 or OC-3/STM-1 data rates. Differential serial
data is input to the chip at the specified rate and
clock recovery is performed on the incoming data
stream. An external crystal is required to minimize
the PLL lock time and provide a stable output clock
source in the absence of serial input data. Retimed
data and clock are output from the S3023.
CHARACTERISTICS
Performance
The S3023 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
T1X1.6/91-022 document, when used with differential
inputs and outputs as shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in
Figure 5. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied for each of the OC-N/STS-N rates.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 4. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Jitter Generation
The jitter generation of the serial clock and serial
data outputs shall not exceed 0.01 UI when a serial
data input with less than 14ps (OC-12) or 56ps (OC-
3) rms jitter is presented to the serial data inputs.
Figure 3. Clock Output to Data Transition Delay
Output Frequency
622.08 MHz
155.52 MHz
SERDATOP/N Setup Time
450 ps
2.5 ns
SERDATOP/N Hold Time
450 ps
2.5 ns
t S
t H
SERCLKOP
SERDATOP/N
Figure 4. Input Jitter Tolerance Specification
f0
f1
f2
f3
ft
0.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
OC/STS
Level
f0
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
f1
(Hz)
12
10
30
300
25
250
3
10
30
300
6.5
65
Figure 5. Jitter Transfer Specification
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
OC/STS
Level
fc
(kHz)
P
(dB)
12
1,2
500
0.1
3
1,2
130
0.1
1. Bellcore Specifications: TR-NWT-000253, Issue 2,
December 1991.
2. CCITT Recommendations: G.958.
4
S3023
SONET/SDH/ATM CLOCK RECOVERY UNIT
April 10, 2001 / Revision A
Table 1. S3023 Pin Assignment and Descriptions
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S3023
SONET/SDH/ATM CLOCK RECOVERY UNIT
April 10, 2001 / Revision A
AVCC
1
20
AVCC
AGND
2
19
SERDATIP
CAP1
S3023
20 TSSOP
Top View
3
18
SERDATIN
CAP2
4
17
AGND
BYPASS
5
16
LOCKDET
SDN
6
15
MODE
SERDATOP
7
14
TTLREF
SERDATON
8
13
LCKREFN
SERCLKOP
9
12
DGND
SERCLKON
10
11
DVCC
Figure 6. S3023 Pinout
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