Document Outline
- COVER
- Specifications
- Features
- Ordering Information
- Part Number
- Pin Configurations
- Electrical Specifications
- Absolute Maximum Ratings
- Operating Temperature Condition
- Recommended DC Operating Conditions
- DC Characteristics 1
- AC Timing for IDD Test Conditions
- IDD7 Timing Patterns for 8 Banks
- DC Characteristics 2
- DC Characteristics 3
- ODT DC Electrical Characteristics
- OCD Default Characteristics
- Pin Capacitance
- AC Characteristics
- ODT AC Electrical Characteristics
- AC Input Test Conditions
- Block Diagram
- Pin Function
- Command Operation
- Command Truth Table
- CKE Truth Table
- Function Truth Table
- Simplified State Diagram
- Operation of DDR2 SDRAM
- Power On and Initialization
- Power-Up and Initialization Sequence
- Programming the Mode Register and Extended Mode Registers
- DDR2 SDRAM Mode Register Set [MRS]
- DDR2 SDRAM Extended Mode Registers Set [EMRS]
- Off-Chip Driver (OCD) Impedance Adjustment
- ODT (On Die Termination)
- Bank Activate Command
- Read and Write Access Modes
- Posted /CAS
- Burst Mode Operation
- Burst Read Command
- Burst Write Command
- Write Data Mask
- Precharge Command
- Burst Read Operation Followed by Precharge
- Burst Write followed by Precharge
- Auto-Precharge Operation
- Burst Read with Auto Precharge
- Burst Write with Auto-Precharge
- Refresh Requirements
- Automatic Refresh Command
- Self Refresh Command
- Power-Down
- Asynchronous CKE Low Event
- Input Clock Frequency Change during Precharge Power-Down
- Burst Interruption
- No Operation Command
- Deselect Command
- Package Drawing
- Recommended Soldering Conditions
Document No. E0852E20 (Ver. 2.0)
Date Published April 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005-2006
PRELIMINARY DATA SHEET
1G bits DDR2 SDRAM
EDE1104ABSE (256M words
4 bits)
EDE1108ABSE (128M words
8 bits)
EDE1116ABSE (64M words
16 bits)
Specifications
Density: 1G bits
Organization
32M words
4 bits
8 banks (EDE1104ABSE)
16M words
8 bits
8 banks (EDE1108ABSE)
8M words
16 bits
8 banks (EDE1116ABSE)
Package
68-ball FBGA (EDE1104/1108ABSE)
92-ball FBGA (EDE1116ABSE)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
1.8V
0.1V
Data rate
800Mbps/667Mbps/533Mbps/400Mbps (max.)
1KB page size (EDE1104/1108ABSE)
Row address: A0 to A13
Column address: A0 to A9, A11 (EDE1104ABSE)
A0 to A9 (EDE1108ABSE)
2KB page size (EDE1116ABSE)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8
s at 0
C
TC
+
85
C
3.9
s at
+
85
C
<
TC
+
95
C
Operating case temperature range
TC = 0
C to +95
C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
8
organization compatible to
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Prelimininary Data Sheet E0852E20 (Ver. 2.0)
2
Ordering Information
Part number
Mask
version
Organization
(words
bits)
Internal
Banks
Speed bin
(CL-tRCD-tRP)
Package
EDE1104ABSE-8E-E
EDE1104ABSE-6C-E
EDE1104ABSE-6E-E
EDE1104ABSE-5C-E
EDE1104ABSE-4A-E
B 256M
4
8
DDR2-800 (5-5-5)
DDR2-667 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
68-ball FBGA
EDE1108ABSE-8E-E
EDE1108ABSE-6C-E
EDE1108ABSE-6E-E
EDE1108ABSE-5C-E
EDE1108ABSE-4A-E
128M
8
DDR2-800 (5-5-5)
DDR2-667 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
EDE1116ABSE-6E-E
EDE1116ABSE-5C-E
EDE1116ABSE-4A-E
64M
16
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
92-ball FBGA
Part Number
Elpida Memory
Density / Bank
11: 1Gb / 8-bank
Organization
04: x4
08: x8
16: x16
Power Supply, Interface
A: 1.8V, SSTL_18
Die Rev.
Package
SE: FBGA (with back cover)
Speed
8E: DDR2-800 (5-5-5)
6C: DDR2-667 (4-4-4)
6E: DDR2-667 (5-5-5)
5C: DDR2-533 (4-4-4)
4A: DDR2-400 (3-3-3)
Product Family
E: DDR2
Type
D: Monolithic Device
E D E 11 04 A B SE - 8E - E
Environment code
E: Lead Free
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Prelimininary Data Sheet E0852E20 (Ver. 2.0)
3
Pin Configurations
/xxx indicates active low signal.
DQ14
1
VDDQ
VDDQ
DQ12
VDD
DQ6
BA2
VDDL
2
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
3
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
/WE
BA1
A1
7
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
8
VSSQ
DQ8
VSSQ
/LDQS
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
9
DQ15
VDDQ
DQ13
VDDQ
DQ7
DQ5
VDD
ODT
VDD
(Top view)
92-ball FBGA
DQ4
VDDQ
(
16 organization)
VDD
NC
VSS
VSSQ /UDQS VDDQ
VDD
A7
A12
A9
NC
A11
NC
A8
NC
VSS
VSS
A3
A5
A6
A4
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
X
AA
NC
NC
VDD
1
DQ6
(NC)*
VDDQ
DQ4
(NC)*
VDDL
VSS
VDD
2
NU/ /RDQS
(NC)*
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
3
VSS
DM/RDQS
(DM)*
VDDQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
8
/DQS
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
9
VDDQ
DQ7
(NC)*
VDDQ
DQ5
(NC)*
VDD
VDD
VSS
(Top view)
68-ball FBGA
Note: ( )* marked pins are for
4 organization.
BA2
ODT
(
8,
4 organization)
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
NC
NC
NC
NC NC NC
Pin name
Function
Pin name
Function
A0 to A13
Address inputs
ODT
ODT control
BA0, BA1, BA2
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ15
Data input/output
VSS
Ground for internal circuit
DQS, /DQS,
UDQS, /UDQS,
LDQS, /LDQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
RDQS, /RDQS
Differential data strobe for read
VSSQ
Ground for DQ circuit
/CS
Chip select
VREF
Input reference voltage
/RAS, /CAS, /WE
Command input
VDDL
Supply voltage for DLL circuit
CKE
Clock enable
VSSDL
Ground for DLL circuit
CK, /CK
Differential clock input
NC*
1
No
connection
DM, UDM, LDM
Write data mask
NU*
2
Not
usable
Notes: 1. Not internally connected with die.
2. Don't connect. Internally connected.
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Prelimininary Data Sheet E0852E20 (Ver. 2.0)
4
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................17
Pin Function.................................................................................................................................................18
Command Operation ...................................................................................................................................20
Simplified State Diagram .............................................................................................................................27
Operation of DDR2 SDRAM ........................................................................................................................28
Package Drawing ........................................................................................................................................64
Recommended Soldering Conditions..........................................................................................................66
EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Prelimininary Data Sheet E0852E20 (Ver. 2.0)
5
Electrical Specifications
All voltages are referenced to VSS (GND)
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Notes
Power supply voltage
VDD
-
1.0 to +2.3
V
1
Power supply voltage for output
VDDQ
-
0.5 to +2.3
V
1
Input voltage
VIN
-
0.5 to +2.3
V
1
Output voltage
VOUT
-
0.5 to +2.3
V
1
Storage temperature
Tstg
-
55 to +100
C 1,
2
Power dissipation
PD
1.0
W
1
Short circuit output current
IOUT
50
mA
1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter Symbol
Rating Unit
Notes
Operating case temperature
TC
0 to +95
C 1,
2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0C to +85C with full AC and DC specifications.
Supporting 0C to +85C and being able to extend to +95C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9s) and higher temperature Self-Refresh entry via A7 "1" on
EMRS (2).
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