Document Outline
- General Description
- Features
- Pin Assignment
- Block Diagram
- Pin Descriptions
- Pin Characteristics
- Bank A Frequency Table
- Bank B Frequency Table
- Output Bank Configuration Select Function Tables
- Feedback Divider Configuration Select Function Table
- CLK_EN Timing Diagram
- CLK_ENA Select Function Table
- CLK_ENB Select Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS DC Characteristics
- LVDS 3.3V DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- 3.3V LVDS Driver Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
1
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS844003I-01 is a 3 differential output LVDS
Synthesizer designed to generate Ethernet refer-
ence clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequen-
cies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 844003I-01 has 2
output banks, Bank A with 1 differential LVDS output pair and
Bank B with 2 differential LVDS output pairs.
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies men-
tioned above. The ICS844003I-01 uses ICS' 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844003I-01 is packaged in a small
24-pin TSSOP package.
F
EATURES
Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz to 680MHz
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
3.3V output supply mode
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
0
1
0
1
Phase
Detector
VCO
0 = 25 (default)
1 = 32
0 0 1
0 1 2
1 0 3
1 1 4
(default)
0 0 2
0 1 4
1 0 5
1 1 8
(default)
FB_DIV
OSC
B
LOCK
D
IAGRAM
CLK_ENA
DIV_SELA[1:0]
VCO_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
XTAL_SEL
FB_DIV
DIV_SELB[1:0]
MR
CLK_ENB
QA0
nQA0
QB0
nQB0
QB1
nQB1
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
P
IN
A
SSIGNMENT
ICS844003I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
DIV_SELB0
VCO_SEL
MR
V
DDO
_
A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
V
DDA
V
DD
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
DIV_SELB1
V
DDO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
24
23
22
21
20
19
18
17
16
15
14
13
Pulldown
Pullup
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
2
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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844003AGI-01
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REV. A MAY 31, 2005
3
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
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PRELIMINARY
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844003AGI-01
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REV. A MAY 31, 2005
4
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3C. O
UTPUT
B
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C
ONFIGURATION
S
ELECT
F
UNCTION
T
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T
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D
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C
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1. CLK_EN T
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TEST_CLK
CLK_ENx
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844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
5
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_A
= V
DDO_B
= 3.3V5%, TA = -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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-
A
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
6
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_A
= V
DDO_B
= 3.3V5%, TA = -40C
TO
85C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_A
= V
DDO_B
= 3.3V5%, TA = -40C
TO
85C
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844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
7
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.56ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
100
1k
10k
100k
1M
10M
100M
dBc
Hz
N
OISE
P
O
WER
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
8
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
tsk(b)
QA0,
QB0, QB1
nQA0,
nQB0, nQB1
tsk(o)
Qy
Qx
nQy
nQx
nQB0
QB0
nQB1
QB1
P
ARAMETER
M
EASUREMENT
I
NFORMATION
B
ANK
S
KEW
LVDS 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
SCOPE
Qx
nQx
LVDS
Power Supply
+
-
Float GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
RMS P
HASE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
O
FFSET
V
OLTAGE
S
ETUP
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
V
DD
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
9
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844003I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 3 below
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
were determined using a 19.53125MHz or 25MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS844003I-01
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844003I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
10
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3.3V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 4. In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
F
IGURE
4. T
YPICAL
LVDS D
RIVER
T
ERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844003I-01 is: 3537
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
R1
100
3.3V
100 Ohm Differential Transmission Line
3.3V
+
-
LVDS
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
11
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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4
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-
-
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2
.
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1
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0
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
12
Integrated
Circuit
Systems, Inc.
ICS844003I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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