1
STEL-2040B
STEL-2040B
Convolutional Encoder
Viterbi Decoder
STEL-2040B
Data Sheet
Netw
or
k Comm
unica
tions Gr
oup - Ca
ble Netw
or
k Oper
a
tion
STEL-2040B
2
FEATURES
n
Constraint Length 7
n
Rates
1
/
3
,
1
/
2
,
2
/
3
* and
3
/
4
* (*Punctured)
n
Built in BER Monitor
n
Programmable Scrambler:
V.35 (CCITT or IESS)
n
Differential Encoder and Decoder
n
Three Bit Soft Decision Inputs in Signed
Magnitude or 2's Complement Formats
n
Up to 256 Kbps Data Rate (0 to 70 C)
n
Coding Gain of 5.2 dB (@ 10
-5
BER, Rate
1
/
2
)
n
Industry Standard Polynomials
G1=171
8
, G2=133
8
, G3=145
8
,
n
Microprocessor Interface
n
Low Power Consumption
n
68-pin PLCC and CLDCC Packages
n
Commercial and Military Temperature
Ranges Available
BLOCK DIAGRAM
D I FF E R E N TIA L
D E C O D E R
A N D V .3 5
D E S C R A M -
B L E R S
D I FFE R E N T IA L
E N C O D E R
A N D V .3 5
S C R A M B L E R S
D R A TE
S M 2 C
TR E L L I S
R A M
D ATA
A D D R
D O D I
S T A TE -M E TR IC
R A M
3
3
3
A D D R E S S
S E Q U E N C E R A N D
C O N TR O L L O G I C
B R A N C H M E TR IC
A N D A D D -C O M PA R E -
S E L E C T L O G I C
PAT H H I S TO R Y A N D
A U TO N O D E -S Y N C
L O G IC
D O U T
I C L K
D R D Y
A C K
G 1 D
2-0
G 2 D
2-0
G 3 D
2-0
S Y N C 0
S Y N C 1
S S T0
S S T 1
TH R E S H
M IS
3
S Y N C
O C L K
D ATA I N
S E L A , B
R E A D , W R I TE
E N L AT C H
D
Q
3 : 1 M U X
O S Y M B
L ATC H
D ATA C L K
M O D E
E R AT E
M IC R O P R O C E S S O R
I N T E R FA C E ,
M O D E S E L E C T
A N D C O N T R O L
S E L E C T
S C R A M
1-0
R E S E T
(T O A L L R E G S . )
E N C O D E R S E C TI O N
D E C O D E R S E C TI O N
2
D E S C R A M -
B L E R ,
B U F FE R
R E G .
& M U X .
2
2
2
A D D R
4
8
D ATA
P N C G 1
P N C G 2
B E R
M O N I TO R
G 3 E R R
G 2 E R R
G 1 E R R
B E R R
P D IS
C O N V O L U T IO N A L
E N C O D E R
3
STEL-2040B
Notes: (1) Tolerances on pin spacing are not cumulative.
(2) Dimensions apply at seating plane.
(3) PLCC and CLDCC packages have different corners and may not fit into sockets designed
for the other type. Universal sockets are available without alignment locators.
0.145"
max.
0.990"
0.010"
0.035"
nominal
0.951"
0.009"
6 6 6 6 6 6 6 6
9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.05"
*Tolerance not
cumulative
0.017"
0.005" **
**At seating
plane
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
6 6 6 6 6 6 6 6
9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.200"
max.
0.990"
0.005"
0.05" *
*Tolerance not
cumulative
0.017"
0.004" **
**At seating
plane
TOP
VIEW
0.954"
0.004"
0.005" *
Package: 68 pin CLDCC
Thermal coefficient,
ja
= 34C/W
Package: 68 pin PLCC
Thermal coefficient,
ja
= 36C/W
FUNCTIONAL DESCRIPTION
Convolutional Encoding and Viterbi Decoding are used to
provide forward error correction (FEC) which improves digital
communication performance over a noisy link. In satellite
communication systems where transmitter power is limited,
FEC techniques can reduce the required transmission power.
The STEL-2040B is a specialized product designed to perform
this specific communications related function.
The encoder creates a stream of symbols which are
transmitted at 2 (Rate
1
/
2
) or 3 (Rate
1
/
3
) times the information
rate. This encoding introduces a high degree of redundancy
which enables accurate decoding of information despite a
high symbol error rate resulting from a noisy link. The coding
overhead can be reduced at the expense of the coding gain
by puncturing (deleting) some of the symbols. The STEL-
2040B is designed to operate in this way at Rate
3
/
4
. In this
case 4 symbols are transmitted for every 3 bits encoded. The
resulting bandwidth overhead is just 33% in this case,
compared with 100% at Rate
1
/
2
.
The STEL-2040B incorporates all the memories required to
perform these functions. In addition, the STEL-2040B
incorporates a differential encoder and decoder, two
scrambling algorithms, a BER monitor and a microprocessor
interface. The STEL-2040B is available in a 68-pin PLCC
(plastic leaded chip carrier) and also in a ceramic leaded chip
carrier (J-bend leads).
PIN CONFIGURATION
PIN CONNECTIONS
1
SYNC
2
V
SS
3
ACK
4
DATACLK
5
DRDY
6
DATAIN
7
MODE
8
SEL A
9
SEL B
10 G3D
2
11 G3D
1
12 G3D
0
13 PNCG2
14 G2D
2
15 G2D
1
16 G2D
0
17 PNCG1
18 G1D
2
19 G1D
1
20 G1D
0
21 DIFEN
22 BERR
23 V
SS
24 G1ERR
25 G2ERR
26 G3ERR
27 ADDR
3
28 ADDR
2
29 ADDR
1
30 ADDR
0
31 V
SS
32 V
SS
33 WRITE
34 READ
35 V
DD
36 DATA
7
37 DATA
6
38 DATA
5
39 DATA
4
40 DATA
3
41 DATA
2
42 DATA
1
43 DATA
0
44 V
SS
45 I.C.
46 DRATE
47 THRESH
0
48 THRESH
1
49 THRESH
2
50 MIS
51 V
SS
52 RESET
53 V
DD
54 SM2C
55 PDIS
56 DOUT
57 SST0
58 SYNC0
59 SST1
60 SYNC1
61 ERATE
62 ENLATCH
63 OSYMB
64 V
DD
65 ICLK
66 OCLK
67 SCRAM1
68 SCRAM0
Notes: 1. I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias.
2. Connect all unused inputs except READ to V
SS
, leave unused outputs unconnected. If the
READ input is not used it should be connected to V
DD
.
STEL-2040B
4
is accomplished by connecting the node sync outputs
(SST0 and SST1) to the node sync inputs (SYNC0 and
SYNC1). The threshold for determining the out of sync
condition is user selectable by means of the THRESH
2-0
inputs. Alternatively, the SYNC0 and SYNC1 pins can be
used with an external algorithm to achieve the same result.
Further information on the theory of operation of Viterbi
decoders may be obtained from text books such as "Error-
Correcting Codes", by Peterson and Weldon (MIT Press),
or "Error Control Coding", by Lin and Costello (Prentice-
Hall). An alternative source of information is the many
papers on this subject that have appeared in the IEEE
transactions, such as "Convolutional Codes and their
Performance in Communication Systems", by Dr. A. J.
Viterbi, IEEE Trans. on Communications Technology,
October 1971.
FUNCTION BLOCK DESCRIPTION
ENCODER
The convolutional coder is functionally independent of
the decoder. A single data bit is clocked into the 7-
bit shift register on the rising edge of DATA CLK. There
are two modes of operation, controlled by the MODE
input. When MODE is low the timing of the SEL A, SEL B
and ENLATCH signals determine whether 2 or 3 symbol
bits are generated for every data bit. When MODE is high
the symbols are automatically generated sequentially
every clock cycle. In this case, the state of ERATE
determines whether the device generates symbols for
Rate
1
/
2
or Rate
1
/
3
operation. The symbols G1, G2, and G3
are generated from the modulo-2 sum (exclusive-OR) of
the inputs to the 3 generators from the taps on the shift
register. The 3 polynomials are 171
8
(G1), 133
8
(G2), and
145
8
(G3). Example inputs are shown in the timing diagram
for both rate
1
/
2
and rate
1
/
3
operation.
DECODER
The STEL-2040B is designed to accept symbols either
synchronously or in a handshake mode. Symbols are
latched into the decoder input registers on the falling edge
of the DRDY input. ACK is returned by the decoder to
indicate that the symbols have been accepted.
The RATE input determines whether the decoder will
operate in Rate
1
/
2
or Rate
1
/
3
mode. When operating at
Rate
1
/
2
the G3 symbol is ignored by the decoder.
For hard decision binary symbols the G1, G2, G3 symbol
bits should be connected to pins G1D
2
, G2D
2
and G3D
2
respectively, and the other symbol input pins should be
tied high (V
DD
). Three-bit soft decision symbols may be
input in Signed Magnitude or Inverted Two's
Complement code, according to the setting of the code
control pin, SM2C. The code should be set to Signed
Magnitude when using hard decision data.
A single decoded data bit is output for every set of input
symbols. The data bit corresponding to a particular
symbol set will be output after a delay of 71 symbols.
Therefore, when using the STEL-2040B to decode blocks
of data 71 additional dummy symbols and 71 DRDY
signals need to be added to the data stream to flush the
last 71 decoded data bits out of the decoder.
Node synchronization (correctly grouping incoming
symbols into G1, G2, and G3 sets) is inherent with many
communication techniques such as TDMA and spread
spectrum systems. If node synchronization is not an
inherent property of the communications link then the
internal auto node sync circuit can be used to do this. This
INPUT SIGNALS
RESET
Asynchronous master Reset. A logic low on this pin will clear
all registers on the STEL-2040B in both the encoder and
decoder sections of the chip. RESET should remain low
for at least 3 cycles of ICLK.
DATACLK
This is the encoder Shift Register Clock. A rising edge on
this clock latches DATAIN into the encoder shift register.
This signal should nominally be a square wave with a
maximum frequency of 256 KHz.
DATAIN
This is the encoder input. The data present at this pin is
latched into the encoder shift register on the rising edge
of DATACLK. This signal should be stable at the rising
edge of DATACLK.
MODE
The state of the MODE input determines the method of
symbol sequencing in the encoder. When MODE is set
low the sequencing is generated externally under the
control of the SEL A and SEL B inputs, and when MODE
is set high it is generated automatically.
SEL A, SEL B
When MODE is set low SEL A and SEL B select the
encoded symbol, G1, G2 or G3, which will appear on the
OSYMB pin on the next rising edge of ENLATCH
according to the table:
5
STEL-2040B
SEL A
SEL B
SYMBOL
POLYNOMIAL
0
1
G1
171
8
(1111001
2
)
1
0
G2
133
8
(1011011
2
)
0
0
G3
145
8
(1100101
2
)
When MODE is set high the symbol sequence is
generated automatically and the SEL A and SEL B inputs
are inactive.
ERATE
When MODE is high the Encoder Rate input determines
whether symbols for Rate
1
/
2
(ERATE=1) or Rate
1
/
3
(ERATE=0) operation are generated. When MODE is low
this input is inactive.
DIFEN
When the DIFEN input is set high the differential encoder
and decoder in the STEL-2040B are enabled. Differential
encoding is done after V.35 scrambling (when used) but
before Invert G2 scrambling (when used) in the encoder.
The sequence is reversed in the decoder. Note that the
BER monitor function will only operate correctly when
DIFEN is set low.
SCRAM0, SCRAM1
The Scramble inputs are used to enable the two scrambler
functions included in the STEL-2040B, as shown in the
table below:
SCRAM0
SCRAM1
FUNCTION
0
0
Scrambler disabled
0
1
V.35 (CCITT compatible)
1
1
V.35 (IESS compatible)
Two different "V.35" scrambler formats are provided since
there are two versions of this standard in exixtence: the
true CCITT version of the standard, and the IESS version,
which has become a de facto standard through widespread
use. In each case, the scrambling function is provided at
the encoder and the descrambler is provided at the
decoder.
ENLATCH
This is the encoder Output Latch Enable. The new symbol
is clocked into the output latch and appears on the
OSYMB pin on the rising edge of ENLATCH. When
MODE is low the symbol selected will depend on the
states of the SEL A and SEL B lines, which should be
stable on the rising edge of ENLATCH. When MODE is
high the symbol selection is internal, and the frequency
of the ENLATCH signal should be 2 or 3 times the
frequency of the DATACLK, depending on the rate
selected.
ICLK, OCLK
System Clock. A crystal may be connected between ICLK
and OCLK or a CMOS level clock may be fed into ICLK
only. The clock frequency should be at least 70 times the
data rate but no more than 18 MHz.
DRATE
The Decoder Rate input selects whether the decoder will
read two symbols (DRATE set high) or three symbols
(DRATE set low)) for every data bit decoded. During Rate
1
/
2
operation the symbol G3 on inputs G3D
2-0
is
completely ignored by the decoder. DRATE should be set
high for Rate
3
/
4
operation.
G1D
2-0
, G2D
2-0
, G3D
2-0
The three 3-bit soft decision symbols are connected to
these inputs and loaded into the input registers on the
falling edge of DRDY. The order in which the symbols are
entered into the decoder from the registers depends on
the state of the SYNC0 and SYNC1 inputs. The decoder
can make use of soft decision information, which includes
both polarity information and a confidence measure, to
improve the decoder performance. If hard decision (single
bit) symbols are used the signals are connected to pins
G1D
2
, G2D
2
and G3D
2
and the other inputs are connected
to V
DD
. See SM2C for a description of the input data
codes.
SM2C
The state of the Signed Magnitude/2's Complement input
determines the format of the incoming soft-decision
symbols into the decoder. When SM2C is high the input
code is Signed Magnitude, and when it is low the code is
Two's Complement. The codes are shown in the following
table:
CODE CONTROL:
SM2C=1
SM2C=0
SYMBOL INPUT:
GXD2-GXD0
GXD2-GXD0
Most Confident '+' level
0 1 1
0 1 1
Data = 0
0 1 0
0 1 0
0 0 1
0 0 1
Least Confident '+' level
0 0 0
0 0 0
Least Confident '' level
1 0 0
1 1 1
Data = 1
1 0 1
1 1 0
1 1 0
1 0 1
Most Confident '' level
1 1 1
1 0 0
SM2C should be set high when using hard decision data.
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