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Электронный компонент: CDP1824CE

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6-37
Features
Fast Access Time
- V
DD
= 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns
- V
DD
= 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns
No Precharge or Clock Required
Description
The CDP1824 and CDP1824C are 32-word x 8-bit fully static
CMOS random-access memories for use in CDP-1800
series microprocessor systems. These parts are compatible
with the CDP1802 microprocessor and will interface directly
without additional components.
The CDP1824 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has
common input and output and is operated from a single
voltage supply. The MRD signal (output disable control)
enables the three-state output drivers, and overrides the
MWR signal. A CS input is provided for memory expansion.
The CDP1824C is functionally identical to the CDP1824.
The CDP1824 has an operating range of 4V to 10.5V, and
the CDP1824C has an operating voltage range of 4V to
6.5V. The CDP1824 and CDP1824C are supplied in 18 lead
hermetic dual-in-line ceramic packages (D suffix), and in 18
lead dual-in-line plastic packages (E suffix).
Pinout
CDP1824, CDP1824C (PDIP, SBDIP)
TOP VIEW
Ordering Information
5V
10V
PACKAGE
TEMPERATURE RANGE
PKG. NO.
CDP1824CE
CDP1824E
PDIP
-40
o
C to +85
o
C
E18.3
CDP1824CEX
CDP1824EX
Burn-In
E18.3
CDP1824CD
CDP1824D
SBDIP
-40
o
C to +85
o
C
D18.3
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
V
DD
MRD
CS
BUS 0
BUS 1
BUS 2
BUS 3
MWR
BUS 4
MA4
MA3
MA2
MA1
MA0
BUS 7
BUS 5
BUS 6
V
SS
OPERATIONAL MODES
FUNCTION
CS
MRD MWR
DATA PINS STATUS
READ
0
0
X
Output: High/Low Dependent
on Data
WRITE
0
1
0
Input: Output Disabled
Not
Selected
1
X
X
Output Disabled:
High-Impedance State
Standby
0
1
1
Output Disabled:
High-Impedance State
Logic 1 = High
Logic 0 = Low
X = Don't Care
March 1997
CDP1824,
CDP1824C
32-Word x 8-Bit Static RAM
File Number
1103.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
6-38
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal)
CDP1824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1824C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Temperature Range (T
A
)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Thermal Resistance (Typical)
JA
(
o
C/W)
JC
(
o
C/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
75
20
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range (T
STG
). . . . . . . . . . . .-65
o
C to +150
o
C
Lead Temperature (During Soldering)
At distance 1/16
1/32 In. (1.59
0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
Recommended Operating Conditions
At T
A
= Full Package Temperature Range.For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
PARAMETER
CONDITION
LIMITS
UNITS
V
DD
(V)
CDP1824D
CDP1824CD
MIN
MAX
MIN
MAX
Supply Voltage Range
-
4
10.5
4
6.5
V
Recommended Input Voltage Range
-
V
SS
V
DD
V
SS
V
DD
V
Input Signal Rise or Fall Time (Note 1)
5
-
5
-
5
s
t
R
, t
F
10
-
2
-
-
s
NOTE:
1. Input signal rise or fall times longer than these maxima can cause loss of stored data in either the selected or deselected mode.
Static Electrical Specifications
At T
A
= -40
o
C to +85
o
C, Except as Noted:
PARAMETER
SYMBOL
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
CDP1824
CDP1824C
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
Quiescent Device
Current
I
DD
-
-
5
-
25
50
-
100
200
A
-
-
10
-
250
500
-
-
-
A
Output Low (Sink)
Current
I
OL
0.4
0, 5
5
1.8
2.2
-
1.8
2.2
-
mA
0.5
0, 10
10
3.6
4.5
-
-
-
-
mA
Output High (Source)
Current
I
OH
4.6
0, 5
5
-0.9
-1.1
-
-0.9
-1.1
-
mA
9.5
0, 10
10
-1.8
-2.2
-
-
-
-
mA
Output Voltage
Low-Level
V
OL
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
Output Voltage
High-Level
V
OH
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
Input Low Voltage
V
IL
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
1.9
-
10
-
-
3
-
-
-
V
Input High Voltage
V
IH
0.5, 9.5
-
5
3.5
-
-
3.5
-
-
V
1.9
-
10
7
-
-
-
-
-
V
Input Leakage Current
I
IN
Any
Input
0, 5
5
-
0.1
1
-
0.1
1
A
0, 10
10
-
0.1
1
-
-
-
A
Operating Current
(Note 2)
I
DD1
-
0, 5
5
-
4
8
-
4
8
mA
-
0, 10
10
-
8
16
-
-
-
mA
CDP1824, CDP1824C
6-39
Three-State Output
Leakage Current
I
OUT
0, 5
0, 5
5
-
0.2
2.0
-
0.2
2
A
0, 10
0, 10
10
-
0.2
2.0
-
-
-
A
Input Capacitance
C
IN
-
-
-
-
5
7.5
-
5
7.5
pF
Output Capacitance
C
OUT
-
-
-
-
10
15
-
10
15
pF
NOTES:
1. Typical values are for T
A
= +25
o
C and nominal V
DD
.
2. Outputs open circuited; Cycle time = 1
s.
Static Electrical Specifications
At T
A
= -40
o
C to +85
o
C, Except as Noted: (Continued)
PARAMETER
SYMBOL
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
CDP1824
CDP1824C
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
Dynamic Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
5%, Input t
R
, t
F
= 10ns, C
L
= 50pF, R
L
= 200k
; See Figure 1
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
CDP1824D, CDP1824E
CDP1824CD, CDP1824CE
V
DD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
READ OPERATION
Access Time From
Address Change
t
AA
5
-
400
710
-
400
710
ns
10
-
200
320
-
-
-
ns
Access Time From
Chip Select
t
DOA
5
-
300
710
-
300
710
ns
10
-
150
320
-
-
-
ns
Output Active From MRD
t
AM
5
-
300
710
-
300
710
ns
10
-
150
320
-
-
-
ns
NOTES:
1. Time required by a limit device to allow for the indicated function.
2. Time required by a typical device to allow for the indicated function. Typical values are for T
A
= +25
o
C and nominal V
DD
.
NOTES:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAMS
MRD
MA
CS
DATA OUT
HIGH IMPEDANCE
t
AM
t
AA
t
DOA
(NOTE 1)
(NOTE 1)
CDP1824, CDP1824C
6-40
Dynamic Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
5%, Input t
R
, t
F
= 10ns, C
L
= 50pF, R
L
= 200k
; See Figure 2
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
CDP1824D, CDP1824E
CDP1824CD, CDP1824CE
V
DD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
WRITE OPERATION
Write Pulse Width
t
WRW
5
390
200
-
390
200
-
ns
10
180
150
-
-
-
-
ns
Data Setup Time
t
DS
5
390
100
-
390
100
-
ns
10
180
50
-
-
-
-
ns
Data Hold Time
t
DH
5
70
40
-
70
40
-
ns
10
35
20
-
-
-
-
ns
Chip Select Setup Time
t
CS
5
425
210
-
425
210
-
ns
10
215
110
-
-
-
-
ns
Address Setup Time
t
AS
5
640
500
-
640
500
-
ns
10
390
300
-
-
-
-
ns
NOTES:
1. Time required by a limit device to allow for the indicated function.
2. Time required by a typical device to allow for the indicated function. Typical values are for T
A
= +25
o
C and nominal V
DD
.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
NOTE: t
R
, t
F
> 1
s.
FIGURE 3. LOW V
DD
DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
t
AS
t
CS
t
WRW
t
DS
t
DH
MA
CS
MWR
BUS
DATA RETENTION
MODE
0.95 V
DD
0.95 V
DD
t
R
V
DR
t
F
(NOTE 1)
(NOTE 1)
V
DD
t
CDR
V
IH
V
IL
CS
V
IH
V
IL
t
RC
CDP1824, CDP1824C
6-41
Data Retention Specifications
at T
A
= -40
o
C to +85
o
C; See Figure 3
PARAMETER
SYMBOL
TEST CONDITIONS
LIMITS
UNITS
V
DD
(V)
CDP1824
CDP1824C
MIN
MAX
MIN
MAX
Data Retention Voltage
V
DR
-
2.5
-
2.5
-
V
Data Retention Quiescent Current
I
DD
V
DR
= 2.5V
-
-
10
-
40
A
Chip Deselect to Data Retention
Time
t
CDR
V
DR
= 2.5V
5
600
-
600
-
ns
10
300
-
-
-
ns
Recovery to Normal Operation Time
t
RC
V
DR
= 2.5V
5
600
-
600
-
ns
10
300
-
-
-
ns
FIGURE 4. FUNCTIONAL DIAGRAM
FIGURE 5. CDP1824 (128 X 8) MINIMUM SYSTEM (128 X 8)
MA4
MA3
MA2
MA1
MA0
MWR
CS
V
DD
= 18
V
SS
= 9
BUS
7
BUS
6
BUS
5
BUS
4
BUS
3
BUS
2
BUS
1
BUS
0
MRD
16
5
4
3
2
1
17
15
6
7
8
10
11
12
13
14
ADDRESS
DECODER
32 X 8-BIT
ARRAY
SENSE
AMPL
I/O BUFFERS
ADDRESS
CPU/ROM SYSTEM
RAM SYSTEM
MA0-MA7
MA0-MA7
MA0-MA7
MRD
MWR
CS
CE0
MRD
TPA
BUS0-BUS7
BUS0-BUS7
BUS0-BUS7
TPA
MRD
MWR
DATA
ROM
CPU
CDP1802
RAM
CDP1824
CDP1824, CDP1824C