3-1
TM
HI5731
12-Bit, 100 MSPS, High Speed D/A
Converter
The HI5731 is a 12-bit, 100 MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.
Pinout
HI5731
(PDIP, SOIC)
TOP VIEW
Features
Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 100 MSPS
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . .3.0pV-s
TTL/CMOS Compatible Inputs
Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
Excellent Spurious Free Dynamic Range
Applications
Cellular Base Stations
GSM Base Stations
Wireless Communications
Direct Digital Frequency Synthesis
Signal Reconstruction
Test Equipment
High Resolution Imaging Systems
Arbitrary Waveform Generators
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI5731BIP
-40 to 85
28 Ld PDIP
E28.6
HI5731BIB
-40 to 85
28 Ld SOIC
M28.3
HI5731-EVS
25
Evaluation Board (SOIC)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
REF OUT
CTRL OUT
CTRL IN
R
SET
I
OUT
ARTN
DV
EE
DGND
DV
CC
CLOCK
AGND
AV
EE
I
OUT
Data Sheet
May 2000
File Number
4070.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
Intersil Corporation 2000
3-2
Typical Application Circuit
Functional Block Diagram
D9 (3)
D8 (4)
D7 (5)
D6 (6)
D5 (7)
D4 (8)
D3 (9)
D2 (10)
D9
D8
D7
D6
D5
D4
D3
D2
+5V
DV
CC
(16)
0.01
F
DGND (17, 28)
CLK (15)
-5.2V (AV
EE
)
0.1
F
(19) ARTN
(22) AV
EE
D/A OUT
(21) I
OUT
(20) I
OUT
(23) R
SET
976
64
(24) CTRL IN
HI5731
D10
D11
D11 (MSB) (1)
D10 (2)
DV
EE
(18)
- 5.2V (AV
EE
)
0.01
F
(25) CTRL OUT
(26) REF OUT
64
0.1
F
- 5.2V (DV
EE
)
0.01
F
0.1
F
(27) AGND
50
D1 (11)
D0 (LSB) (12)
D1
D0
UPPER
SLAVE
I
OUT
(LSB) D0
D1
D2
D3
D4
D5
D6
D9
D7
D8
4-BIT
DECODER
I
OUT
+
-
CTRL
REF OUT
R
SET
CTRL
25
12-BIT
MASTER
REGISTER
AV
EE
AGND
DV
EE
DGND DV
CC
15
SWITCHED
CURRENT
CELLS
D10
(MSB) D11
REGISTER
DATA
BUFFER/
LEVEL
SHIFTER
OVERDRIVEABLE
VOLTAGE
REFERENCE
CLK
REF CELL
IN
OUT
8 LSBs
CURRENT
CELLS
R2R
NETWORK
227
227
15
15
ARTN
HI5731
3-3
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage V
CC
to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DV
EE
to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AV
EE
to AGND, ARTN . . . . . -5.5V
Digital Input Voltages (D11-D0, CLK) to DGND . . . . . DV
CC
to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . .
2.5mA
Voltage from CTRL IN to AV
EE
. . . . . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . .
2.5mA
Reference Input Voltage Range . . . . . . . . . . . . . . . . . .-3.7V to AV
EE
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature
HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal
T
A
= 25
o
C for All Typical Values
PARAMETER
TEST CONDITIONS
HI5731BI
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
12
-
-
Bits
Integral Linearity Error, INL
(Note 4) ("Best Fit" Straight Line)
-
0.75
1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
0.5
1.0
LSB
Offset Error, I
OS
(Note 4)
-
20
75
A
Full Scale Gain Error, FSE
(Notes 2, 4)
-
1
10
%
Offset Drift Coefficient
(Note 3)
-
-
0.05
A/
o
C
Full Scale Output Current, I
FS
-
20.48
-
mA
Output Voltage Compliance Range
(Note 3)
-1.25
-
0
V
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 3)
100
-
-
MSPS
Output Voltage Full Scale Step
Settling Time, t
SETT
, Full Scale
To
0.5 LSB Error Band R
L
= 50
(Note 3)
-
20
-
ns
Singlet Glitch Area, GE (Peak)
R
L
= 50
(Note 3)
-
5
-
pV-s
Doublet Glitch Area, (Net)
-
3
-
pV-s
Output Slew Rate
R
L
= 50
, DAC Operating in Latched Mode (Note 3)
-
1,000
-
V/
s
Output Rise Time
R
L
= 50
, DAC Operating in Latched Mode (Note 3)
-
675
-
ps
Output Fall Time
R
L
= 50
, DAC Operating in Latched Mode (Note 3)
-
470
-
ps
Spurious Free Dynamic Range within a Window
(Note 3)
f
CLK
= 10 MSPS, f
OUT
= 1.23MHz, 2MHz Span
-
85
-
dBc
f
CLK
= 20 MSPS, f
OUT
= 5.055MHz, 2MHz Span
-
77
-
dBc
f
CLK
= 40 MSPS, f
OUT
= 16MHz, 10MHz Span
-
75
-
dBc
f
CLK
= 50 MSPS, f
OUT
= 10.1MHz, 2MHz Span
-
80
-
dBc
f
CLK
= 80 MSPS, f
OUT
= 5.1MHz, 2MHz Span
-
78
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 10.1MHz, 2MHz Span
-
79
-
dBc
Spurious Free Dynamic Range to Nyquist
(Note 3)
f
CLK
= 40 MSPS, f
OUT
= 2.02MHz, 20MHz Span
-
70
-
dBc
f
CLK
= 80 MSPS, f
OUT
= 2.02MHz, 40MHz Span
-
70
-
dBc
f
CLK
= 100 MSPS, f
OUT
= 2.02MHz, 50MHz Span
-
69
-
dBc
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, V
REF
(Note 4)
-1.27
-1.23
-1.17
V
Internal Reference Voltage Drift
(Note 3)
-
175
-
V/
o
C
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-125
-
+50
A
HI5731
3-4
Internal Reference Load Regulation
I
REF
= 0 to I
REF
= -125
A
-
50
-
V
Input Impedance at REF OUT pin
(Note 3)
-
1.4
-
k
Amplifier Large Signal Bandwidth (0.6V
P-P
)
Sine Wave Input, to Slew Rate Limited (Note 3)
-
3
-
MHz
Amplifier Small Signal Bandwidth (0.1V
P-P
)
Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
Reference Input Impedance
(Note 3)
-
12
-
k
Reference Input Multiplying Bandwidth (CTL IN)
R
L
= 50
, 100mV Sine Wave, to -3dB Loss at I
OUT
(Note 3)
-
200
-
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
IH
(Note 4)
2.0
-
-
V
Input Logic Low Voltage, V
IL
(Note 4)
-
-
0.8
V
Input Logic Current, I
IH
(Note 4)
-
-
400
A
Input Logic Current, I
IL
(Note 4)
-
-
700
A
Digital Input Capacitance, C
IN
(Note 3)
-
3.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, t
SU
See Figure 1 (Note 3)
3.0
2.0
-
ns
Data Hold Time, t
HLD
See Figure 1 (Note 3)
0.5
0.25
-
ns
Propagation Delay Time, t
PD
See Figure 1 (Note 3)
-
4.5
-
ns
CLK Pulse Width, t
PW1
, t
PW2
See Figure 1 (Note 3)
3.0
-
-
ns
POWER SUPPLY CHARACTERISTICS
I
EEA
(Note 4)
-
42
50
mA
I
EED
(Note 4)
-
70
85
mA
I
CCD
(Note 4)
-
13
20
mA
Power Dissipation
(Note 4)
-
650
-
mW
Power Supply Rejection Ratio
V
CC
5%, V
EE
5%
-
5
-
A/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25
o
C. 100% production tested at temperature extremes for military temperature devices, sample tested for
industrial temperature devices.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
Timing Diagrams
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
Electrical Specifications
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal
T
A
= 25
o
C for All Typical Values (Continued)
PARAMETER
TEST CONDITIONS
HI5731BI
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
CLK
D11-D0
I
OUT
50%
t
SETT
1
/
2
LSB ERROR BAND
t
PD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA =
1
/
2
(H x W)
HI5731
3-5
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Typical Performance Curves
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
Timing Diagrams
(Continued)
CLK
D11-D0
I
OUT
50%
t
PW1
t
PW2
t
SU
t
HLD
t
SU
t
SU
t
PD
t
PD
t
PD
t
HLD
t
HLD
-50
-30
-10
10
30
50
70
90
560
600
640
680
TEMPERATURE
(mW)
CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
-50
-30
-10
10
30
50
70
90
-1.29
-1.27
-1.25
-1.23
-1.21
TEMPERATURE
(V)
HI5731
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