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Features
Floating channel designed for bootstrap operation
Fully operational to 200V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground 5V offset
CMOS Schmitt-triggered inputs with pull-down
Shut down input turns off both channels
Matched propagation delay for both channels
Outputs in phase with inputs
Also available LEAD-FREE
Packages
HIGH AND LOW SIDE DRIVER
Product Summary
V
OFFSET
200V max.
I
O
+/-
3.0A / 3.0A typ.
V
OUT
10 - 20V
t
on/off
95 & 65 ns typ.
Delay Matching
15 ns max.
Description
The IR2010 is a high power, high voltage, high speed power MOSFET and IGBT
drivers with independent high and low side referenced output channels, ideal for Audio
Class D and DC-DC converter applications. Logic inputs are compatible with standard
CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse
current buffer stage designed for minimum driver cross-conduction. Propagation de-
lays are matched to simplify use in high frequency applications. The floating channel
can be used to drive an N-channel power MOSFET or IGBT in the high side configura-
tion which operates up to 200 volts. Proprietary HVIC and latch immune CMOS tech-
nologies enable ruggedized monolithic construction.
IR2010(
S
) & (PbF)
14-Lead PDIP
16-Lead SOIC
www.irf.com
1
Typical Connection
HIN
200V
TO
LOAD
V
DD
V
B
V
S
HO
LO
COM
HIN
LIN
V
SS
SD
V
CC
LIN
V
DD
SD
V
SS
V
CC
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
Data Sheet No. PD60195-D
Applications
Audio Class D amplifiers
High power DC-DC SMPS converters
Other high frequency applications
2
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IR2010(
S
) & (PbF)
(Please refer to the Design Tip DT97-3 for more details).
Note 1: Logic operational for V
S
of -4 to +200V. Logic state held for V
S
of -4V to -V
BS
.
Note 2: When V
DD
< 5V, the minimum V
SS
offset is limited to -V
DD.
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply absolute voltage
V
S
+ 10
V
S
+ 20
V
S
High side floating supply offset voltage
Note 1
200
V
HO
High side floating output voltage
V
S
V
B
V
CC
Low side fixed supply voltage
10
20
V
LO
Low side output voltage
0
V
CC
V
DD
Logic supply voltage
V
SS
+ 3
V
SS
+ 20
V
SS
Logic supply offset voltage
-5 (Note 2)
5
V
IN
Logic input voltage (HIN, LIN & SD)
V
SS
V
DD
T
A
Ambient temperature
-40
125
C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 24 and 25.
V
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply voltage
-0.3
225
V
S
High side floating supply offset voltage
V
B
- 25
V
B
+ 0.3
V
HO
High side floating output voltage
V
S
- 0.3
V
B
+ 0.3
V
CC
Low side fixed supply voltage
-0.3
25
V
LO
Low side output voltage
-0.3
V
CC
+ 0.3
V
DD
Logic supply voltage
-0.3
V
SS
+ 25
V
SS
Logic supply offset voltage
V
CC
- 25
V
CC
+ 0.3
V
IN
Logic input voltage (HIN, LIN & SD)
V
SS
- 0.3
V
DD
+ 0.3
dV
s
/dt
Allowable offset supply voltage transient (figure 2)
--
50
V/ns
P
D
Package power dissipation @ T
A
+25
C
(14 lead DIP)
--
1.6
(16 lead SOIC)
--
1.25
R
THJA
Thermal resistance, junction to ambient
(14 lead DIP)
--
75
(16 lead SOIC)
--
100
T
J
Junction temperature
--
150
T
S
Storage temperature
-55
150
T
L
Lead temperature (soldering, 10 seconds)
--
300
C/W
W
V
C
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3
IR2010(
S
) & (PbF)
Symbol
Definition
Figure Min.
Typ. Max. Units Test Conditions
t
on
Turn-on propagation delay
7
50
95
135
V
S
= 0V
t
off
Turn-off propagation delay
8
30
65
105
V
S
= 200V
t
sd
Shutdown propagation delay
9
35
70
105
V
S
= 200V
t
r
Turn-on rise time
10
--
10
20
t
f
Turn-off fall time
11
--
15
25
MT
Delay matching, HS & LS turn-on/off
6
--
--
15
ns
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, C
L
= 1000 pF, T
A
= 25
C and V
SS
= COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
Definition
Figure Min.
Typ. Max. Units Test Conditions
V
IH
Logic "1" input voltage
12
9.5
--
--
V
IL
Logic "0" input voltage
13
--
--
6.0
V
IH
Logic "1" input voltage
12
2
--
--
V
IL
Logic "0" input voltage
13
--
--
1
V
OH
High level output voltage, V
BIAS
- V
O
14
--
--
1.0
I
O
= 0A
V
OL
Low level output voltage, V
O
15
--
--
0.1
I
O
= 0A
I
LK
Offset supply leakage current
16
--
--
50
V
B
=V
S
= 200V
I
QBS
Quiescent V
BS
supply current
17
--
70
210
V
IN
= 0V or V
DD
I
QCC
Quiescent V
CC
supply current
18
--
100
230
V
IN
= 0V or V
DD
I
QDD
Quiescent V
DD
supply current
19
--
1
5
V
IN
= 0V or V
DD
I
IN+
Logic "1" input bias current
20
--
20
40
V
IN
= V
DD
I
IN-
Logic "0" input bias current
21
--
--
1.0
V
IN
= 0V
V
BSUV+
V
BS
supply undervoltage positive going
22
7.5
8.6
9.7
threshold
V
BSUV-
V
BS
supply undervoltage negative going
23
7.0
8.2
9.4
threshold
V
CCUV+
V
CC
supply undervoltage positive going
24
7.5
8.6
9.7
threshold
V
CCUV-
V
CC
supply undervoltage negative going
25
7.0
8.2
9.4
threshold
I
O+
Output high short circuit pulsed current
26
2.5
3.0
--
V
O
= 0V, V
IN
= V
DD
PW
10
s
I
O-
Output low short circuit pulsed current
27
2.5
3.0
--
V
O
= 15V, V
IN
= 0V
PW
10
s
V
A
V
A
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15V, T
A
= 25
C and V
SS
= COM
unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters
are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN and SD. The V
O
and I
O
parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
V
DD
= 15V
V
DD
= 3.3V
4
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IR2010(
S
) & (PbF)
Functional Block Diagram
Lead Definitions
Symbol Description
14 Lead PDIP
16 Lead SOIC (Wide Body)
IR2010
IR2010S
Part Number
Lead Assignments
V
DD
Logic supply
HIN
Logic input for high side gate driver output (HO), in phase
SD
Logic input for shutdown
LIN
Logic input for low side gate driver output (LO), in phase
V
SS
Logic ground
V
B
High side floating supply
HO
High side gate drive output
V
S
High side floating supply return
V
CC
Low side supply
LO
Low side gate drive output
COM
Low side return
V
B
SD
LIN
V
DD
V
SS
UV
DETECT
DELAY
V
CC
UV
DETECT
LO
V
S
COM
S
R
UV
Q
HIN
HO
LEVEL
SHIFT
CIRCUIT
V
SS
/COM
LEVEL
SHIFT
LEVEL
SHIFT
V
SS
/COM
www.irf.com
5
IR2010(
S
) & (PbF)
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Waveform Definition
Figure 6. Delay Matching Waveform Definitions
Figure 5. Shutdown Waveform Definitions
HIN
LIN
tr
ton
tf
toff
HO
LO
50%
50%
90%
90%
10%
10%
HIN
LIN
HO
50%
50%
10%
LO
90%
MT
HO
LO
MT
(0 to 200V)
HIN
LIN
SD
HO
LO
SD
tsd
HO
LO
50%
90%
HV =10 to 200V
<50 V/ns
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