Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. A
05/01/03
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS71V16F32GST04
IS71V16F32GSB04
3.0 Volt-Only Flash & SRAM COMBO with
Stacked Multi-Chip Package (MCP)
-- 32 Mbit Simultaneous Operation Flash
Memory (x16) and 4 Mbit Static RAM (x16)
MAY 2003
MCP FEATURES
Power supply voltage 2.7V to 3.3V
High performance:
Flash: 70ns maximum access time
SRAM: 70ns maximum access time
Packages: 59-ball BGA or 56-ball BGA
Operating Temperature: -30C to +85C
FLASH FEATURES
Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum
Read Current at 5 Mhz:18 mA maximum
Sleep Mode: 5
A maximum
User Configurable Banks
- Bank A : 4 Mbit (8KB x 8 and 64KB x 7)
- Bank B : 12 Mbit (64KB x 24)
- Bank C : 12 Mbit (64KB x 24)
- Bank D : 4 Mbit (64KB x 8 )
User chooses two virtual banks from a combination
of four physical banks
Simultaneous R/W Operations (dual virtual bank):
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
Sector Erase Architecture:
8 sectors of 4K words each and 63 sectors of 32K words
each in Word mode. Any combination of sectors, or
the entire flash can be simultaneously erased
Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
Program Algorithms:
Automatically writes and verifies data at specified
address
Top or Bottom Boot
Hidden ROM Region:
256 byte with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
Data Polling and Toggle Bit:
Allow for detection of program or erase cycle comple-
tion
Ready-Busy output (RY/
BY
)
Detection of program or erase cycle completion
Over 100,000 write/erase cycles
Low supply voltage (Vccf
2.5V) inhibits writes
WP
/ACC input pin:
If V
IL
, allows partial protection of boot sectors
If V
IH
, allows removal of boot sector protection
If Vacc, program time is improved
SRAM FEATURES (4 Mb density)
Power Dissipation:
Operating: 40 mA maximum
Standby: 10 A maximum
Chip Selects:
CE1
s, CE2s
Power down feature using
CE1s
, or CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control:
LB
s (DQ0DQ7),
UB
s
(DQ8DQ15)
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
05/01/03
IS71V16F32GST04
IS71V16F32GSB04
ISSI
GENERAL DESCRIPTION
The flash and SRAM MCP is a 32 Mbit Flash/4 Mbit SRAM with shared data, address, and control pins. The 32 Mbit flash
is composed of 2,097,152 words of 16 bits. The 4Mb SRAM has 262,144 words of 16 bits. Data lines DQ0-DQ15 handle
the 16-bit word access for both the SRAM and Flash memories. Optionally,
UB
s or
LB
s control pins allow single byte
accesses with the SRAM.
The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer.
The 32 Mbit flash/4 Mbit SRAM is offered in 56-ball or 59-ball package. The flash is compatible with the JEDEC Flash
command set standard. The flash access time is 70ns, and the SRAM access time is 70ns.
The Flash architecture is composed of two virtual banks which allows simultaneous operation on each. Optimized
performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read
from the other bank. Both operations would then be operating simultaneously, with zero latency.
MCP BLOCK DIAGRAM
GND
GND
V
CCf
RY/
BY
4-MBIT
Static RAM
32-MBIT
Flash Memory
DQ0-DQ15
A0-A20
WP
/ACC
RESET
CE
f
I/Of
LB
s
UB
s
WE
OE
CE1
s
CE2s
DQ0-DQ15
A0-A17
V
CCS
A0-A20
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
05/01/03
IS71V16F32GST04
IS71V16F32GSB04
ISSI
PIN DESCRIPTIONS
A17-A0
Address Inputs, Common
A20-A18
Address Inputs, Flash
DQ15-DQ0
Data Inputs/Outputs, Common
RESET
Reset
CE1
s, CE2s
Chip Enable, SRAM
CE
f
Chip Enable, Flash
OE
Output Enable, Common
WE
Write Enable, Common
PIN CONFIGURATION (32 Mb Flash and 4 Mb SRAM)
PACKAGE CODE: B 59 BALL FBGA (Top View) (7.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
LB
s
Lower-byte Control, SRAM
UB
s
Upper-byte Control, SRAM
WP
/ACC
Write Protect/Acceleration Pin, Flash
RY/
BY
Ready/Busy Output (Flash)
Open Drain Output
Vccf
Power, Flash
Vccs
Power, SRAM
GND
Ground, Common
A
C
E
F
G
H
J
K
B
NC
NC
WP
/ACC
A7
LB
WE
A8
A11
DQ8 DQ2
DQ11
NC DQ5 DQ14
RY/
BY
A2
A5
A18
A20
A9
A13 NC
A1
A17
A10 A14 NC
CE
f
OE
DQ9
DQ3
DQ4 DQ13DQ15 NC
A0 GND DQ1
DQ6 NC A16
CE1
s DQ0 DQ10
Vccf
Vccs DQ12 DQ7 GND
D
UB
A3
A6
CE2s
RESET
A19 A12 A15
A4
NC
1
2
3
4
5
6
7
8
Shared
SRAM Only
Flash Only
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. A
05/01/03
IS71V16F32GST04
IS71V16F32GSB04
ISSI
PIN DESCRIPTIONS
A17-A0
Address Inputs, Common
A20-A18
Address Inputs, Flash
DQ15-DQ0
Data Inputs/Outputs, Common
RESET
Reset
CE1
s, CE2s
Chip Enable, SRAM
CE
f
Chip Enable, Flash
OE
Output Enable, Common
WE
Write Enable, Common
PIN CONFIGURATION (32 Mb Flash and 4 Mb SRAM)
PACKAGE CODE: M 56 BALL FBGA (Top View) (7.00 mm x 9.00 mm Body, 0.8 mm Ball Pitch)
LB
s
Lower-byte Control, SRAM
UB
s
Upper-byte Control, SRAM
WP
/ACC
Write Protect/Acceleration Pin, Flash
RY/
BY
Ready/Busy Output (Flash)
Open Drain Output
Vccf
Power, Flash
Vccs
Power, SRAM
GND
Ground, Common
A
C
E
F
G
H
B
WP
/ACC
A7
LB
WE
A8
A11
DQ8 DQ2
DQ11
NC DQ5 DQ14
RY/
BY
A2
A5
A18
A20
A9
A13 NC
A1
A17
A10 A14 NC
CE
f
OE
DQ9
DQ3
DQ4 DQ13DQ15 NC
A0 GND DQ1
DQ6 NC A16
CE1
s DQ0 DQ10
Vccf
Vccs DQ12 DQ7 GND
D
UB
A3
A6
CE2s
RESET
A19 A12 A15
A4
1
2
3
4
5
6
7
8
Shared
SRAM Only
Flash Only
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