General Description
The MAX9492 frequency synthesizer is designed to
generate multiple clocks for clock distribution in net-
work routers or switches. The device provides a total of
six buffered clock outputs (CLK1 to CLK6). CLK1 is the
buffered output of the reference clock. CLK2 through
CLK6 are independently programmable to generate
eight different frequencies based on a 25MHz input
crystal: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All
the outputs are LVCMOS single-ended signals. Either a
25MHz crystal or an external clock can serve as the
input reference clock. The MAX9492 incorporates two
phase-locked loops (PLLs) with two internal loop filters.
Select the MAX9492's output clock frequency by pro-
gramming on-chip registers through the MAX9492's
I
2
C* interface. The device also features spread-spec-
trum capability to reduce electromagnetic interference
(EMI). This technique allows spreading the fundamental
energy over a wider frequency range, hence reducing
the respective energy amplitude. The output frequency
spectrum is downspread by -1.25% or -2.5%.
The MAX9492 operates from a 3.3V supply and is guar-
anteed over the extended temperature range (-40C to
+85C). The device is available in a space-saving,
20-pin, TQFN, 5mm x 5mm package.
Applications
Network Routers
Telecom/Networking Equipment
Storage Area Networks/Network Attached
Storage
Features
o Five LVCMOS Outputs with Independent
Frequency Selections
o One Buffered Reference Clock Output
o Eight Selectable Frequencies: 133, 125, 83, 66,
62.5, 50, 33, and 25MHz
o Crystal or an Input-Clock-Based Clock Reference
o Output Frequency Programmed Through I
2
C
Interface
o 0, -1.25%, or -2.5% Selectable Downspreading
Rate
o Low Output Period Jitter
(Without Spread Spectrum) < 10ps
RMS
o <220ps Output-to-Output Skew
o Available in 20-Lead, 5mm x 5mm, TQFN Package
o +3.3V Supply
o -40C to +85C Extended Temperature Range
MAX9492
Multiple-Output Clock Generator
with Spread Spectrum
________________________________________________________________ Maxim Integrated Products
1
Ordering Information
19-3683; Rev 0; 5/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX9492ETP -40C to +85C
20 Thi n QFN- E P **
5m m x 5m m x
0.8m m
T2055-3
Typical Operating Circuit and Pin Configuration appear at
end of data sheet.
*Purchase of I
2
C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
license under the Philips I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C
Standard Specification as defined by Philips.
**EP = Exposed pad.
MAX9492
Multiple-Output Clock Generator
with Spread Spectrum
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DDA
= +3.0V to +3.6V, T
A
= -40C to +85C, unless otherwise noted. Typical values at V
DD
= V
DDA
= +3.3V, T
A
= +25C,
with CLK1 at 25MHz, and all other CLK_ outputs at 133MHz.) (Note 1)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD_
to GND .........................................................-0.3V to +4.0V
All Other Pins to GND.................................-0.3V to (V
DD
+ 1.0V)
Short-Circuit Duration (all LVCMOS outputs) .............Continuous
ESD Protection (Human Body Model)................................. 2kV
Continuous Power Dissipation (T
A
= +70C)
20-Pin TQFN (derate 20.8mW/C above +70C) ......1667mW
Storage Temperature Range .............................-65C to +165C
Maximum Junction Temperature .....................................+150C
Operating Temperature Range ...........................-40C to +85C
Lead Temperature (soldering, 10s) ................................+300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (X1)
Input High Level
V
IH1
2.0
V
Input Low Level
V
IL1
0.8
V
Input Current
I
IL1
, I
IH1
V
X
_ = 0 to V
DD
-20
+20
A
CLOCK OUTPUTS (CLK_)
I
OH
= -100A
V
DD
-
0.2
Output High Level
V
OH
I
OH
= -4mA
2.4
V
I
OL
= 100A
0.2
Output Low Level
V
OL
I
OL
= 4mA
0.4
V
Output Short-Circuit Current
I
OS
CLK_ = V
DD
or GND
-60
+69
mA
Output Capacitance
C
O
(Note 2)
5
pF
THREE-LEVEL INPUTS (SSC, SA0, SA1)
Input High Level
V
IH2
2.5
V
Input Low Level
V
IL2
0.8
V
Input Open Level
V
IO2
1.35
1.90
V
Input Current
I
IL2
, I
IH2
V
IL2
= 0 or V
IH2
= V
DD
-15
+15
A
SERIAL INTERFACE (SCL, SDA) (Note 3)
Input High Level
V
IH
0.7 x
V
DD
V
Input Low Level
V
IL
0.3 x
V
DD
V
Input Leakage Current
I
IH
, I
IL
-1
+1
A
Low-Level Output
V
OL
I
SINK
= 4mA
0.4
V
Input Capacitance
Ci
(Note 2)
10
pF
POWER SUPPLIES
Digital Power-Supply Voltage
V
DD
3.0
3.6
V
Analog Power-Supply Voltage
V
DDA
3.0
3.6
V
Total Supply Current
I
DC
C
L
= 10pF
60
76
mA
Output Disabled Supply Current
I
OD
All clock registers = 0x0F
18
24
mA
MAX9492
Multiple-Output Clock Generator
with Spread Spectrum
_______________________________________________________________________________________
3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS (CLK_)
Crystal Frequency
10
35
MHz
Input Frequency Range
External clock
15
35
MHz
Crystal Frequency Tolerance
f
A
-50
+50
ppm
Output-to-Output Skew
t
SKO
Any two CLK_ outputs
220
ps
Rise Time
t
R1
20% V
DD
to 80% V
DD
1.9
2.5
ns
Fall Time
t
F1
80% V
DD
to 20% V
DD
1.3
2.5
ns
Duty Cycle
40
60
%
Output Period Jitter
J
P
RMS (SSC = 0), CLK1 is disabled to high
impedance
10
15
ps
Power-Up Time
t
PO
V
DD
> 2.8V to PLL lock
2
ms
SSC = high
-2.5
Frequency Spread
SSC = floating
-1.25
%
AC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DDA
= +3.0V to +3.6V, C
L
= 10pF, unless otherwise noted. Typical values at V
DD
= V
DDA
= +3.3V, T
A
= +25C, with CLK1 at
25MHz and all other CLK_ outputs at 133MHz.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock
f
SCL
400
kHz
Bus Free Time Between STOP
and START Conditions
t
BUF
1.3
s
Hold Time, Repeated START
Condition
t
HD,STA
0.6
s
Repeated START Condition
Setup Time
t
SU,STA
0.6
s
STOP Condition Setup Time
t
SU,STO
0.6
s
Data Hold Time
t
HD,DAT
(Note 4)
15
900
ns
Data Hold Time Slave
t
HD,DAT
(Note 4)
15
900
ns
Data Setup Time
t
SU,DAT
100
ns
SCL Clock Low Period
t
LOW
1.3
s
SCL Clock High Period
t
HIGH
0.7
s
Rise Time of SDA and SCL,
Receiving
t
R
(Notes 2, 5)
20 +
0.1C
B
300
ns
Fall Time of SDA and SCL,
Receiving
t
F
(Notes 2, 5)
20 +
0.1C
B
300
ns
SERIAL INTERFACE TIMING
(V
DD
= V
DDA
= +3.3V, T
A
= -40C to +85C.) (Note 1, Figure 1)
MAX9492
Multiple-Output Clock Generator
with Spread Spectrum
4
_______________________________________________________________________________________
Typical Operating Characteristics
(T
A
= +25C, unless otherwise noted.)
MAX9492 toc03
FALL TIME vs. TEMPERATURE
(ALL OUTPUTS SET TO 133MHz)
TEMPERATURE (
C)
FALL TIME (ns)
-40
-15
10
35
60
85
1.0
1.2
1.4
1.6
1.8
2.0
MAX9492 toc01
SUPPLY CURRENT vs. TEMPERATURE
(ALL OUTPUTS SET TO 133MHz)
TEMPERATURE (
C)
SUPPLY CURRENT (mA)
-40
-15
10
35
60
85
58.0
58.4
58.8
59.2
59.6
60.0
60.4
60.8
61.2
61.6
62.0
MAX9492 toc02
RISE TIME vs. TEMPERATURE
(ALL OUTPUTS SET TO 133MHz)
TEMPERATURE (
C)
RISE TIME (ns)
-40
-15
10
35
60
85
1.5
1.7
1.9
2.1
2.3
2.5
Note 1: All DC parameters tested at T
A
= +25C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: No high output level is specified but only the output resistance to the bus. For I
2
C, the high-level voltage is provided by
pullup resistors on the bus.
Note 4: The device provides a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge the unde-
fined region of SCL's falling edge.
Note 5: C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
DD
and 0.7 x V
DD
.
Note 6: Bus sink current is less than 6mA. C
B
is the total capacitance of one bus line in pF. t
R
and t
F
are measured between 0.3 x
V
DD
and 0.7 x V
DD
.
Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fall Time of SDA, Transmitting
t
F,TX
(Notes 2, 6)
20 +
0.1C
B
250
ns
Pulse Width of Spike Suppressed
t
SP
(Notes 2, 7)
0
50
ns
Capacitive Load for Each Bus
Line
C
B
(Note 2)
400
pF
SERIAL INTERFACE TIMING (continued)
(V
DD
= V
DDA
= +3.3V, T
A
= -40C to +85C.) (Note 1, Figure 1)
MAX9492
Multiple-Output Clock Generator
with Spread Spectrum
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(T
A
= +25C, unless otherwise noted.)
133MHz OUTPUT WITH
0% AND 1.25% DOWNSPREADING
MAX9492 toc10
10dB/REF 0dBm
RBW = 100kHz
VBW = 1kHz
ATN = 20dB
CENTER = 133MHz
SPAN = 15MHz
133MHz OUTPUT WITH
0% AND 2.5% DOWNSPREADING
MAX9492 toc11
10dB/REF 0dBm
RBW = 100kHz
VBW = 1kHz
ATN = 20dB
CENTER = 133MHz
SPAN = 15MHz
PERIOD JITTER vs. TEMPERATURE
MAX9492 toc04
TEMPERATURE (
C)
PERIOD JITTER (ps
RMS
)
60
35
10
-15
4
8
12
16
20
0
-40
85
133MHz
33.3MHz
62.5MHz
125MHz
133MHz OUTPUT WAVEFORM
MAX9492 toc05
3.3V
0V
2ns/div
83MHz OUTPUT WAVEFORM
MAX9492 toc06
3.3V
0V
2ns/div
DUTY CYCLE vs. TEMPERATURE
MAX9492 toc07
TEMPERATURE (
C)
DUTY CYCLE (%)
60
35
-15
10
47.5
48.0
48.5
49.0
49.5
50.0
50.5
51.0
47.0
-40
85
133MHz
33.3MHz
62.5MHz
125MHz
133MHz OUTPUT 0% DOWNSPREADING
MAX9492 toc09
10dB/REF 0dBm
RBW = 10kHz
VBW = 10kHz
ATN = 20dB
CENTER = 133MHz
SPAN = 4MHz
MAX9492 toc08
PERIOD JITTER vs. FREQUENCY
FREQUENCY (MHz)
PERIOD JITTER (ps
RMS
)
25
50
75
100
125
150
0
4
8
12
16
20
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