PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef80d04a5a
SDF18C64x72G_C.fm - Rev. C 8/03 EN

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

SYNCHRONOUS
DRAM MODULE

MT18LSDF6472G 512MB

For the latest data sheet, please refer to the Micron

Web

site: www.micron.com/datasheets

Features

· 168-pin, dual in-line memory module (DIMM)
· PC133- and PC100-compliant
· Registered inputs with one-clock delay
· Utilizes 100 MHz and 133 MHz SDRAM devices
· Phase-lock loop (PLL) clock driver to reduce loading
· ECC-optimized pinout
· 512MB (64 Meg x 72)
· Single +3.3V ±0.3V power supply
· Fully synchronous; all signals registered on positive

edge of PLL clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal SDRAM banks for hiding row access/

precharge

· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge and Auto Refresh Modes
· Self Refresh Mode
· 64ms refresh: 8,192 cycles
· LVTTL-compatible inputs and outputs
· Serial Presence-Detect (SPD)
· Gold edge contacts

NOTE:

1. Module latency; registered mode adds one clock

cycle to CL.

Figure 1: 168-Pin DIMM (MO-161)

NOTE:

The designators for component and PCB revision are
the last two characters of each part number. Consult
factory for current revision codes. Example:
MT18LSDF6472G-133B1.

OPTIONS

MARKING

· Package

168-pin DIMM (Standard)

168-pin DIMM (Lead-free)

· Frequency/CAS Latency

133 MHz/CL = 2

-13E

133 MHz/CL = 3

-133

100 MHz/CL = 2

-10E

Table 1:

Device Timing

MODULE

MARKINGS

PC100

CL -

RCD -

PC133

CL -

RCD -

-13E

2 - 2 - 2

-133

2 - 2 - 2

3 - 3 - 3

-10E

2 - 2 - 2

Table 2:

Address Table

512MB

Refresh Count

Device Banks

4 (BA0, BA1)

Device Configuration

64 Meg x 4

Row Addressing

8K (A0A12)

Column Addressing

2K (A0A9, A11)

Module Ranks

1 (S0#, S2#)

Table 3:

Part Numbers

PART NUMBER

CONFIGURATION

SYSTEM BUS

SPEED

MT18LSDF6472G-13E__

64 Meg x 72

133 MHz

MT18LSDF6472G-133__

64 Meg x 72

133 MHz

MT18LSDF6472G-10E__

64 Meg x 72

100 MHz

Standard 1.05in. (26.67mm)

Low-Profile 0.90in. (22.86mm)

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Figure 2: 168-Pin DIMM Layout

Table 4:

Pin Assignment (168-Pin
DIMM Front

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

CB1

DQ0

DQ21

DQ1

S2#

DQ22

DQ2

DQMB2

DQ23

DQ3

DQMB3

WE#

DQ24

DQ4

DQMB0

DQ25

DQ5

DQMB1

DQ26

DQ6

S0#

DQ27

DQ7

CB2

DQ8

CB3

DQ28

DQ29

DQ9

DQ16

DQ30

DQ10

DQ17

DQ31

DQ11

DQ18

DQ12

DQ19

DQ13

A10

BA1

DQ20

DQ14

SDA

DQ15

SCL

CB0

CK0

Table 5:

Pin Assignment (168-Pin
DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

106

CB5

127

148

DQ32

107

128

CKE0

149

DQ53

DQ33

108

129

150

DQ54

DQ34

109

130 DQMB6

151

DQ55

DQ35

110

131 DQMB7 152

111

CAS#

132

153

DQ56

DQ36

112 DQMB4 133

154

DQ57

DQ37

113 DQMB5 134

155

DQ58

DQ38

114

135

156

DQ59

DQ39

115

RAS#

136

CB6

157

DQ40

116

137

CB7

158

DQ60

117

138

159

DQ61

DQ41

118

139

DQ48

160

DQ62

DQ42

119

140

DQ49

161

DQ63

DQ43

120

141

DQ50

162

100

DQ44

121

142

DQ51

163

101

DQ45

122

BA0

143

164

102

123

A11

144

DQ52

165

SA0

103

DQ46

124

145

166

SA1

104

DQ47

125

146

167

SA2

105

CB4

126

A12

147

REGE

168

U11

U10

U12

U13

U14

U15

U16

U17

U19

U20

U21

U22

U23

U24

PIN 1

PIN 41

PIN 84

PIN 85

PIN125

PIN 168

U11

U10

U12

U13

U14

U15

U16

U17

U19

U20

U21

U22

U23

U24

PIN 1

PIN 41

PIN 84

PIN 85

PIN125

PIN 168

Standard 1.05in. (26.67mm)

Low-Profile 0.90in. (22.86mm)

Indicates a V

or V

DDQ

Indicates a V

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Table 6:

Pin Descriptions

Pin numbers not listed in correct order; for more information, see Pin Assignment tables on page 2

PINS

SYMBOL

TYPE

DESCRIPTION

27, 111, 115

WE#, CAS#,

RAS#

Input

Command Inputs: WE#, CAS#, and RAS# (along with S#) define the
command being entered.

CK0

Input

Clock: CK is distributed through an on-board PLL to all devices.

128

CKE0

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
Deactivating the clock provides POWER-DOWN and SELF REFRESH
operation (all device banks idle) or CLOCK SUSPEND operation (burst
access in progress). CKE is synchronous except after the device enters
power-down and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including CKE, are
disabled during power-down and self refresh modes, providing low
standby power.

30, 45

S0#, S2#

Input

Chip Select: S# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when S# is registered
HIGH. S# is considered part of the command code.

28, 29, 46, 47, 112,

113, 130, 131

DQMB0

DQMB7

Input

Input/Output Mask: DQMB is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQMB is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH
during a READ cycle.

37, 122

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.

3338, 117121, 123,

126

A0A12

Input

Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands,
to select one location out of the memory array in the respective device
bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.

Input

Write Protect: Serial presence-detect hardware write protect.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.

166, 167, 168

SA0SA2

Input

Presence-Detect Address Inputs: These pins are used to configure the
presence-detect device.

147

REGE

Input

25, 711, 1317, 19,
20, 5558, 60, 6567,
6982, 7477, 8689,

9195, 97101, 103,

104, 139142, 144,
149151, 153156,

158161

DQ0DQ63

Input/

Output

Data I/Os: Data Bus

21, 22, 52, 53, 105,

106, 136, 137

CB0CB7

Input/

Output

ECC Check Bits.

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of
the module.

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Figure 3: Functional Block Diagram

SA0

SPD

SCL

SDA

SA1

SA2

RS0#

SDRAMs

12pF

CK1-CK3

PLL

SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
SDRAM x 2
REGISTER x 3

CK0

12pF

RDQMB4

DQM CS#

DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3

RDQMB0

DQM CS#

U24

DQ
DQ
DQ
DQ

DQ32
DQ33
DQ34
DQ35

DQM CS#

DQ
DQ
DQ
DQ

DQ4
DQ5
DQ6
DQ7

DQM CS#

U23

DQ
DQ
DQ
DQ

DQ36
DQ37
DQ38
DQ39

RDQMB5

DQM CS#

DQ
DQ
DQ
DQ

DQ8
DQ9
DQ10
DQ11

RDQMB1

DQM CS#

U22

DQ
DQ
DQ
DQ

DQ40
DQ41
DQ41
DQ43

DQM CS#

DQ
DQ
DQ
DQ

DQ12
DQ13
DQ14
DQ15

DQM CS#

U21

DQ
DQ
DQ
DQ

DQ44
DQ45
DQ46
DQ47

DQM CS#

U20

DQ
DQ
DQ
DQ

CB0
CB1
CB2
CB3

DQM

U16

DQ
DQ
DQ
DQ

CB4
CB5
CB6
CB7

RS2#

RDQMB6

DQM CS#

DQ
DQ
DQ
DQ

DQ16
DQ17
DQ18
DQ19

RDQMB2

DQM CS#

U15

DQ
DQ
DQ
DQ

DQ48
DQ49
DQ50
DQ51

DQM CS#

DQ
DQ
DQ
DQ

DQ20
DQ21
DQ22
DQ23

DQM CS#

U14

DQ
DQ
DQ
DQ

DQ52
DQ53
DQ54
DQ55

RDQMB7

DQM CS#

DQ
DQ
DQ
DQ

DQ24
DQ25
DQ26
DQ27

RDQMB3

DQM CS#

U13

U5, U6, U19

U18

U11

U17

DQ
DQ
DQ
DQ

DQ56
DQ57
DQ58
DQ59

DQM CS#

U10

DQ0
DQ1
DQ2
DQ3

DQ28
DQ29
DQ30
DQ31

DQM CS#

U12

DQ
DQ
DQ
DQ

DQ60
DQ61
DQ62
DQ63

RAS#

CAS#

CKE0

WE#

A0-A12

RRAS#: SDRAMs

RCAS#: SDRAMs

RCKE0: SDRAMs

RWE#: SDRAMs

RA0-RA12: SDRAMs

RBA0: SDRAMs

RBA1: SDRAMs

RS0#, RS2#

RDQMB0 - RDQMB7

BA0

BA1

S0#, S2#

DQMB0 - DQMB7

PLL CLK

R
E

S
T
E

REG

10K

CS#

NOTE:

1. All resistor values are 10

W unless otherwise specified.

DDR SDRAM = MT48LC64M4A2FB

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

General Description

The MT18LSDF6472G is a high-speed CMOS,

dynamic random-access, 512MB memory module
organized in a x72 (ECC) configuration. This module
uses internally configured quad-bank SDRAMs with a
synchronous interface (all signals are registered on the
positive edge of the clock signal).

Read and write accesses to SDRAM modules are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank; A0A12
select the device row). The address bits registered
coincident with the READ or WRITE command are
used to select the starting device column location for
the burst access.

SDRAM modules provide for programmable read or

write burst lengths of 1, 2, 4, or 8 locations, or full page,
with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.

SDRAM modules use an internal pipelined architec-

ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the device column
address to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one
device bank while accessing one of the other three
device banks will hide the PRECHARGE cycles and
provide seamless, high-speed, random-access opera-
tion.

SDRAM modules are designed to operate in +3.3V

±0.3V, low-power memory systems. An auto refresh
mode is provided, along with a power-saving, power-
down mode. All inputs and outputs are LVTTL-com-
patible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between device banks in order to hide precharge
time, and the capability to randomly change device
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM oper-
ation, refer to the 256Mb SDRAM component data
sheet.

PLL and Register Operation

This module can be operated in either registered

mode (REGE pin HIGH), where the control/address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the fol-
lowing rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin LOW) where the
input signals pass through the register/buffer to the
SDRAM devices on the same clock. A phase-lock loop
(PLL) on the modules is used to redrive the clock sig-
nals to the SDRAM devices to minimize system clock
loading (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated).

Serial Presence-Detect Operation

This module incorporates serial presence-detect

(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.

Device Description

In general, the 256Mb SDRAM component device

used for this modules is a quad-bank DRAM, that
operate at 3.3V and include a synchronous interface
(all signals are registered on the positive edge of the
clock signal, CK0). The four banks of a x4, 256Mb
device are each configured as 8,192 bit-rows, by 2,048
bit-columns, by 4 input/output bits.

Module Functional Description

Module read and write accesses are burst oriented;

accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ
or WRITE command. The address bits registered coin-
cident with the ACTIVE command are used to select
the device bank and row to be accessed. BA0 and BA1
select the device bank, A0A12, select the device row.

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

The address bits A0A9, A11 registered coincident with
the READ or WRITE command, are used to select the
starting device column location for the burst access.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, command descriptions and device opera-
tion.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V

and V

Q (simul-

taneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a
COMMAND INHIBIT or NOP. Starting at some point
during this 100µs period and continuing at least
through the end of this period, Command Inhibit or
NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All device banks must then be precharged, thereby
placing the device in the all banks idle state.

Once in the idle state, two AUTO refresh cycles must

be performed. After the AUTO refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM device. This defini-
tion includes the selection of a burst length, a burst
type, a CAS latency, an operating mode and a write
burst mode, as shown in the Mode Register Definition
Diagram. The mode register is programmed via the
LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the
device loses power.

Mode register bits M0M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. A12 (M12) is undefined, but should be driven
LOW during loading of mode register.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-

fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.

Figure 4: Mode Register Definition

Diagram

Reserved*

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

A11

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = "0, 0, 0"

to ensure compatibility

with future devices.

A12

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. For full-page accesses: y = 2,048.
2. For a burst length of two, A1A9, A11 select the block-

of-two burst; A0 selects the starting column within the
block.

3. For a burst length of four,A2A9, A11 select the block-

of-four burst; A0A1 select the starting column within
the block.

4. For a burst length of eight, A3A9, A11 select the block-

of-eight burst; A0A2 select the starting column within
the block.

5. For a full-page burst, the full row is selected and A0-A9,

A11 select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

7. For a burst length of one, A0A9, A11 select the unique

column to be accessed, and mode register bit M3 is
ignored.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Figure 7,
Burst Definition Table. The block is uniquely selected
by A1A9, A11 when the burst length is set to two; A2
A9, A11 when the burst length is set to four; and by A3
A9, A11 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is
reached, as shown in Figure 7, Burst Definition Table.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Figure 7, Burst
Definition Table.

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. DQ will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and pro-
vided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assum-
ing that the clock cycle time is such that all relevant
access times are met, if a read command is registered
at T0 and the latency is programmed to two clocks, DQ
will start driving after T1 and the data will be valid by
T2, as shown in Figure 5, CAS Latency Diagram. Table
8, CAS Latency Table, indicates the operating frequen-
cies at which each CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test

Table 7:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full Page

(y)

n= A0-A9

(location 0-y)

Cn, Cn+1, Cn+2

Cn+3, Cn+4...

...Cn-1, Cn...

Not Supported

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

modes. The programmed burst length applies to both
read and write bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with
future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0

M2 applies to both read and write bursts; when M9 = 1,
the programmed burst length applies to read bursts,
but write accesses are single-location (nonburst)
accesses.

Figure 5: CAS Latency Diagram

Table 8:

CAS Latency Table

Registered mode adds one clock cycle to CL

SPEED

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHz)

CAS LATENCY = 2

CAS LATENCY = 3

-13E

£ 133

£ 143

-133

£ 100

£ 133

-10E

£ 100

N/A

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Commands

Table 9, SDRAM Commands and DQMB Operation

Truth Table, provides a quick reference of available
commands. This is followed by written description of
each command. For a more detailed description of

commands and operations, refer to the 256Mb SDRAM
component data sheet.

NOTE:

1. A0A12 provide row address; BA0BA1 determine which device bank is made active.
2. A0A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW dis-

ables the auto-precharge feature; BA0BA1 determine which device bank is being read from or written to.

3. A10 LOW: BA0BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and

BA0, BA1 are "Don't Care."

4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
6. A0A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates DQ during WRITEs (zero-clock delay) and READs (two-clock delay).

Table 9:

SDRAM Commands and DQMB Operation Truth Table

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION)

CS# RAS# CAS#

WE#

DQMB

ADDR

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/

Row

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE
burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)

4, 5

LOAD MODE REGISTER

Op-code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

, V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs NC or I/O Pins

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature

(Commercial) . . . . . . . . . . . . . . . . .. 0°C to +55°C

Storage Temperature (plastic) . . . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 18W

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1, 5, 6; notes appear on page 14; V

, V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

, V

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

£ VIN £ V

(All other pins not under test = 0V)

Command and
Address Inputs,
CK, CKE

-10

µA

DQ, DQMB

-5

OUTPUT LEAKAGE CURRENT: DQ pins are disabled;
0V

£ V

OUT

£ V

-10

µA

OUTPUT LEVELS: Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4

0.4

Table 11: I

Specifications and Conditions

Notes: 1, 5, 6, 11, 13; notes appear on page 14; V

, V

Q = +3.3V ±0.3V; SDRAM component values only

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133 -10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;

RC =

RC (MIN)

2,430 2,250 2,250

3, 18, 19, 30

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode;CKE = HIGH; CS# = HIGH; All

device banks active after

RCD met; No accesses in progress

720

3, 12, 19, 30

OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active

2,430 2,430 2,430

3, 18, 19, 30

AUTO REFRESH CURRENT

RC =

RFC (MIN)

5,130 4,860 4,860

3, 12

CKE = HIGH; CS# = HIGH

RFC = 7.8125µs

18, 19, 30, 31

SELF REFRESH CURRENT: CKE

£ 0.2V

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Table 12: Capacitance

Note 2; notes appear on page 14

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#, CKE

Input Capacitance: S#, DQMB

Input Capacitance: CK0

Input Capacitance: SCL, SA, SDA

Input Capacitance: CK

Input Capacitance: REGE

1.5

Input/Output Capacitance: DQ, CB

Table 13: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11; notes appear on page 14
Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters

ACCHARACTERISTICS

-13E

-133

-10E

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Access timefrom CLK (pos.edge)

CL= 3

AC(3)

5.4

CL= 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL= 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE holdt ime

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (noload)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192 rows)

REF

AUTOREFRESH period

RFC

PRECHARGE command period

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

ACTIVE bank a to ACTIVE bank b
command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK

7ns

7.5ns

7ns

Exit SELFREFRESH to ACTIVE command

XSR

Table 13: Electrical Characteristics and Recommended AC Operating Conditions

(Continued)

Notes: 5, 6, 8, 9, 11; notes appear on page 14

ACCHARACTERISTICS

-13E

-133

-10E

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Table 14: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11; notes appear on page 14

PARAMETER

SYMBOL

-13E

-133

-10E

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE
command

CL = 3

ROH(3)

CL = 2

ROH(2)

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Notes

1. All voltages referenced to V

2. This parameter is sampled. V

, V

Q = +3.3V; f =

1 MHz; T

= 25°C; pin under test biased at 1.4V.

3. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to in-

dicate cycle time at which proper operation over
the full temperature range is ensured (0°C

£ T

+55°C).

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be

repeated any time the

REF refresh requirement is

exceeded.

7. AC characteristics assume

T = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V,

with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V

(MAX) and V

(MIN) and no longer at the ISV crossover point.

12. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

13. I

specifications are tested after the device is

properly initialized.

14. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 10ns for -10E;

CK = 7.5ns for -133

and -13E.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

£ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

£ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-

ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7ns for -13E; 7.5ns for -133;

and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.

25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.

AC for -133/-13E at CL = 3 with no load is 4.6ns

and is guaranteed by design.

28. Parameter guaranteed by design.
29. For -13E, CL = 2 and

CK = 7.5ns; for -133, CL = 3

and

CK = 7.5ns; for -10E, CL = 2 and

CK = 10ns

30. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

31. Refer to device data sheet for timing waveforms.
32. The value of

RAS used in -13E speed grade mod-

ules is calculated from

RC -

RP.

33. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

50pF

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 6, Data Validity, and Figure 7, Defini-
tion of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 8, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 6: Data Validity

Figure 7: Definition of Start and Stop

Figure 8: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Figure 9: SPD EEPROM Timing Diagram

Table 15: EEPROM Device Select Code

The most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 16: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

Start, Device Select, RW = 1

Random Address Read

Start, Device Select, RW= 0, Address

RESTART, Device Select, RW= 1

Sequential Read

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

£ 16

START, Device Select, RW = 0

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge

of SDA.

2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains
HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 17: Serial Presence-Detect EEPROM DC Operating Conditions

= +3.3V ±0.3V; all voltages referenced to V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7 V

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

-10

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

-10

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V; All other inputs = V

or V

CCS

µA

POWER SUPPLY CURRENT:

Write

Read

Table 18: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.2

0.9

µs

Time the bus must be free before a new transition can start

BUF

1.3

µs

Data-out hold time

200

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

0.6

µs

Clock HIGH period

HIGH

0.6

µs

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

LOW

1.3

µs

SDA and SCL rise time

0.3

µs

SCL clock frequency

SCL

400

KHz

Data-in setup time

SU:DAT

100

Start condition setup time

SU:STA

0.6

µs

Stop condition setup time

SU:STO

0.6

µs

WRITE cycle time

WRC

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

Table 19: Serial Presence-Detect Matrix

"1"/"0": Serial data, "driven to HIGH"/"driven to LOW"; V

= +3.3V ±0.3V

BYTE

DESCRIPTION

ENTRY (VERSION)

MT18LSDF6472G

Number of Bytes Used by Micron

128

Total Number of SPD Memory Bytes

256

Memory Type

SDRAM

Number of Row Addresses

Number of Column Addresses

Number of Module Ranks

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

LVTTL

SDRAM Cycle Time,

CK (CAS Latency = 3)

7 (-13E)

7.5 (-133)

8 (-10E)

70
75
80

SDRAM Access from CLK,

AC (CAS Latency = 3)

5.4 (-13E/-133)

6 (-10E)

54
60

Module Configuration Type

ECC

Refresh Rate/Type

7.81µs/SELF

SDRAM Width (Primary SDRAM)

Error-checking SDRAM Data Width

Minimum Clock Delay from Back-to-Back Random Column

Addresses,

CCD

Burst Lengths Supported

1, 2, 4, 8, PAGE

Number of Banks on SDRAM Device

CAS Latencies Supported

2, 3

CS Latency

WE Latency

SDRAM Module Attributes

-10E, -133, -13E

SDRAM Device Attributes: General

SDRAM Cycle Time,

CK (CAS Latency = 2)

7.5 (-13E)

10 (-133/-10E)

SDRAM Access from CLK,

AC (CAS Latency = 2)

5.4 (-13E)

6 (-133/-10E)

54
60

SDRAM Cycle Time,

CK (CAS Latency = 1)

SDRAM Access from CLK,

AC (CAS Latency = 1)

Minimum Row Precharge Time,

15 (-13E)

20 (-133/-10E)

0F
14

Minimum Row Active to Row Active,

RRD

14 (-13E)
15 (-133)
20 (-10E)

0E
0F
14

Minimum RAS# to CAS# Delay,

RCD

15 (-13E)

20 (-133/-10E)

0F
14

Minimum RAS# Pulse Width,

RAS (See note 1)

45 (-13E)
44 (-133)
50 (-10E)

2C
32

Module Rank Density

512MB

Command and Address Setup Time,

AS,

CMS

1.5 (-13E/-133)

2 (-10E)

15
20

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SDF18C64x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. The value of

RAS used for -13E modules is calculated from

RC -

RP. Actual device specification value is 37ns.

Command and Address Hold Time,

AH,

CMH

0.8 (-13E/-133)

1 (-10E)

08
10

Data Signal Input Setup Time,

1.5 (-13E/-133)

2 (-10E)

15
20

Data Signal Input Hold Time,

0.8 (-13E/-133)

1 (-10E)

08
10

36-61

Reserved

SPD Revision

REV. 1.2

Checksum For Bytes 0-62

-13E
-133
-10E

3B
83

Manufacturer's JEDEC ID Code

MICRON

65-71

Manufacturer's JEDEC ID Code (Cont.)

Manufacturing Location

1 - 12

01 - 0C

73-90

Module Part Number (ASCII)

Variable Data

PCB Identification Code

1 - 9

01-09

Identification Code (Cont.)

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98

Module Serial Number

Variable Data

99-125

Manufacturer-Specific Data (RSVD)

126

System Frequency

100 MHz (-13E/ -133/-10E)

127

SDRAM Component & Clock Detail

Table 19: Serial Presence-Detect Matrix (Continued)

"1"/"0": Serial data, "driven to HIGH"/"driven to LOW"; V

= +3.3V ±0.3V

BYTE

DESCRIPTION

ENTRY (VERSION)

MT18LSDF6472G

512MB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80d04a5a

Micron Technology, Inc., reserves the right to change products or specifications without notice..

SDF18C64x72G_C.fm - Rev. C 8/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 11: Low-Profile 168-Pin DIMM Dimensions

NOTE:

All dimensions are in inches (millimeters);

or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete
power supply and temperature range for production

devices. Although considered final, these specifica-
tions are subject to change, as further product devel-
opment and data characterization sometimes occur.

BACK VIEW

FRONT VIEW

5.256 (133.50)
5.244 (133.20)

0.157 (3.99)

MAX

0.700 (17.78)

0.906 (23.01)

0.894(22.71)

PIN 1

0.250 (6.35)

4.550 (115.57)

0.050 (1.27)

0.040 (1.02)

0.039 (1.00)
R(2X)

PIN 84

0.118 (3.00)

0.079 (2.00) R

(2X)

0.118 (3.00)

(2X)

PIN 168

PIN 85

2.625 (66.68)

1.661 (42.18)

0.128 (3.25)

0.118 (3.00)

(2X)

0.054 (1.37)
0.046 (1.17)

U11

U10

U12

U13

U14

U15

U16

U17

U19

U20

U21

U22

U23

U24

MAX

MIN

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT18LSDF6472

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT18LSDF6472