COD0418X
0.25
m SIGMA-DELTA VOICE CODEC
1
GENERAL DESCRIPTION
The COD0418X is Sigma-Delta CODEC for speech and telephony applications. The product contains both digital
IIR/FIR filter and smoothing filter. The normal input and output channels have
/A law format with 38dB signal to
distortion ratio. The input and output of this device is compressed form(A-law,
-law) and 16bit linear which can
be easily determined by control select pins. and it has variable gain control block varies from -4dB to +58dB, 2dB
steps and input type of AFE is differential and there is another analog bypass mode single input port. An on-chip
voltage reference circuit is included to allow the single supply operation.
FEATURES
-- Single chip voice line Codec (A/D, D/A converter included)
-- Over-sampled Sigma Delta modulator/Demodulator
-- Input/output format: 8bit
-law/A-law and linear 16bit
* These three types are easily selectable by control pins
* When serial interface mode: 16bit linear
-- ADC gain block(AFE) range: -4dB to +58dB, 2dB step
-- DAC gain block rang: 0,2,3.5dB
-- Analog bypass mode for substitution of AFE
-- Sigma Delta ADC.
* 256X Over-sampling
* On chip Decimation Filter
* On chip Smoothing Filter
-- Sigma Delta DAC.
* 256X Over-sampling
* On chip 256X Interpolation Filter
* On chip Analog Post Filter
-- AFE has differential inputs, analog bypass mode has single and analog output is single.
-- Sampling Rate: 8kHz
-- On chip voltage reference circuitry
-- Single +2.5V Power Supply
-- 1.6Vpp Input/output signal swing but with signal distortion swings up to 2Vpp.
-- Power Consumption
* Operating Mode: 17mW Typ(2.5V)
* Power-down Mode: 125
W Typ(2.5V)
0.25
m SIGMA-DELTA VOICE CODEC
COD0418X
2
TYPICAL APPLICATIONS
-- Speech Processing
(Recognition, Synthesis, Compression etc.)
-- Telephony
-- Modem
FUNCTIONAL BLOCK DIAGRAM WITH INPUT/OUPUT APPLICATION
Bypass
Mode
Input
AFE
Mux
Analog
ҥ
Modulator
Decimation
Filter
Serial Interface
+ Offset Calibration
1. 16bit Linear PCM
2.
-law
3. A-law
Offset
Calibration
DAC
Analog
Post Filter
Digital
ҥ
Modulator
Interpolation
Filter
Reference
Generation
Blocks
AIG[4:0]
AIS[1:0]
DG[4:0]
+
-
+
-
+
-
AFETP
AFETN
VREFOUT
IREF
APOSTOUT
+
+
0.1uF
10uF
0.33uF Tantalum
Capacitor
0.33uF Tantalum
Capacitor
0.33uF Tantalum
Capacitor
SYNCSDECI[1:0]TDECI SINPO[1:0]TPOSTADLCS DALCSBCKDADSADHPBDAHPBAIG[4:0]AIS[4:0]DG[1:0]
SDOUT
SDIN
X256FS
RST
DAPWD
ADPWD
ALOOP
ADMUTE
DAMUTE
REFL
VSS25AD1
VDD25AD1
VSS25AA1
VDD25AA1
ADCPS
DACPS
COD0418X
0.25
m SIGMA-DELTA VOICE CODEC
3
CORE PIN DESCRIPTION
Name
I/O Type
I/O Pad
Pin Description
VDD25AA1
AP
vdd2t_abb
Analog Power (+2.5V): 10uF ceramic and 0.1uF tantalum capacitors
should be connected between VDD25AA1 and VSS25AA1 and
these two capacitors should be placed as close as possible to two
power pads. and the order of two capacitor is described in core
evaluation guide.
VSS25AA1
AG
vss2t_abb
Analog Ground (0.0V)
IREF
AO
poa_abb
Current Reference Output: this pin is for test, so normally this pin is
float.
REFL
AG
vss2t_abb
Analog Reference Ground (0.0V): for proper operation the end user
should supply clean ground level voltage to this pin but if there is no
other ground level source, end user can supply analog ground level
to this pin.
* Note: if there are not enough pins available, end user can connect
this pin to VASS25AA1, but in this case REFL should be connected
to "VASS25AA1 PAD"
AINP
AI
pia_abb
AFE Analog Positive input: this is positive analog input pin of
Analog Front End gain stage. and the input impedance of this pin is
20Kohm.
AINN
AI
pia_abb
AFE Analog Negative input: this is negative analog input pin of
Analog Front End gain stage. and the input impedance of this pin is
20Kohm.
NOTES:
1.
This pin descriptions are not fixed, but recommended.
2.
The Power pin(VDD25AA1,VDD25AD1) must be connected by DIODE_SLOT2.
3. The Ground pin (VSS25AA1, VSS25AD1) must be connected by DIODE_SLOT2.
4. SDECI[1:0], TDECI -> Decimation Filter Block test pin.
5.
SINPO[1:0], TPOST -> Post Filter Block test pin.
I/O TYPE ABBR.
-- AI: Analog Input
-- DI: Digital Input
-- AO: Analog Output
-- DO: Digital Output
-- AB: Analog Bi-directional
-- DB: Digital Bi-directional
-- AP: Analog Power
-- AG: Analog Ground
-- DP: Digital Power
-- DG: Digital Ground
0.25
m SIGMA-DELTA VOICE CODEC
COD0418X
4
CORE PIN DESCRIPTION (Cont'd)
Name
I/O Type
I/O Pad
Pin Description
AFETP
AO
poa_abb
AFE Positive Test Output: this is a test pin of AFE block and AFE
positive output, the detailed control of this test mode is described in
pin description of AIS[1:0]
AFETN
AO
poa_abb
AFE Negative Test Output: this is a test pin of AFE block and AFE
negative output, the detailed control of this test mode is described in
pin description of AIS[1:0]
DAMUTE
DI
picc_abb
DAC Analog Mute select (High active): when high state DAC mute
function activates
ADMUTE
DI
picc_abb
ADC Analog Mute select (High active): when high state ADC mute
function activates
ALOOP
DI
picc_abb
Analog loop back select (High active): test pin for internal analog
blocks only. and in normal operation, this is LOW state.
VREFOUT
AO
poa_abb
Vref output: voltage reference output of COD0418x and two
capacitors should be placed between VREFOUT and analog ground
level and one capacitor is 10uF and the other is 0.1uF and detailed
capacitor order is described in core evaluation guide and
input/output application guide.
ABIN
AI
pia_abb
Bypass Mode Analog Input: analog input of bypass mode and
detailed control of bypass mode is described in pin description of
AIS[1:0]
APOSTOUT
AO
poa_abb
DAC Analog output: the output load of APOSTOUT is 10Kohm and
maximum output of this is 1.6Vp-p but from the request of end user
the DAC gain has 3 steps, when 0dB=1.337Vpp, 2dB=1.683Vpp and
3.5dB=2.0Vpp and AC Electrical test of DAC will be performed at
0dB gain and 1.6Vpp input source for core performance test.
ADPWD
DI
picc_abb
ADC Power Down (High active): when high state ADC power down
activates
DAPWD
DI
picc_abb
DAC Power Down (High active): when high state DAC power down
activates
RST
DI
picc_abb
Digital Reset (High active)
X256FS
DI
picc_abb
256*Sampling Freq.(FS) Clock: main clock of COD0418x and it
should be 2.048MHz
SYNC
DI
picc_abb
Sampling Freq.(FS) Clock
SDECI[1:0]
DI
picc_abb
ADC Digital Filter input select: test pin for internal functional blocks,
and in normal operation these are LOW states.
TDECI
DI
picc_abb
ADC Digital Filter Test input: test pin for internal functional blocks,
and in normal operation, this is LOW state.
SINPO[1:0]
DI
picc_abb
DAC Post Filter input select: test pin for internal functional blocks,
and in normal operation these are LOW states.
COD0418X
0.25
m SIGMA-DELTA VOICE CODEC
5
CORE PIN DESCRIPTION (Cont'd)
Name
I/O Type
I/O Pad
Pin Description
SDIN
DI
picc_abb
Serial Data Input: The input of DAC
TPOST
DI
picc_abb
DAC Post Filter Test input: test pin for internal functional blocks,
and in normal operation, this is LOW state.
ADLCS
DI
picc_abb
ADC Linear/Command data select (Low/High): when low state ADC
Linear mode selected, and high ADC Command mode selected.
DALCS
DI
picc_abb
DAC Linear/Command data select (Low/High): when low state DAC
Linear mode selected, and high DAC Command mode selected.
ADCPS
DI
picc_abb
ADC
-law/A-law select (Low/High): when high state ADC A-law
mode selected, and low ADC
-law mode selected.
DACPS
DI
picc_abb
DAC
-law/A-law select (Low/High): when high state DAC A-law
mode selected, and low DAC
-law mode selected.
VSS25AD1
DG
vss2t_abb
Digital Ground (0.0V): 10uF ceramic and 0.1uF tantalum capacitors
should be connected between VDD25AD1 and VSS25AD1 and
these two capacitors should be placed as close as possible to two
power pads. and the order of two capacitors is described in core
evaluation guide.
VDD25AD1
DP
vdd2t_abb
Digital Power Supply (2.5V)
SDOUT
DO
pot2_abb
Serial Data Output: this is ADC output
BCK
DI
picc_abb
Bit Clock - Serial Interface Clock
DADS
DO
pot2_abb
DAC Modulator output: DAC sigma-delta modulator output and this
pin is for internal functional block test, and in normal operation, this
pin is floating state, but this should be muxed out for test.
ADHPB
DI
picc_abb
ADC High Pass Filter Enable (Low Active): this pin changes of lower
side of base-band frequency response. when high state COD0418X
core will transmit very low frequency component (from DC to
300Hz) but when low state, high pass filter function will be enabled,
so frequencies below 300Hz will be eliminated. this is only for ADC
path.
DAHPB
DI
picc_abb
DAC High Pass Filter Enable (Low Active) : this pin changes of
lower side of base-band frequency response. when high state
COD0418X core will receive very low frequency component (from
DC to 300Hz) but when low state, high pass filter function will be
enabled, so frequencies below 300Hz will be eliminated. this is only
for DAC path.
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