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Revision 0.0
KM68512B Family
CMOS SRAM
January 1998
1
Advance
Document Title
64Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No.
0.0
Remark
Advance
History
Initial draft
Draft Data
January 10th 1998
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you ha ve
any questions, please contact the SAMSUNG branch office near you.
Revision 0.0
KM68512B Family
CMOS SRAM
January 1998
2
Advance
64Kx8 bit Low Power CMOS Static RAM
The KM68512B family is fabricated by SAMSUNG
s advanced
CMOS process technology. The family support various operat-
ing temperature ranges and small package type for user flexi-
bility of system design. The family also support low data
retention voltage for battery back-up operation with low data
retention current.
GENERAL DESCRIPTION
FEATURES
Process Technology : 0.4
m CMOS
Organization : 64Kx8
Power Supply Voltage : Single 5V
10%
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 32-TSOP I -0820F
PIN DESCRIPTION
Name
Function
A
0
~A
15
Address Inputs
WE
Write Enable Input
CS
1
, CS
2
Chip Select Inputs
OE
Output Enable Input
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Power
Vss
Ground
N.C
No Connection
PRODUCT FAMILY
Product Family
Operating Temperature
V
CC
Range
Speed(ns)
Power Dissipation
PKG Type
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
KM68512BL-L
Commercial(0~70
C)
5V
0.5V
55/70
10
A
60mA
32-TSOP1-F
KM68512BLI-L
Industrial(-40~85
C)
70
15
A
FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A11
A9
A8
A13
WE
CS2
A15
NC
NC
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-TSOP
Type1 - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
Precharge circuit.
Memory array
512 rows
128
8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0
A1 A2
A3 A9
A11
A10
A4
A5
A6
A7
A8
A12
A14
I/O1
Data
cont
Data
cont
I/O8
A13
A15
CS
WE
OE
Control
logic
CS2
Revision 0.0
KM68512B Family
CMOS SRAM
January 1998
3
Advance
PRODUCT LIST
Commercial Temperature Product
(0~70
C)
Industrial Temperature Products
(-40~85
C)
Part Name
Function
Part Name
Function
KM68512BLT-5L
KM68512BLT-7L
32-TSOP1-F, 55ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
KM68512BLTI-7L
32-TSOP1-F, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
1. X means don
t care.(Must be low or high state)
CS
1
CS
2
OE
WE
I/O Pin
Mode
Power
H
X
1)
X
1)
X
1)
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
L
Din
Write
Active
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper ation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect r eliability.
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
V
IN
,V
OUT
-0.5 to 7.0
V
-
Voltage on Vcc supply relative to Vss
V
CC
-0.5 to 7.0
V
-
Power Dissipation
P
D
1.0
W
-
Storage temperature
T
STG
-65 to 150
C
-
Operating Temperature
T
A
0 to 70
C
KM68512BL
-40 to 85
C
KM68512BLI
Soldering temperature and time
T
SOLDER
260
C, 10sec(Lead Only)
-
-
Revision 0.0
KM68512B Family
CMOS SRAM
January 1998
4
Advance
RECOMMENDED DC OPERATING CONDITIONS
1)
Note
1. Commercial Product : T
A
=0 to 70
C, unless otherwise specified
Industrial Product : T
A
=-40 to 85
C, unless otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
30ns
3. Undershoot : -3.0V in case of pulse width
30ns
4. Overshoot and undershoot is sampled, not 100% tested
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
2.2
-
Vcc+0.5V
2)
V
Input low voltage
V
IL
-0.5
3)
-
0.8
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
6
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
8
pF
DC AND OPERATING CHARACTERISTICS
1. Industrial product = 15
A
Item
Symbol
Test Conditions
Min Typ Max Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or
WE=V
IL
, V
IO
=Vss to Vcc
-1
-
1
A
Operating power supply
I
CC
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or
V
IH
, Read
-
7
10
mA
Average operating current
I
CC1
Cycle time=1
, 100% duty, I
IO
=0mA
CS
1
0.2V, CS
2
V
CC
-0.2V, V
IN
0.2V or V
IN
Vcc -0.2V
Read
-
-
5
mA
Write
-
-
30
mA
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
-
-
60
mA
Output low voltage
V
OL
I
OL
=2.1mA
-
-
0.4
V
Output high voltage
V
OH
I
OH
=-1.0mA
2.4
-
-
V
Standby Current(TTL)
I
SB
CS
1
=V
IH
, CS
2
=V
IL
,
Other inputs =V
IL
or V
IH
-
-
3
mA
Standby Current (CMOS)
I
SB1
CS
1
Vcc-0.2V, CS
2
Vcc-0.2V or CS
2
0.2V
-
1
10
1)
A
Revision 0.0
KM68512B Family
CMOS SRAM
January 1998
5
Advance
AC CHARACTERISTICS
(Vcc=4.5~5.5V,
KM68512B Family : T
A
=0 to 70
C, KM68512BI Family : T
A
=-40 to 85
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
ns
Output disable to high-Z output
t
OHZ
0
20
0
25
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
55
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
20
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and faling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
DATA RETENTION CHARACTERISTICS
1. CS
1
Vcc-0.2V, CS
2
Vcc-0.2V( CS
1
controlled) or CS
2
0.2V(CS
2
controlled).
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
1)
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V, CS
1
Vcc-0.2V
KM68512BL-L
-
0.5
10
A
KM68512BLI-L
-
-
15
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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